xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll (revision d8d131dfa99762ccdd2116661980b7d0493cd7b5) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s
6
7define <vscale x 1 x i32> @vnsra_wx_i64_nxv1i32(<vscale x 1 x i64> %va, i64 %b) {
8; CHECK-LABEL: vnsra_wx_i64_nxv1i32:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
11; CHECK-NEXT:    vnsra.wx v8, v8, a0
12; CHECK-NEXT:    ret
13  %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
14  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
15  %x = ashr <vscale x 1 x i64> %va, %splat
16  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
17  ret <vscale x 1 x i32> %y
18}
19
20define <vscale x 2 x i32> @vnsra_wx_i64_nxv2i32(<vscale x 2 x i64> %va, i64 %b) {
21; CHECK-LABEL: vnsra_wx_i64_nxv2i32:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
24; CHECK-NEXT:    vnsra.wx v10, v8, a0
25; CHECK-NEXT:    vmv.v.v v8, v10
26; CHECK-NEXT:    ret
27  %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
28  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
29  %x = ashr <vscale x 2 x i64> %va, %splat
30  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
31  ret <vscale x 2 x i32> %y
32}
33
34define <vscale x 4 x i32> @vnsra_wx_i64_nxv4i32(<vscale x 4 x i64> %va, i64 %b) {
35; CHECK-LABEL: vnsra_wx_i64_nxv4i32:
36; CHECK:       # %bb.0:
37; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
38; CHECK-NEXT:    vnsra.wx v12, v8, a0
39; CHECK-NEXT:    vmv.v.v v8, v12
40; CHECK-NEXT:    ret
41  %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
42  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
43  %x = ashr <vscale x 4 x i64> %va, %splat
44  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
45  ret <vscale x 4 x i32> %y
46}
47
48define <vscale x 8 x i32> @vnsra_wx_i64_nxv8i32(<vscale x 8 x i64> %va, i64 %b) {
49; CHECK-LABEL: vnsra_wx_i64_nxv8i32:
50; CHECK:       # %bb.0:
51; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
52; CHECK-NEXT:    vnsra.wx v16, v8, a0
53; CHECK-NEXT:    vmv.v.v v8, v16
54; CHECK-NEXT:    ret
55  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
56  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
57  %x = ashr <vscale x 8 x i64> %va, %splat
58  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
59  ret <vscale x 8 x i32> %y
60}
61
62define <vscale x 1 x i32> @vnsra_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
63; CHECK-LABEL: vnsra_wv_nxv1i32_sext:
64; CHECK:       # %bb.0:
65; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
66; CHECK-NEXT:    vnsra.wv v8, v8, v9
67; CHECK-NEXT:    ret
68  %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
69  %x = ashr <vscale x 1 x i64> %va, %vc
70  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
71  ret <vscale x 1 x i32> %y
72}
73
74define <vscale x 1 x i32> @vnsra_wx_i32_nxv1i32_sext(<vscale x 1 x i64> %va, i32 %b) {
75; CHECK-LABEL: vnsra_wx_i32_nxv1i32_sext:
76; CHECK:       # %bb.0:
77; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
78; CHECK-NEXT:    vnsra.wx v8, v8, a0
79; CHECK-NEXT:    ret
80  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
81  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
82  %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
83  %x = ashr <vscale x 1 x i64> %va, %vb
84  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
85  ret <vscale x 1 x i32> %y
86}
87
88define <vscale x 1 x i32> @vnsra_wx_i16_nxv1i32_sext(<vscale x 1 x i64> %va, i16 %b) {
89; CHECK-LABEL: vnsra_wx_i16_nxv1i32_sext:
90; CHECK:       # %bb.0:
91; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
92; CHECK-NEXT:    vnsra.wx v8, v8, a0
93; CHECK-NEXT:    ret
94  %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
95  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
96  %vb = sext <vscale x 1 x i16> %splat to <vscale x 1 x i64>
97  %x = ashr <vscale x 1 x i64> %va, %vb
98  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
99  ret <vscale x 1 x i32> %y
100}
101
102define <vscale x 1 x i32> @vnsra_wx_i8_nxv1i32_sext(<vscale x 1 x i64> %va, i8 %b) {
103; CHECK-LABEL: vnsra_wx_i8_nxv1i32_sext:
104; CHECK:       # %bb.0:
105; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
106; CHECK-NEXT:    vnsra.wx v8, v8, a0
107; CHECK-NEXT:    ret
108  %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
109  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
110  %vb = sext <vscale x 1 x i8> %splat to <vscale x 1 x i64>
111  %x = ashr <vscale x 1 x i64> %va, %vb
112  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
113  ret <vscale x 1 x i32> %y
114}
115
116define <vscale x 1 x i32> @vnsra_wi_i32_nxv1i32_sext(<vscale x 1 x i64> %va) {
117; CHECK-LABEL: vnsra_wi_i32_nxv1i32_sext:
118; CHECK:       # %bb.0:
119; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
120; CHECK-NEXT:    vnsrl.wi v8, v8, 15
121; CHECK-NEXT:    ret
122  %vb = sext <vscale x 1 x i32> splat (i32 15) to <vscale x 1 x i64>
123  %x = ashr <vscale x 1 x i64> %va, %vb
124  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
125  ret <vscale x 1 x i32> %y
126}
127
128define <vscale x 2 x i32> @vnsra_wv_nxv2i32_sext(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
129; CHECK-LABEL: vnsra_wv_nxv2i32_sext:
130; CHECK:       # %bb.0:
131; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
132; CHECK-NEXT:    vnsra.wv v11, v8, v10
133; CHECK-NEXT:    vmv.v.v v8, v11
134; CHECK-NEXT:    ret
135  %vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
136  %x = ashr <vscale x 2 x i64> %va, %vc
137  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
138  ret <vscale x 2 x i32> %y
139}
140
141define <vscale x 2 x i32> @vnsra_wx_i32_nxv2i32_sext(<vscale x 2 x i64> %va, i32 %b) {
142; CHECK-LABEL: vnsra_wx_i32_nxv2i32_sext:
143; CHECK:       # %bb.0:
144; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
145; CHECK-NEXT:    vnsra.wx v10, v8, a0
146; CHECK-NEXT:    vmv.v.v v8, v10
147; CHECK-NEXT:    ret
148  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
149  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
150  %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
151  %x = ashr <vscale x 2 x i64> %va, %vb
152  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
153  ret <vscale x 2 x i32> %y
154}
155
156define <vscale x 2 x i32> @vnsra_wx_i16_nxv2i32_sext(<vscale x 2 x i64> %va, i16 %b) {
157; CHECK-LABEL: vnsra_wx_i16_nxv2i32_sext:
158; CHECK:       # %bb.0:
159; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
160; CHECK-NEXT:    vnsra.wx v10, v8, a0
161; CHECK-NEXT:    vmv.v.v v8, v10
162; CHECK-NEXT:    ret
163  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
164  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
165  %vb = sext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
166  %x = ashr <vscale x 2 x i64> %va, %vb
167  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
168  ret <vscale x 2 x i32> %y
169}
170
171define <vscale x 2 x i32> @vnsra_wx_i8_nxv2i32_sext(<vscale x 2 x i64> %va, i8 %b) {
172; CHECK-LABEL: vnsra_wx_i8_nxv2i32_sext:
173; CHECK:       # %bb.0:
174; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
175; CHECK-NEXT:    vnsra.wx v10, v8, a0
176; CHECK-NEXT:    vmv.v.v v8, v10
177; CHECK-NEXT:    ret
178  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
179  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
180  %vb = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
181  %x = ashr <vscale x 2 x i64> %va, %vb
182  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
183  ret <vscale x 2 x i32> %y
184}
185
186define <vscale x 2 x i32> @vnsra_wi_i32_nxv2i32_sext(<vscale x 2 x i64> %va) {
187; CHECK-LABEL: vnsra_wi_i32_nxv2i32_sext:
188; CHECK:       # %bb.0:
189; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
190; CHECK-NEXT:    vnsrl.wi v10, v8, 15
191; CHECK-NEXT:    vmv.v.v v8, v10
192; CHECK-NEXT:    ret
193  %vb = sext <vscale x 2 x i32> splat (i32 15) to <vscale x 2 x i64>
194  %x = ashr <vscale x 2 x i64> %va, %vb
195  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
196  ret <vscale x 2 x i32> %y
197}
198
199define <vscale x 4 x i32> @vnsra_wv_nxv4i32_sext(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
200; CHECK-LABEL: vnsra_wv_nxv4i32_sext:
201; CHECK:       # %bb.0:
202; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
203; CHECK-NEXT:    vnsra.wv v14, v8, v12
204; CHECK-NEXT:    vmv.v.v v8, v14
205; CHECK-NEXT:    ret
206  %vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
207  %x = ashr <vscale x 4 x i64> %va, %vc
208  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
209  ret <vscale x 4 x i32> %y
210}
211
212define <vscale x 4 x i32> @vnsra_wx_i32_nxv4i32_sext(<vscale x 4 x i64> %va, i32 %b) {
213; CHECK-LABEL: vnsra_wx_i32_nxv4i32_sext:
214; CHECK:       # %bb.0:
215; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
216; CHECK-NEXT:    vnsra.wx v12, v8, a0
217; CHECK-NEXT:    vmv.v.v v8, v12
218; CHECK-NEXT:    ret
219  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
220  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
221  %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
222  %x = ashr <vscale x 4 x i64> %va, %vb
223  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
224  ret <vscale x 4 x i32> %y
225}
226
227define <vscale x 4 x i32> @vnsra_wx_i16_nxv4i32_sext(<vscale x 4 x i64> %va, i16 %b) {
228; CHECK-LABEL: vnsra_wx_i16_nxv4i32_sext:
229; CHECK:       # %bb.0:
230; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
231; CHECK-NEXT:    vnsra.wx v12, v8, a0
232; CHECK-NEXT:    vmv.v.v v8, v12
233; CHECK-NEXT:    ret
234  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
235  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
236  %vb = sext <vscale x 4 x i16> %splat to <vscale x 4 x i64>
237  %x = ashr <vscale x 4 x i64> %va, %vb
238  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
239  ret <vscale x 4 x i32> %y
240}
241
242define <vscale x 4 x i32> @vnsra_wx_i8_nxv4i32_sext(<vscale x 4 x i64> %va, i8 %b) {
243; CHECK-LABEL: vnsra_wx_i8_nxv4i32_sext:
244; CHECK:       # %bb.0:
245; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
246; CHECK-NEXT:    vnsra.wx v12, v8, a0
247; CHECK-NEXT:    vmv.v.v v8, v12
248; CHECK-NEXT:    ret
249  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
250  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
251  %vb = sext <vscale x 4 x i8> %splat to <vscale x 4 x i64>
252  %x = ashr <vscale x 4 x i64> %va, %vb
253  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
254  ret <vscale x 4 x i32> %y
255}
256
257define <vscale x 4 x i32> @vnsra_wi_i32_nxv4i32_sext(<vscale x 4 x i64> %va) {
258; CHECK-LABEL: vnsra_wi_i32_nxv4i32_sext:
259; CHECK:       # %bb.0:
260; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
261; CHECK-NEXT:    vnsrl.wi v12, v8, 15
262; CHECK-NEXT:    vmv.v.v v8, v12
263; CHECK-NEXT:    ret
264  %vb = sext <vscale x 4 x i32> splat (i32 15) to <vscale x 4 x i64>
265  %x = ashr <vscale x 4 x i64> %va, %vb
266  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
267  ret <vscale x 4 x i32> %y
268}
269
270define <vscale x 8 x i32> @vnsra_wv_nxv8i32_sext(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
271; CHECK-LABEL: vnsra_wv_nxv8i32_sext:
272; CHECK:       # %bb.0:
273; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
274; CHECK-NEXT:    vnsra.wv v20, v8, v16
275; CHECK-NEXT:    vmv.v.v v8, v20
276; CHECK-NEXT:    ret
277  %vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
278  %x = ashr <vscale x 8 x i64> %va, %vc
279  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
280  ret <vscale x 8 x i32> %y
281}
282
283define <vscale x 8 x i32> @vnsra_wx_i32_nxv8i32_sext(<vscale x 8 x i64> %va, i32 %b) {
284; CHECK-LABEL: vnsra_wx_i32_nxv8i32_sext:
285; CHECK:       # %bb.0:
286; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
287; CHECK-NEXT:    vnsra.wx v16, v8, a0
288; CHECK-NEXT:    vmv.v.v v8, v16
289; CHECK-NEXT:    ret
290  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
291  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
292  %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
293  %x = ashr <vscale x 8 x i64> %va, %vb
294  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
295  ret <vscale x 8 x i32> %y
296}
297
298define <vscale x 8 x i32> @vnsra_wx_i16_nxv8i32_sext(<vscale x 8 x i64> %va, i16 %b) {
299; CHECK-LABEL: vnsra_wx_i16_nxv8i32_sext:
300; CHECK:       # %bb.0:
301; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
302; CHECK-NEXT:    vnsra.wx v16, v8, a0
303; CHECK-NEXT:    vmv.v.v v8, v16
304; CHECK-NEXT:    ret
305  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
306  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
307  %vb = sext <vscale x 8 x i16> %splat to <vscale x 8 x i64>
308  %x = ashr <vscale x 8 x i64> %va, %vb
309  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
310  ret <vscale x 8 x i32> %y
311}
312
313define <vscale x 8 x i32> @vnsra_wx_i8_nxv8i32_sext(<vscale x 8 x i64> %va, i8 %b) {
314; CHECK-LABEL: vnsra_wx_i8_nxv8i32_sext:
315; CHECK:       # %bb.0:
316; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
317; CHECK-NEXT:    vnsra.wx v16, v8, a0
318; CHECK-NEXT:    vmv.v.v v8, v16
319; CHECK-NEXT:    ret
320  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
321  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
322  %vb = sext <vscale x 8 x i8> %splat to <vscale x 8 x i64>
323  %x = ashr <vscale x 8 x i64> %va, %vb
324  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
325  ret <vscale x 8 x i32> %y
326}
327
328define <vscale x 8 x i32> @vnsra_wi_i32_nxv8i32_sext(<vscale x 8 x i64> %va) {
329; CHECK-LABEL: vnsra_wi_i32_nxv8i32_sext:
330; CHECK:       # %bb.0:
331; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
332; CHECK-NEXT:    vnsrl.wi v16, v8, 15
333; CHECK-NEXT:    vmv.v.v v8, v16
334; CHECK-NEXT:    ret
335  %vb = sext <vscale x 8 x i32> splat (i32 15) to <vscale x 8 x i64>
336  %x = ashr <vscale x 8 x i64> %va, %vb
337  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
338  ret <vscale x 8 x i32> %y
339}
340
341define <vscale x 1 x i32> @vnsra_wv_nxv1i32_zext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
342; CHECK-LABEL: vnsra_wv_nxv1i32_zext:
343; CHECK:       # %bb.0:
344; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
345; CHECK-NEXT:    vnsra.wv v8, v8, v9
346; CHECK-NEXT:    ret
347  %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
348  %x = ashr <vscale x 1 x i64> %va, %vc
349  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
350  ret <vscale x 1 x i32> %y
351}
352
353define <vscale x 1 x i32> @vnsra_wx_i32_nxv1i32_zext(<vscale x 1 x i64> %va, i32 %b) {
354; CHECK-LABEL: vnsra_wx_i32_nxv1i32_zext:
355; CHECK:       # %bb.0:
356; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
357; CHECK-NEXT:    vnsra.wx v8, v8, a0
358; CHECK-NEXT:    ret
359  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
360  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
361  %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
362  %x = ashr <vscale x 1 x i64> %va, %vb
363  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
364  ret <vscale x 1 x i32> %y
365}
366
367define <vscale x 1 x i32> @vnsra_wx_i16_nxv1i32_zext(<vscale x 1 x i64> %va, i16 %b) {
368; CHECK-LABEL: vnsra_wx_i16_nxv1i32_zext:
369; CHECK:       # %bb.0:
370; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
371; CHECK-NEXT:    vnsra.wx v8, v8, a0
372; CHECK-NEXT:    ret
373  %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
374  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
375  %vb = zext <vscale x 1 x i16> %splat to <vscale x 1 x i64>
376  %x = ashr <vscale x 1 x i64> %va, %vb
377  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
378  ret <vscale x 1 x i32> %y
379}
380
381define <vscale x 1 x i32> @vnsra_wx_i8_nxv1i32_zext(<vscale x 1 x i64> %va, i8 %b) {
382; CHECK-LABEL: vnsra_wx_i8_nxv1i32_zext:
383; CHECK:       # %bb.0:
384; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
385; CHECK-NEXT:    vnsra.wx v8, v8, a0
386; CHECK-NEXT:    ret
387  %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
388  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
389  %vb = zext <vscale x 1 x i8> %splat to <vscale x 1 x i64>
390  %x = ashr <vscale x 1 x i64> %va, %vb
391  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
392  ret <vscale x 1 x i32> %y
393}
394
395define <vscale x 1 x i32> @vnsra_wi_i32_nxv1i32_zext(<vscale x 1 x i64> %va) {
396; CHECK-LABEL: vnsra_wi_i32_nxv1i32_zext:
397; CHECK:       # %bb.0:
398; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
399; CHECK-NEXT:    vnsrl.wi v8, v8, 15
400; CHECK-NEXT:    ret
401  %vb = zext <vscale x 1 x i32> splat (i32 15) to <vscale x 1 x i64>
402  %x = ashr <vscale x 1 x i64> %va, %vb
403  %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
404  ret <vscale x 1 x i32> %y
405}
406
407define <vscale x 2 x i32> @vnsra_wv_nxv2i32_zext(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
408; CHECK-LABEL: vnsra_wv_nxv2i32_zext:
409; CHECK:       # %bb.0:
410; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
411; CHECK-NEXT:    vnsra.wv v11, v8, v10
412; CHECK-NEXT:    vmv.v.v v8, v11
413; CHECK-NEXT:    ret
414  %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
415  %x = ashr <vscale x 2 x i64> %va, %vc
416  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
417  ret <vscale x 2 x i32> %y
418}
419
420define <vscale x 2 x i32> @vnsra_wx_i32_nxv2i32_zext(<vscale x 2 x i64> %va, i32 %b) {
421; CHECK-LABEL: vnsra_wx_i32_nxv2i32_zext:
422; CHECK:       # %bb.0:
423; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
424; CHECK-NEXT:    vnsra.wx v10, v8, a0
425; CHECK-NEXT:    vmv.v.v v8, v10
426; CHECK-NEXT:    ret
427  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
428  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
429  %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
430  %x = ashr <vscale x 2 x i64> %va, %vb
431  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
432  ret <vscale x 2 x i32> %y
433}
434
435define <vscale x 2 x i32> @vnsra_wx_i16_nxv2i32_zext(<vscale x 2 x i64> %va, i16 %b) {
436; CHECK-LABEL: vnsra_wx_i16_nxv2i32_zext:
437; CHECK:       # %bb.0:
438; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
439; CHECK-NEXT:    vnsra.wx v10, v8, a0
440; CHECK-NEXT:    vmv.v.v v8, v10
441; CHECK-NEXT:    ret
442  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
443  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
444  %vb = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
445  %x = ashr <vscale x 2 x i64> %va, %vb
446  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
447  ret <vscale x 2 x i32> %y
448}
449
450define <vscale x 2 x i32> @vnsra_wx_i8_nxv2i32_zext(<vscale x 2 x i64> %va, i8 %b) {
451; CHECK-LABEL: vnsra_wx_i8_nxv2i32_zext:
452; CHECK:       # %bb.0:
453; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
454; CHECK-NEXT:    vnsra.wx v10, v8, a0
455; CHECK-NEXT:    vmv.v.v v8, v10
456; CHECK-NEXT:    ret
457  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
458  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
459  %vb = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
460  %x = ashr <vscale x 2 x i64> %va, %vb
461  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
462  ret <vscale x 2 x i32> %y
463}
464
465define <vscale x 2 x i32> @vnsra_wi_i32_nxv2i32_zext(<vscale x 2 x i64> %va) {
466; CHECK-LABEL: vnsra_wi_i32_nxv2i32_zext:
467; CHECK:       # %bb.0:
468; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
469; CHECK-NEXT:    vnsrl.wi v10, v8, 15
470; CHECK-NEXT:    vmv.v.v v8, v10
471; CHECK-NEXT:    ret
472  %vb = zext <vscale x 2 x i32> splat (i32 15) to <vscale x 2 x i64>
473  %x = ashr <vscale x 2 x i64> %va, %vb
474  %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
475  ret <vscale x 2 x i32> %y
476}
477
478define <vscale x 4 x i32> @vnsra_wv_nxv4i32_zext(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
479; CHECK-LABEL: vnsra_wv_nxv4i32_zext:
480; CHECK:       # %bb.0:
481; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
482; CHECK-NEXT:    vnsra.wv v14, v8, v12
483; CHECK-NEXT:    vmv.v.v v8, v14
484; CHECK-NEXT:    ret
485  %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
486  %x = ashr <vscale x 4 x i64> %va, %vc
487  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
488  ret <vscale x 4 x i32> %y
489}
490
491define <vscale x 4 x i32> @vnsra_wx_i32_nxv4i32_zext(<vscale x 4 x i64> %va, i32 %b) {
492; CHECK-LABEL: vnsra_wx_i32_nxv4i32_zext:
493; CHECK:       # %bb.0:
494; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
495; CHECK-NEXT:    vnsra.wx v12, v8, a0
496; CHECK-NEXT:    vmv.v.v v8, v12
497; CHECK-NEXT:    ret
498  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
499  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
500  %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
501  %x = ashr <vscale x 4 x i64> %va, %vb
502  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
503  ret <vscale x 4 x i32> %y
504}
505
506define <vscale x 4 x i32> @vnsra_wx_i16_nxv4i32_zext(<vscale x 4 x i64> %va, i16 %b) {
507; CHECK-LABEL: vnsra_wx_i16_nxv4i32_zext:
508; CHECK:       # %bb.0:
509; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
510; CHECK-NEXT:    vnsra.wx v12, v8, a0
511; CHECK-NEXT:    vmv.v.v v8, v12
512; CHECK-NEXT:    ret
513  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
514  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
515  %vb = zext <vscale x 4 x i16> %splat to <vscale x 4 x i64>
516  %x = ashr <vscale x 4 x i64> %va, %vb
517  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
518  ret <vscale x 4 x i32> %y
519}
520
521define <vscale x 4 x i32> @vnsra_wx_i8_nxv4i32_zext(<vscale x 4 x i64> %va, i8 %b) {
522; CHECK-LABEL: vnsra_wx_i8_nxv4i32_zext:
523; CHECK:       # %bb.0:
524; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
525; CHECK-NEXT:    vnsra.wx v12, v8, a0
526; CHECK-NEXT:    vmv.v.v v8, v12
527; CHECK-NEXT:    ret
528  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
529  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
530  %vb = zext <vscale x 4 x i8> %splat to <vscale x 4 x i64>
531  %x = ashr <vscale x 4 x i64> %va, %vb
532  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
533  ret <vscale x 4 x i32> %y
534}
535
536define <vscale x 4 x i32> @vnsra_wi_i32_nxv4i32_zext(<vscale x 4 x i64> %va) {
537; CHECK-LABEL: vnsra_wi_i32_nxv4i32_zext:
538; CHECK:       # %bb.0:
539; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
540; CHECK-NEXT:    vnsrl.wi v12, v8, 15
541; CHECK-NEXT:    vmv.v.v v8, v12
542; CHECK-NEXT:    ret
543  %vb = zext <vscale x 4 x i32> splat (i32 15) to <vscale x 4 x i64>
544  %x = ashr <vscale x 4 x i64> %va, %vb
545  %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
546  ret <vscale x 4 x i32> %y
547}
548
549define <vscale x 8 x i32> @vnsra_wv_nxv8i32_zext(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
550; CHECK-LABEL: vnsra_wv_nxv8i32_zext:
551; CHECK:       # %bb.0:
552; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
553; CHECK-NEXT:    vnsra.wv v20, v8, v16
554; CHECK-NEXT:    vmv.v.v v8, v20
555; CHECK-NEXT:    ret
556  %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
557  %x = ashr <vscale x 8 x i64> %va, %vc
558  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
559  ret <vscale x 8 x i32> %y
560}
561
562define <vscale x 8 x i32> @vnsra_wx_i32_nxv8i32_zext(<vscale x 8 x i64> %va, i32 %b) {
563; CHECK-LABEL: vnsra_wx_i32_nxv8i32_zext:
564; CHECK:       # %bb.0:
565; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
566; CHECK-NEXT:    vnsra.wx v16, v8, a0
567; CHECK-NEXT:    vmv.v.v v8, v16
568; CHECK-NEXT:    ret
569  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
570  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
571  %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
572  %x = ashr <vscale x 8 x i64> %va, %vb
573  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
574  ret <vscale x 8 x i32> %y
575}
576
577define <vscale x 8 x i32> @vnsra_wx_i16_nxv8i32_zext(<vscale x 8 x i64> %va, i16 %b) {
578; CHECK-LABEL: vnsra_wx_i16_nxv8i32_zext:
579; CHECK:       # %bb.0:
580; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
581; CHECK-NEXT:    vnsra.wx v16, v8, a0
582; CHECK-NEXT:    vmv.v.v v8, v16
583; CHECK-NEXT:    ret
584  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
585  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
586  %vb = zext <vscale x 8 x i16> %splat to <vscale x 8 x i64>
587  %x = ashr <vscale x 8 x i64> %va, %vb
588  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
589  ret <vscale x 8 x i32> %y
590}
591
592define <vscale x 8 x i32> @vnsra_wx_i8_nxv8i32_zext(<vscale x 8 x i64> %va, i8 %b) {
593; CHECK-LABEL: vnsra_wx_i8_nxv8i32_zext:
594; CHECK:       # %bb.0:
595; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
596; CHECK-NEXT:    vnsra.wx v16, v8, a0
597; CHECK-NEXT:    vmv.v.v v8, v16
598; CHECK-NEXT:    ret
599  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
600  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
601  %vb = zext <vscale x 8 x i8> %splat to <vscale x 8 x i64>
602  %x = ashr <vscale x 8 x i64> %va, %vb
603  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
604  ret <vscale x 8 x i32> %y
605}
606
607define <vscale x 8 x i32> @vnsra_wi_i32_nxv8i32_zext(<vscale x 8 x i64> %va) {
608; CHECK-LABEL: vnsra_wi_i32_nxv8i32_zext:
609; CHECK:       # %bb.0:
610; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
611; CHECK-NEXT:    vnsrl.wi v16, v8, 15
612; CHECK-NEXT:    vmv.v.v v8, v16
613; CHECK-NEXT:    ret
614  %vb = zext <vscale x 8 x i32> splat (i32 15) to <vscale x 8 x i64>
615  %x = ashr <vscale x 8 x i64> %va, %vb
616  %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
617  ret <vscale x 8 x i32> %y
618}
619