xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll (revision 1cb599835ccf7ee8b2d1d5a7f3107e19a26fc6f5) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \
3; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \
5; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s
6
7declare <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16(
8  <vscale x 1 x half>,
9  <vscale x 1 x half>,
10  iXLen, iXLen);
11
12define <vscale x 1 x half> @intrinsic_vfsqrt_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
13; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f16_nxv1f16:
14; CHECK:       # %bb.0: # %entry
15; CHECK-NEXT:    fsrmi a1, 0
16; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
17; CHECK-NEXT:    vfsqrt.v v8, v8
18; CHECK-NEXT:    fsrm a1
19; CHECK-NEXT:    ret
20entry:
21  %a = call <vscale x 1 x half> @llvm.riscv.vfsqrt.nxv1f16(
22    <vscale x 1 x half> undef,
23    <vscale x 1 x half> %0,
24    iXLen 0, iXLen %1)
25
26  ret <vscale x 1 x half> %a
27}
28
29declare <vscale x 1 x half> @llvm.riscv.vfsqrt.mask.nxv1f16(
30  <vscale x 1 x half>,
31  <vscale x 1 x half>,
32  <vscale x 1 x i1>,
33  iXLen, iXLen, iXLen);
34
35define <vscale x 1 x half> @intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
36; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16:
37; CHECK:       # %bb.0: # %entry
38; CHECK-NEXT:    fsrmi a1, 0
39; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu
40; CHECK-NEXT:    vfsqrt.v v8, v9, v0.t
41; CHECK-NEXT:    fsrm a1
42; CHECK-NEXT:    ret
43entry:
44  %a = call <vscale x 1 x half> @llvm.riscv.vfsqrt.mask.nxv1f16(
45    <vscale x 1 x half> %0,
46    <vscale x 1 x half> %1,
47    <vscale x 1 x i1> %2,
48    iXLen 0, iXLen %3, iXLen 1)
49
50  ret <vscale x 1 x half> %a
51}
52
53declare <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16(
54  <vscale x 2 x half>,
55  <vscale x 2 x half>,
56  iXLen, iXLen);
57
58define <vscale x 2 x half> @intrinsic_vfsqrt_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
59; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f16_nxv2f16:
60; CHECK:       # %bb.0: # %entry
61; CHECK-NEXT:    fsrmi a1, 0
62; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
63; CHECK-NEXT:    vfsqrt.v v8, v8
64; CHECK-NEXT:    fsrm a1
65; CHECK-NEXT:    ret
66entry:
67  %a = call <vscale x 2 x half> @llvm.riscv.vfsqrt.nxv2f16(
68    <vscale x 2 x half> undef,
69    <vscale x 2 x half> %0,
70    iXLen 0, iXLen %1)
71
72  ret <vscale x 2 x half> %a
73}
74
75declare <vscale x 2 x half> @llvm.riscv.vfsqrt.mask.nxv2f16(
76  <vscale x 2 x half>,
77  <vscale x 2 x half>,
78  <vscale x 2 x i1>,
79  iXLen, iXLen, iXLen);
80
81define <vscale x 2 x half> @intrinsic_vfsqrt_mask_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
82; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f16_nxv2f16:
83; CHECK:       # %bb.0: # %entry
84; CHECK-NEXT:    fsrmi a1, 0
85; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu
86; CHECK-NEXT:    vfsqrt.v v8, v9, v0.t
87; CHECK-NEXT:    fsrm a1
88; CHECK-NEXT:    ret
89entry:
90  %a = call <vscale x 2 x half> @llvm.riscv.vfsqrt.mask.nxv2f16(
91    <vscale x 2 x half> %0,
92    <vscale x 2 x half> %1,
93    <vscale x 2 x i1> %2,
94    iXLen 0, iXLen %3, iXLen 1)
95
96  ret <vscale x 2 x half> %a
97}
98
99declare <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16(
100  <vscale x 4 x half>,
101  <vscale x 4 x half>,
102  iXLen, iXLen);
103
104define <vscale x 4 x half> @intrinsic_vfsqrt_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
105; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f16_nxv4f16:
106; CHECK:       # %bb.0: # %entry
107; CHECK-NEXT:    fsrmi a1, 0
108; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
109; CHECK-NEXT:    vfsqrt.v v8, v8
110; CHECK-NEXT:    fsrm a1
111; CHECK-NEXT:    ret
112entry:
113  %a = call <vscale x 4 x half> @llvm.riscv.vfsqrt.nxv4f16(
114    <vscale x 4 x half> undef,
115    <vscale x 4 x half> %0,
116    iXLen 0, iXLen %1)
117
118  ret <vscale x 4 x half> %a
119}
120
121declare <vscale x 4 x half> @llvm.riscv.vfsqrt.mask.nxv4f16(
122  <vscale x 4 x half>,
123  <vscale x 4 x half>,
124  <vscale x 4 x i1>,
125  iXLen, iXLen, iXLen);
126
127define <vscale x 4 x half> @intrinsic_vfsqrt_mask_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
128; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f16_nxv4f16:
129; CHECK:       # %bb.0: # %entry
130; CHECK-NEXT:    fsrmi a1, 0
131; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu
132; CHECK-NEXT:    vfsqrt.v v8, v9, v0.t
133; CHECK-NEXT:    fsrm a1
134; CHECK-NEXT:    ret
135entry:
136  %a = call <vscale x 4 x half> @llvm.riscv.vfsqrt.mask.nxv4f16(
137    <vscale x 4 x half> %0,
138    <vscale x 4 x half> %1,
139    <vscale x 4 x i1> %2,
140    iXLen 0, iXLen %3, iXLen 1)
141
142  ret <vscale x 4 x half> %a
143}
144
145declare <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16(
146  <vscale x 8 x half>,
147  <vscale x 8 x half>,
148  iXLen, iXLen);
149
150define <vscale x 8 x half> @intrinsic_vfsqrt_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
151; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f16_nxv8f16:
152; CHECK:       # %bb.0: # %entry
153; CHECK-NEXT:    fsrmi a1, 0
154; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
155; CHECK-NEXT:    vfsqrt.v v8, v8
156; CHECK-NEXT:    fsrm a1
157; CHECK-NEXT:    ret
158entry:
159  %a = call <vscale x 8 x half> @llvm.riscv.vfsqrt.nxv8f16(
160    <vscale x 8 x half> undef,
161    <vscale x 8 x half> %0,
162    iXLen 0, iXLen %1)
163
164  ret <vscale x 8 x half> %a
165}
166
167declare <vscale x 8 x half> @llvm.riscv.vfsqrt.mask.nxv8f16(
168  <vscale x 8 x half>,
169  <vscale x 8 x half>,
170  <vscale x 8 x i1>,
171  iXLen, iXLen, iXLen);
172
173define <vscale x 8 x half> @intrinsic_vfsqrt_mask_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
174; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f16_nxv8f16:
175; CHECK:       # %bb.0: # %entry
176; CHECK-NEXT:    fsrmi a1, 0
177; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu
178; CHECK-NEXT:    vfsqrt.v v8, v10, v0.t
179; CHECK-NEXT:    fsrm a1
180; CHECK-NEXT:    ret
181entry:
182  %a = call <vscale x 8 x half> @llvm.riscv.vfsqrt.mask.nxv8f16(
183    <vscale x 8 x half> %0,
184    <vscale x 8 x half> %1,
185    <vscale x 8 x i1> %2,
186    iXLen 0, iXLen %3, iXLen 1)
187
188  ret <vscale x 8 x half> %a
189}
190
191declare <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16(
192  <vscale x 16 x half>,
193  <vscale x 16 x half>,
194  iXLen, iXLen);
195
196define <vscale x 16 x half> @intrinsic_vfsqrt_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
197; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f16_nxv16f16:
198; CHECK:       # %bb.0: # %entry
199; CHECK-NEXT:    fsrmi a1, 0
200; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
201; CHECK-NEXT:    vfsqrt.v v8, v8
202; CHECK-NEXT:    fsrm a1
203; CHECK-NEXT:    ret
204entry:
205  %a = call <vscale x 16 x half> @llvm.riscv.vfsqrt.nxv16f16(
206    <vscale x 16 x half> undef,
207    <vscale x 16 x half> %0,
208    iXLen 0, iXLen %1)
209
210  ret <vscale x 16 x half> %a
211}
212
213declare <vscale x 16 x half> @llvm.riscv.vfsqrt.mask.nxv16f16(
214  <vscale x 16 x half>,
215  <vscale x 16 x half>,
216  <vscale x 16 x i1>,
217  iXLen, iXLen, iXLen);
218
219define <vscale x 16 x half> @intrinsic_vfsqrt_mask_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
220; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv16f16_nxv16f16:
221; CHECK:       # %bb.0: # %entry
222; CHECK-NEXT:    fsrmi a1, 0
223; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu
224; CHECK-NEXT:    vfsqrt.v v8, v12, v0.t
225; CHECK-NEXT:    fsrm a1
226; CHECK-NEXT:    ret
227entry:
228  %a = call <vscale x 16 x half> @llvm.riscv.vfsqrt.mask.nxv16f16(
229    <vscale x 16 x half> %0,
230    <vscale x 16 x half> %1,
231    <vscale x 16 x i1> %2,
232    iXLen 0, iXLen %3, iXLen 1)
233
234  ret <vscale x 16 x half> %a
235}
236
237declare <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16(
238  <vscale x 32 x half>,
239  <vscale x 32 x half>,
240  iXLen, iXLen);
241
242define <vscale x 32 x half> @intrinsic_vfsqrt_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {
243; CHECK-LABEL: intrinsic_vfsqrt_v_nxv32f16_nxv32f16:
244; CHECK:       # %bb.0: # %entry
245; CHECK-NEXT:    fsrmi a1, 0
246; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
247; CHECK-NEXT:    vfsqrt.v v8, v8
248; CHECK-NEXT:    fsrm a1
249; CHECK-NEXT:    ret
250entry:
251  %a = call <vscale x 32 x half> @llvm.riscv.vfsqrt.nxv32f16(
252    <vscale x 32 x half> undef,
253    <vscale x 32 x half> %0,
254    iXLen 0, iXLen %1)
255
256  ret <vscale x 32 x half> %a
257}
258
259declare <vscale x 32 x half> @llvm.riscv.vfsqrt.mask.nxv32f16(
260  <vscale x 32 x half>,
261  <vscale x 32 x half>,
262  <vscale x 32 x i1>,
263  iXLen, iXLen, iXLen);
264
265define <vscale x 32 x half> @intrinsic_vfsqrt_mask_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
266; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv32f16_nxv32f16:
267; CHECK:       # %bb.0: # %entry
268; CHECK-NEXT:    fsrmi a1, 0
269; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, mu
270; CHECK-NEXT:    vfsqrt.v v8, v16, v0.t
271; CHECK-NEXT:    fsrm a1
272; CHECK-NEXT:    ret
273entry:
274  %a = call <vscale x 32 x half> @llvm.riscv.vfsqrt.mask.nxv32f16(
275    <vscale x 32 x half> %0,
276    <vscale x 32 x half> %1,
277    <vscale x 32 x i1> %2,
278    iXLen 0, iXLen %3, iXLen 1)
279
280  ret <vscale x 32 x half> %a
281}
282
283declare <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32(
284  <vscale x 1 x float>,
285  <vscale x 1 x float>,
286  iXLen, iXLen);
287
288define <vscale x 1 x float> @intrinsic_vfsqrt_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
289; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f32_nxv1f32:
290; CHECK:       # %bb.0: # %entry
291; CHECK-NEXT:    fsrmi a1, 0
292; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
293; CHECK-NEXT:    vfsqrt.v v8, v8
294; CHECK-NEXT:    fsrm a1
295; CHECK-NEXT:    ret
296entry:
297  %a = call <vscale x 1 x float> @llvm.riscv.vfsqrt.nxv1f32(
298    <vscale x 1 x float> undef,
299    <vscale x 1 x float> %0,
300    iXLen 0, iXLen %1)
301
302  ret <vscale x 1 x float> %a
303}
304
305declare <vscale x 1 x float> @llvm.riscv.vfsqrt.mask.nxv1f32(
306  <vscale x 1 x float>,
307  <vscale x 1 x float>,
308  <vscale x 1 x i1>,
309  iXLen, iXLen, iXLen);
310
311define <vscale x 1 x float> @intrinsic_vfsqrt_mask_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
312; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f32_nxv1f32:
313; CHECK:       # %bb.0: # %entry
314; CHECK-NEXT:    fsrmi a1, 0
315; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu
316; CHECK-NEXT:    vfsqrt.v v8, v9, v0.t
317; CHECK-NEXT:    fsrm a1
318; CHECK-NEXT:    ret
319entry:
320  %a = call <vscale x 1 x float> @llvm.riscv.vfsqrt.mask.nxv1f32(
321    <vscale x 1 x float> %0,
322    <vscale x 1 x float> %1,
323    <vscale x 1 x i1> %2,
324    iXLen 0, iXLen %3, iXLen 1)
325
326  ret <vscale x 1 x float> %a
327}
328
329declare <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32(
330  <vscale x 2 x float>,
331  <vscale x 2 x float>,
332  iXLen, iXLen);
333
334define <vscale x 2 x float> @intrinsic_vfsqrt_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
335; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f32_nxv2f32:
336; CHECK:       # %bb.0: # %entry
337; CHECK-NEXT:    fsrmi a1, 0
338; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
339; CHECK-NEXT:    vfsqrt.v v8, v8
340; CHECK-NEXT:    fsrm a1
341; CHECK-NEXT:    ret
342entry:
343  %a = call <vscale x 2 x float> @llvm.riscv.vfsqrt.nxv2f32(
344    <vscale x 2 x float> undef,
345    <vscale x 2 x float> %0,
346    iXLen 0, iXLen %1)
347
348  ret <vscale x 2 x float> %a
349}
350
351declare <vscale x 2 x float> @llvm.riscv.vfsqrt.mask.nxv2f32(
352  <vscale x 2 x float>,
353  <vscale x 2 x float>,
354  <vscale x 2 x i1>,
355  iXLen, iXLen, iXLen);
356
357define <vscale x 2 x float> @intrinsic_vfsqrt_mask_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
358; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f32_nxv2f32:
359; CHECK:       # %bb.0: # %entry
360; CHECK-NEXT:    fsrmi a1, 0
361; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu
362; CHECK-NEXT:    vfsqrt.v v8, v9, v0.t
363; CHECK-NEXT:    fsrm a1
364; CHECK-NEXT:    ret
365entry:
366  %a = call <vscale x 2 x float> @llvm.riscv.vfsqrt.mask.nxv2f32(
367    <vscale x 2 x float> %0,
368    <vscale x 2 x float> %1,
369    <vscale x 2 x i1> %2,
370    iXLen 0, iXLen %3, iXLen 1)
371
372  ret <vscale x 2 x float> %a
373}
374
375declare <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32(
376  <vscale x 4 x float>,
377  <vscale x 4 x float>,
378  iXLen, iXLen);
379
380define <vscale x 4 x float> @intrinsic_vfsqrt_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
381; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f32_nxv4f32:
382; CHECK:       # %bb.0: # %entry
383; CHECK-NEXT:    fsrmi a1, 0
384; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
385; CHECK-NEXT:    vfsqrt.v v8, v8
386; CHECK-NEXT:    fsrm a1
387; CHECK-NEXT:    ret
388entry:
389  %a = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32(
390    <vscale x 4 x float> undef,
391    <vscale x 4 x float> %0,
392    iXLen 0, iXLen %1)
393
394  ret <vscale x 4 x float> %a
395}
396
397declare <vscale x 4 x float> @llvm.riscv.vfsqrt.mask.nxv4f32(
398  <vscale x 4 x float>,
399  <vscale x 4 x float>,
400  <vscale x 4 x i1>,
401  iXLen, iXLen, iXLen);
402
403define <vscale x 4 x float> @intrinsic_vfsqrt_mask_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
404; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f32_nxv4f32:
405; CHECK:       # %bb.0: # %entry
406; CHECK-NEXT:    fsrmi a1, 0
407; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu
408; CHECK-NEXT:    vfsqrt.v v8, v10, v0.t
409; CHECK-NEXT:    fsrm a1
410; CHECK-NEXT:    ret
411entry:
412  %a = call <vscale x 4 x float> @llvm.riscv.vfsqrt.mask.nxv4f32(
413    <vscale x 4 x float> %0,
414    <vscale x 4 x float> %1,
415    <vscale x 4 x i1> %2,
416    iXLen 0, iXLen %3, iXLen 1)
417
418  ret <vscale x 4 x float> %a
419}
420
421declare <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32(
422  <vscale x 8 x float>,
423  <vscale x 8 x float>,
424  iXLen, iXLen);
425
426define <vscale x 8 x float> @intrinsic_vfsqrt_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
427; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f32_nxv8f32:
428; CHECK:       # %bb.0: # %entry
429; CHECK-NEXT:    fsrmi a1, 0
430; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
431; CHECK-NEXT:    vfsqrt.v v8, v8
432; CHECK-NEXT:    fsrm a1
433; CHECK-NEXT:    ret
434entry:
435  %a = call <vscale x 8 x float> @llvm.riscv.vfsqrt.nxv8f32(
436    <vscale x 8 x float> undef,
437    <vscale x 8 x float> %0,
438    iXLen 0, iXLen %1)
439
440  ret <vscale x 8 x float> %a
441}
442
443declare <vscale x 8 x float> @llvm.riscv.vfsqrt.mask.nxv8f32(
444  <vscale x 8 x float>,
445  <vscale x 8 x float>,
446  <vscale x 8 x i1>,
447  iXLen, iXLen, iXLen);
448
449define <vscale x 8 x float> @intrinsic_vfsqrt_mask_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
450; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f32_nxv8f32:
451; CHECK:       # %bb.0: # %entry
452; CHECK-NEXT:    fsrmi a1, 0
453; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu
454; CHECK-NEXT:    vfsqrt.v v8, v12, v0.t
455; CHECK-NEXT:    fsrm a1
456; CHECK-NEXT:    ret
457entry:
458  %a = call <vscale x 8 x float> @llvm.riscv.vfsqrt.mask.nxv8f32(
459    <vscale x 8 x float> %0,
460    <vscale x 8 x float> %1,
461    <vscale x 8 x i1> %2,
462    iXLen 0, iXLen %3, iXLen 1)
463
464  ret <vscale x 8 x float> %a
465}
466
467declare <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32(
468  <vscale x 16 x float>,
469  <vscale x 16 x float>,
470  iXLen, iXLen);
471
472define <vscale x 16 x float> @intrinsic_vfsqrt_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {
473; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f32_nxv16f32:
474; CHECK:       # %bb.0: # %entry
475; CHECK-NEXT:    fsrmi a1, 0
476; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
477; CHECK-NEXT:    vfsqrt.v v8, v8
478; CHECK-NEXT:    fsrm a1
479; CHECK-NEXT:    ret
480entry:
481  %a = call <vscale x 16 x float> @llvm.riscv.vfsqrt.nxv16f32(
482    <vscale x 16 x float> undef,
483    <vscale x 16 x float> %0,
484    iXLen 0, iXLen %1)
485
486  ret <vscale x 16 x float> %a
487}
488
489declare <vscale x 16 x float> @llvm.riscv.vfsqrt.mask.nxv16f32(
490  <vscale x 16 x float>,
491  <vscale x 16 x float>,
492  <vscale x 16 x i1>,
493  iXLen, iXLen, iXLen);
494
495define <vscale x 16 x float> @intrinsic_vfsqrt_mask_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
496; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv16f32_nxv16f32:
497; CHECK:       # %bb.0: # %entry
498; CHECK-NEXT:    fsrmi a1, 0
499; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, mu
500; CHECK-NEXT:    vfsqrt.v v8, v16, v0.t
501; CHECK-NEXT:    fsrm a1
502; CHECK-NEXT:    ret
503entry:
504  %a = call <vscale x 16 x float> @llvm.riscv.vfsqrt.mask.nxv16f32(
505    <vscale x 16 x float> %0,
506    <vscale x 16 x float> %1,
507    <vscale x 16 x i1> %2,
508    iXLen 0, iXLen %3, iXLen 1)
509
510  ret <vscale x 16 x float> %a
511}
512
513declare <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64(
514  <vscale x 1 x double>,
515  <vscale x 1 x double>,
516  iXLen, iXLen);
517
518define <vscale x 1 x double> @intrinsic_vfsqrt_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {
519; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f64_nxv1f64:
520; CHECK:       # %bb.0: # %entry
521; CHECK-NEXT:    fsrmi a1, 0
522; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
523; CHECK-NEXT:    vfsqrt.v v8, v8
524; CHECK-NEXT:    fsrm a1
525; CHECK-NEXT:    ret
526entry:
527  %a = call <vscale x 1 x double> @llvm.riscv.vfsqrt.nxv1f64(
528    <vscale x 1 x double> undef,
529    <vscale x 1 x double> %0,
530    iXLen 0, iXLen %1)
531
532  ret <vscale x 1 x double> %a
533}
534
535declare <vscale x 1 x double> @llvm.riscv.vfsqrt.mask.nxv1f64(
536  <vscale x 1 x double>,
537  <vscale x 1 x double>,
538  <vscale x 1 x i1>,
539  iXLen, iXLen, iXLen);
540
541define <vscale x 1 x double> @intrinsic_vfsqrt_mask_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
542; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f64_nxv1f64:
543; CHECK:       # %bb.0: # %entry
544; CHECK-NEXT:    fsrmi a1, 0
545; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
546; CHECK-NEXT:    vfsqrt.v v8, v9, v0.t
547; CHECK-NEXT:    fsrm a1
548; CHECK-NEXT:    ret
549entry:
550  %a = call <vscale x 1 x double> @llvm.riscv.vfsqrt.mask.nxv1f64(
551    <vscale x 1 x double> %0,
552    <vscale x 1 x double> %1,
553    <vscale x 1 x i1> %2,
554    iXLen 0, iXLen %3, iXLen 1)
555
556  ret <vscale x 1 x double> %a
557}
558
559declare <vscale x 2 x double> @llvm.riscv.vfsqrt.nxv2f64(
560  <vscale x 2 x double>,
561  <vscale x 2 x double>,
562  iXLen, iXLen);
563
564define <vscale x 2 x double> @intrinsic_vfsqrt_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {
565; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f64_nxv2f64:
566; CHECK:       # %bb.0: # %entry
567; CHECK-NEXT:    fsrmi a1, 0
568; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
569; CHECK-NEXT:    vfsqrt.v v8, v8
570; CHECK-NEXT:    fsrm a1
571; CHECK-NEXT:    ret
572entry:
573  %a = call <vscale x 2 x double> @llvm.riscv.vfsqrt.nxv2f64(
574    <vscale x 2 x double> undef,
575    <vscale x 2 x double> %0,
576    iXLen 0, iXLen %1)
577
578  ret <vscale x 2 x double> %a
579}
580
581declare <vscale x 2 x double> @llvm.riscv.vfsqrt.mask.nxv2f64(
582  <vscale x 2 x double>,
583  <vscale x 2 x double>,
584  <vscale x 2 x i1>,
585  iXLen, iXLen, iXLen);
586
587define <vscale x 2 x double> @intrinsic_vfsqrt_mask_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
588; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f64_nxv2f64:
589; CHECK:       # %bb.0: # %entry
590; CHECK-NEXT:    fsrmi a1, 0
591; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu
592; CHECK-NEXT:    vfsqrt.v v8, v10, v0.t
593; CHECK-NEXT:    fsrm a1
594; CHECK-NEXT:    ret
595entry:
596  %a = call <vscale x 2 x double> @llvm.riscv.vfsqrt.mask.nxv2f64(
597    <vscale x 2 x double> %0,
598    <vscale x 2 x double> %1,
599    <vscale x 2 x i1> %2,
600    iXLen 0, iXLen %3, iXLen 1)
601
602  ret <vscale x 2 x double> %a
603}
604
605declare <vscale x 4 x double> @llvm.riscv.vfsqrt.nxv4f64(
606  <vscale x 4 x double>,
607  <vscale x 4 x double>,
608  iXLen, iXLen);
609
610define <vscale x 4 x double> @intrinsic_vfsqrt_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {
611; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f64_nxv4f64:
612; CHECK:       # %bb.0: # %entry
613; CHECK-NEXT:    fsrmi a1, 0
614; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
615; CHECK-NEXT:    vfsqrt.v v8, v8
616; CHECK-NEXT:    fsrm a1
617; CHECK-NEXT:    ret
618entry:
619  %a = call <vscale x 4 x double> @llvm.riscv.vfsqrt.nxv4f64(
620    <vscale x 4 x double> undef,
621    <vscale x 4 x double> %0,
622    iXLen 0, iXLen %1)
623
624  ret <vscale x 4 x double> %a
625}
626
627declare <vscale x 4 x double> @llvm.riscv.vfsqrt.mask.nxv4f64(
628  <vscale x 4 x double>,
629  <vscale x 4 x double>,
630  <vscale x 4 x i1>,
631  iXLen, iXLen, iXLen);
632
633define <vscale x 4 x double> @intrinsic_vfsqrt_mask_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
634; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f64_nxv4f64:
635; CHECK:       # %bb.0: # %entry
636; CHECK-NEXT:    fsrmi a1, 0
637; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu
638; CHECK-NEXT:    vfsqrt.v v8, v12, v0.t
639; CHECK-NEXT:    fsrm a1
640; CHECK-NEXT:    ret
641entry:
642  %a = call <vscale x 4 x double> @llvm.riscv.vfsqrt.mask.nxv4f64(
643    <vscale x 4 x double> %0,
644    <vscale x 4 x double> %1,
645    <vscale x 4 x i1> %2,
646    iXLen 0, iXLen %3, iXLen 1)
647
648  ret <vscale x 4 x double> %a
649}
650
651declare <vscale x 8 x double> @llvm.riscv.vfsqrt.nxv8f64(
652  <vscale x 8 x double>,
653  <vscale x 8 x double>,
654  iXLen, iXLen);
655
656define <vscale x 8 x double> @intrinsic_vfsqrt_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {
657; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f64_nxv8f64:
658; CHECK:       # %bb.0: # %entry
659; CHECK-NEXT:    fsrmi a1, 0
660; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
661; CHECK-NEXT:    vfsqrt.v v8, v8
662; CHECK-NEXT:    fsrm a1
663; CHECK-NEXT:    ret
664entry:
665  %a = call <vscale x 8 x double> @llvm.riscv.vfsqrt.nxv8f64(
666    <vscale x 8 x double> undef,
667    <vscale x 8 x double> %0,
668    iXLen 0, iXLen %1)
669
670  ret <vscale x 8 x double> %a
671}
672
673declare <vscale x 8 x double> @llvm.riscv.vfsqrt.mask.nxv8f64(
674  <vscale x 8 x double>,
675  <vscale x 8 x double>,
676  <vscale x 8 x i1>,
677  iXLen, iXLen, iXLen);
678
679define <vscale x 8 x double> @intrinsic_vfsqrt_mask_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
680; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f64_nxv8f64:
681; CHECK:       # %bb.0: # %entry
682; CHECK-NEXT:    fsrmi a1, 0
683; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, mu
684; CHECK-NEXT:    vfsqrt.v v8, v16, v0.t
685; CHECK-NEXT:    fsrm a1
686; CHECK-NEXT:    ret
687entry:
688  %a = call <vscale x 8 x double> @llvm.riscv.vfsqrt.mask.nxv8f64(
689    <vscale x 8 x double> %0,
690    <vscale x 8 x double> %1,
691    <vscale x 8 x i1> %2,
692    iXLen 0, iXLen %3, iXLen 1)
693
694  ret <vscale x 8 x double> %a
695}
696