xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vfredusum.ll (revision 1cb599835ccf7ee8b2d1d5a7f3107e19a26fc6f5) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \
3; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \
5; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s
6
7declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16(
8  <vscale x 4 x half>,
9  <vscale x 1 x half>,
10  <vscale x 4 x half>,
11  iXLen, iXLen);
12
13define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
14; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv1f16_nxv4f16:
15; CHECK:       # %bb.0: # %entry
16; CHECK-NEXT:    fsrmi a1, 0
17; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, ma
18; CHECK-NEXT:    vfredusum.vs v8, v9, v10
19; CHECK-NEXT:    fsrm a1
20; CHECK-NEXT:    ret
21entry:
22  %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv1f16(
23    <vscale x 4 x half> %0,
24    <vscale x 1 x half> %1,
25    <vscale x 4 x half> %2,
26    iXLen 0, iXLen %3)
27
28  ret <vscale x 4 x half> %a
29}
30
31declare <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.nxv1i1(
32  <vscale x 4 x half>,
33  <vscale x 1 x half>,
34  <vscale x 4 x half>,
35  <vscale x 1 x i1>,
36  iXLen, iXLen);
37
38define <vscale x 4 x half> @intrinsic_vfredusum_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
39; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv1f16_nxv4f16:
40; CHECK:       # %bb.0: # %entry
41; CHECK-NEXT:    fsrmi a1, 0
42; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, ma
43; CHECK-NEXT:    vfredusum.vs v8, v9, v10, v0.t
44; CHECK-NEXT:    fsrm a1
45; CHECK-NEXT:    ret
46entry:
47  %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.nxv1i1(
48    <vscale x 4 x half> %0,
49    <vscale x 1 x half> %1,
50    <vscale x 4 x half> %2,
51    <vscale x 1 x i1> %3,
52    iXLen 0, iXLen %4)
53
54  ret <vscale x 4 x half> %a
55}
56
57declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16(
58  <vscale x 4 x half>,
59  <vscale x 2 x half>,
60  <vscale x 4 x half>,
61  iXLen, iXLen);
62
63define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
64; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv2f16_nxv4f16:
65; CHECK:       # %bb.0: # %entry
66; CHECK-NEXT:    fsrmi a1, 0
67; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, ma
68; CHECK-NEXT:    vfredusum.vs v8, v9, v10
69; CHECK-NEXT:    fsrm a1
70; CHECK-NEXT:    ret
71entry:
72  %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv2f16(
73    <vscale x 4 x half> %0,
74    <vscale x 2 x half> %1,
75    <vscale x 4 x half> %2,
76    iXLen 0, iXLen %3)
77
78  ret <vscale x 4 x half> %a
79}
80
81declare <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.nxv2i1(
82  <vscale x 4 x half>,
83  <vscale x 2 x half>,
84  <vscale x 4 x half>,
85  <vscale x 2 x i1>,
86  iXLen, iXLen);
87
88define <vscale x 4 x half> @intrinsic_vfredusum_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
89; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv2f16_nxv4f16:
90; CHECK:       # %bb.0: # %entry
91; CHECK-NEXT:    fsrmi a1, 0
92; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, ma
93; CHECK-NEXT:    vfredusum.vs v8, v9, v10, v0.t
94; CHECK-NEXT:    fsrm a1
95; CHECK-NEXT:    ret
96entry:
97  %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.nxv2i1(
98    <vscale x 4 x half> %0,
99    <vscale x 2 x half> %1,
100    <vscale x 4 x half> %2,
101    <vscale x 2 x i1> %3,
102    iXLen 0, iXLen %4)
103
104  ret <vscale x 4 x half> %a
105}
106
107declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16(
108  <vscale x 4 x half>,
109  <vscale x 4 x half>,
110  <vscale x 4 x half>,
111  iXLen, iXLen);
112
113define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
114; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv4f16_nxv4f16:
115; CHECK:       # %bb.0: # %entry
116; CHECK-NEXT:    fsrmi a1, 0
117; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma
118; CHECK-NEXT:    vfredusum.vs v8, v9, v10
119; CHECK-NEXT:    fsrm a1
120; CHECK-NEXT:    ret
121entry:
122  %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv4f16(
123    <vscale x 4 x half> %0,
124    <vscale x 4 x half> %1,
125    <vscale x 4 x half> %2,
126    iXLen 0, iXLen %3)
127
128  ret <vscale x 4 x half> %a
129}
130
131declare <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.nxv4i1(
132  <vscale x 4 x half>,
133  <vscale x 4 x half>,
134  <vscale x 4 x half>,
135  <vscale x 4 x i1>,
136  iXLen, iXLen);
137
138define <vscale x 4 x half> @intrinsic_vfredusum_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
139; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv4f16_nxv4f16:
140; CHECK:       # %bb.0: # %entry
141; CHECK-NEXT:    fsrmi a1, 0
142; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma
143; CHECK-NEXT:    vfredusum.vs v8, v9, v10, v0.t
144; CHECK-NEXT:    fsrm a1
145; CHECK-NEXT:    ret
146entry:
147  %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.nxv4i1(
148    <vscale x 4 x half> %0,
149    <vscale x 4 x half> %1,
150    <vscale x 4 x half> %2,
151    <vscale x 4 x i1> %3,
152    iXLen 0, iXLen %4)
153
154  ret <vscale x 4 x half> %a
155}
156
157declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16(
158  <vscale x 4 x half>,
159  <vscale x 8 x half>,
160  <vscale x 4 x half>,
161  iXLen, iXLen);
162
163define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
164; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv8f16_nxv4f16:
165; CHECK:       # %bb.0: # %entry
166; CHECK-NEXT:    fsrmi a1, 0
167; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, ma
168; CHECK-NEXT:    vfredusum.vs v8, v10, v9
169; CHECK-NEXT:    fsrm a1
170; CHECK-NEXT:    ret
171entry:
172  %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv8f16(
173    <vscale x 4 x half> %0,
174    <vscale x 8 x half> %1,
175    <vscale x 4 x half> %2,
176    iXLen 0, iXLen %3)
177
178  ret <vscale x 4 x half> %a
179}
180
181declare <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.nxv8i1(
182  <vscale x 4 x half>,
183  <vscale x 8 x half>,
184  <vscale x 4 x half>,
185  <vscale x 8 x i1>,
186  iXLen, iXLen);
187
188define <vscale x 4 x half> @intrinsic_vfredusum_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
189; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv8f16_nxv4f16:
190; CHECK:       # %bb.0: # %entry
191; CHECK-NEXT:    fsrmi a1, 0
192; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, ma
193; CHECK-NEXT:    vfredusum.vs v8, v10, v9, v0.t
194; CHECK-NEXT:    fsrm a1
195; CHECK-NEXT:    ret
196entry:
197  %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.nxv8i1(
198    <vscale x 4 x half> %0,
199    <vscale x 8 x half> %1,
200    <vscale x 4 x half> %2,
201    <vscale x 8 x i1> %3,
202    iXLen 0, iXLen %4)
203
204  ret <vscale x 4 x half> %a
205}
206
207declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16(
208  <vscale x 4 x half>,
209  <vscale x 16 x half>,
210  <vscale x 4 x half>,
211  iXLen, iXLen);
212
213define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
214; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv16f16_nxv4f16:
215; CHECK:       # %bb.0: # %entry
216; CHECK-NEXT:    fsrmi a1, 0
217; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, ma
218; CHECK-NEXT:    vfredusum.vs v8, v12, v9
219; CHECK-NEXT:    fsrm a1
220; CHECK-NEXT:    ret
221entry:
222  %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv16f16(
223    <vscale x 4 x half> %0,
224    <vscale x 16 x half> %1,
225    <vscale x 4 x half> %2,
226    iXLen 0, iXLen %3)
227
228  ret <vscale x 4 x half> %a
229}
230
231declare <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.nxv16i1(
232  <vscale x 4 x half>,
233  <vscale x 16 x half>,
234  <vscale x 4 x half>,
235  <vscale x 16 x i1>,
236  iXLen, iXLen);
237
238define <vscale x 4 x half> @intrinsic_vfredusum_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
239; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv16f16_nxv4f16:
240; CHECK:       # %bb.0: # %entry
241; CHECK-NEXT:    fsrmi a1, 0
242; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, ma
243; CHECK-NEXT:    vfredusum.vs v8, v12, v9, v0.t
244; CHECK-NEXT:    fsrm a1
245; CHECK-NEXT:    ret
246entry:
247  %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.nxv16i1(
248    <vscale x 4 x half> %0,
249    <vscale x 16 x half> %1,
250    <vscale x 4 x half> %2,
251    <vscale x 16 x i1> %3,
252    iXLen 0, iXLen %4)
253
254  ret <vscale x 4 x half> %a
255}
256
257declare <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16(
258  <vscale x 4 x half>,
259  <vscale x 32 x half>,
260  <vscale x 4 x half>,
261  iXLen, iXLen);
262
263define <vscale x 4 x half> @intrinsic_vfredusum_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
264; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv32f16_nxv4f16:
265; CHECK:       # %bb.0: # %entry
266; CHECK-NEXT:    fsrmi a1, 0
267; CHECK-NEXT:    vsetvli zero, a0, e16, m8, tu, ma
268; CHECK-NEXT:    vfredusum.vs v8, v16, v9
269; CHECK-NEXT:    fsrm a1
270; CHECK-NEXT:    ret
271entry:
272  %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.nxv4f16.nxv32f16(
273    <vscale x 4 x half> %0,
274    <vscale x 32 x half> %1,
275    <vscale x 4 x half> %2,
276    iXLen 0, iXLen %3)
277
278  ret <vscale x 4 x half> %a
279}
280
281declare <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.nxv32i1(
282  <vscale x 4 x half>,
283  <vscale x 32 x half>,
284  <vscale x 4 x half>,
285  <vscale x 32 x i1>,
286  iXLen, iXLen);
287
288define <vscale x 4 x half> @intrinsic_vfredusum_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
289; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv32f16_nxv4f16:
290; CHECK:       # %bb.0: # %entry
291; CHECK-NEXT:    fsrmi a1, 0
292; CHECK-NEXT:    vsetvli zero, a0, e16, m8, tu, ma
293; CHECK-NEXT:    vfredusum.vs v8, v16, v9, v0.t
294; CHECK-NEXT:    fsrm a1
295; CHECK-NEXT:    ret
296entry:
297  %a = call <vscale x 4 x half> @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.nxv32i1(
298    <vscale x 4 x half> %0,
299    <vscale x 32 x half> %1,
300    <vscale x 4 x half> %2,
301    <vscale x 32 x i1> %3,
302    iXLen 0, iXLen %4)
303
304  ret <vscale x 4 x half> %a
305}
306
307declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32(
308  <vscale x 2 x float>,
309  <vscale x 1 x float>,
310  <vscale x 2 x float>,
311  iXLen, iXLen);
312
313define <vscale x 2 x float> @intrinsic_vfredusum_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
314; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv1f32_nxv2f32:
315; CHECK:       # %bb.0: # %entry
316; CHECK-NEXT:    fsrmi a1, 0
317; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma
318; CHECK-NEXT:    vfredusum.vs v8, v9, v10
319; CHECK-NEXT:    fsrm a1
320; CHECK-NEXT:    ret
321entry:
322  %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32(
323    <vscale x 2 x float> %0,
324    <vscale x 1 x float> %1,
325    <vscale x 2 x float> %2,
326    iXLen 0, iXLen %3)
327
328  ret <vscale x 2 x float> %a
329}
330
331declare <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.nxv1i1(
332  <vscale x 2 x float>,
333  <vscale x 1 x float>,
334  <vscale x 2 x float>,
335  <vscale x 1 x i1>,
336  iXLen, iXLen);
337
338define <vscale x 2 x float> @intrinsic_vfredusum_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
339; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv1f32_nxv2f32:
340; CHECK:       # %bb.0: # %entry
341; CHECK-NEXT:    fsrmi a1, 0
342; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma
343; CHECK-NEXT:    vfredusum.vs v8, v9, v10, v0.t
344; CHECK-NEXT:    fsrm a1
345; CHECK-NEXT:    ret
346entry:
347  %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.nxv1i1(
348    <vscale x 2 x float> %0,
349    <vscale x 1 x float> %1,
350    <vscale x 2 x float> %2,
351    <vscale x 1 x i1> %3,
352    iXLen 0, iXLen %4)
353
354  ret <vscale x 2 x float> %a
355}
356
357declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32(
358  <vscale x 2 x float>,
359  <vscale x 2 x float>,
360  <vscale x 2 x float>,
361  iXLen, iXLen);
362
363define <vscale x 2 x float> @intrinsic_vfredusum_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
364; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv2f32_nxv2f32:
365; CHECK:       # %bb.0: # %entry
366; CHECK-NEXT:    fsrmi a1, 0
367; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma
368; CHECK-NEXT:    vfredusum.vs v8, v9, v10
369; CHECK-NEXT:    fsrm a1
370; CHECK-NEXT:    ret
371entry:
372  %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv2f32(
373    <vscale x 2 x float> %0,
374    <vscale x 2 x float> %1,
375    <vscale x 2 x float> %2,
376    iXLen 0, iXLen %3)
377
378  ret <vscale x 2 x float> %a
379}
380
381declare <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.nxv2i1(
382  <vscale x 2 x float>,
383  <vscale x 2 x float>,
384  <vscale x 2 x float>,
385  <vscale x 2 x i1>,
386  iXLen, iXLen);
387
388define <vscale x 2 x float> @intrinsic_vfredusum_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
389; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv2f32_nxv2f32:
390; CHECK:       # %bb.0: # %entry
391; CHECK-NEXT:    fsrmi a1, 0
392; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma
393; CHECK-NEXT:    vfredusum.vs v8, v9, v10, v0.t
394; CHECK-NEXT:    fsrm a1
395; CHECK-NEXT:    ret
396entry:
397  %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.nxv2i1(
398    <vscale x 2 x float> %0,
399    <vscale x 2 x float> %1,
400    <vscale x 2 x float> %2,
401    <vscale x 2 x i1> %3,
402    iXLen 0, iXLen %4)
403
404  ret <vscale x 2 x float> %a
405}
406
407declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32(
408  <vscale x 2 x float>,
409  <vscale x 4 x float>,
410  <vscale x 2 x float>,
411  iXLen, iXLen);
412
413define <vscale x 2 x float> @intrinsic_vfredusum_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
414; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv4f32_nxv2f32:
415; CHECK:       # %bb.0: # %entry
416; CHECK-NEXT:    fsrmi a1, 0
417; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma
418; CHECK-NEXT:    vfredusum.vs v8, v10, v9
419; CHECK-NEXT:    fsrm a1
420; CHECK-NEXT:    ret
421entry:
422  %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv4f32(
423    <vscale x 2 x float> %0,
424    <vscale x 4 x float> %1,
425    <vscale x 2 x float> %2,
426    iXLen 0, iXLen %3)
427
428  ret <vscale x 2 x float> %a
429}
430
431declare <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.nxv4i1(
432  <vscale x 2 x float>,
433  <vscale x 4 x float>,
434  <vscale x 2 x float>,
435  <vscale x 4 x i1>,
436  iXLen, iXLen);
437
438define <vscale x 2 x float> @intrinsic_vfredusum_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
439; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv4f32_nxv2f32:
440; CHECK:       # %bb.0: # %entry
441; CHECK-NEXT:    fsrmi a1, 0
442; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma
443; CHECK-NEXT:    vfredusum.vs v8, v10, v9, v0.t
444; CHECK-NEXT:    fsrm a1
445; CHECK-NEXT:    ret
446entry:
447  %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.nxv4i1(
448    <vscale x 2 x float> %0,
449    <vscale x 4 x float> %1,
450    <vscale x 2 x float> %2,
451    <vscale x 4 x i1> %3,
452    iXLen 0, iXLen %4)
453
454  ret <vscale x 2 x float> %a
455}
456
457declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv8f32(
458  <vscale x 2 x float>,
459  <vscale x 8 x float>,
460  <vscale x 2 x float>,
461  iXLen, iXLen);
462
463define <vscale x 2 x float> @intrinsic_vfredusum_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
464; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv8f32_nxv2f32:
465; CHECK:       # %bb.0: # %entry
466; CHECK-NEXT:    fsrmi a1, 0
467; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma
468; CHECK-NEXT:    vfredusum.vs v8, v12, v9
469; CHECK-NEXT:    fsrm a1
470; CHECK-NEXT:    ret
471entry:
472  %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv8f32(
473    <vscale x 2 x float> %0,
474    <vscale x 8 x float> %1,
475    <vscale x 2 x float> %2,
476    iXLen 0, iXLen %3)
477
478  ret <vscale x 2 x float> %a
479}
480
481declare <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.nxv8i1(
482  <vscale x 2 x float>,
483  <vscale x 8 x float>,
484  <vscale x 2 x float>,
485  <vscale x 8 x i1>,
486  iXLen, iXLen);
487
488define <vscale x 2 x float> @intrinsic_vfredusum_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
489; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv8f32_nxv2f32:
490; CHECK:       # %bb.0: # %entry
491; CHECK-NEXT:    fsrmi a1, 0
492; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma
493; CHECK-NEXT:    vfredusum.vs v8, v12, v9, v0.t
494; CHECK-NEXT:    fsrm a1
495; CHECK-NEXT:    ret
496entry:
497  %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.nxv8i1(
498    <vscale x 2 x float> %0,
499    <vscale x 8 x float> %1,
500    <vscale x 2 x float> %2,
501    <vscale x 8 x i1> %3,
502    iXLen 0, iXLen %4)
503
504  ret <vscale x 2 x float> %a
505}
506
507declare <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv16f32(
508  <vscale x 2 x float>,
509  <vscale x 16 x float>,
510  <vscale x 2 x float>,
511  iXLen, iXLen);
512
513define <vscale x 2 x float> @intrinsic_vfredusum_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
514; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv16f32_nxv2f32:
515; CHECK:       # %bb.0: # %entry
516; CHECK-NEXT:    fsrmi a1, 0
517; CHECK-NEXT:    vsetvli zero, a0, e32, m8, tu, ma
518; CHECK-NEXT:    vfredusum.vs v8, v16, v9
519; CHECK-NEXT:    fsrm a1
520; CHECK-NEXT:    ret
521entry:
522  %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv16f32(
523    <vscale x 2 x float> %0,
524    <vscale x 16 x float> %1,
525    <vscale x 2 x float> %2,
526    iXLen 0, iXLen %3)
527
528  ret <vscale x 2 x float> %a
529}
530
531declare <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.nxv16i1(
532  <vscale x 2 x float>,
533  <vscale x 16 x float>,
534  <vscale x 2 x float>,
535  <vscale x 16 x i1>,
536  iXLen, iXLen);
537
538define <vscale x 2 x float> @intrinsic_vfredusum_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
539; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv16f32_nxv2f32:
540; CHECK:       # %bb.0: # %entry
541; CHECK-NEXT:    fsrmi a1, 0
542; CHECK-NEXT:    vsetvli zero, a0, e32, m8, tu, ma
543; CHECK-NEXT:    vfredusum.vs v8, v16, v9, v0.t
544; CHECK-NEXT:    fsrm a1
545; CHECK-NEXT:    ret
546entry:
547  %a = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.nxv16i1(
548    <vscale x 2 x float> %0,
549    <vscale x 16 x float> %1,
550    <vscale x 2 x float> %2,
551    <vscale x 16 x i1> %3,
552    iXLen 0, iXLen %4)
553
554  ret <vscale x 2 x float> %a
555}
556
557declare <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv1f64(
558  <vscale x 1 x double>,
559  <vscale x 1 x double>,
560  <vscale x 1 x double>,
561  iXLen, iXLen);
562
563define <vscale x 1 x double> @intrinsic_vfredusum_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
564; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv1f64_nxv1f64:
565; CHECK:       # %bb.0: # %entry
566; CHECK-NEXT:    fsrmi a1, 0
567; CHECK-NEXT:    vsetvli zero, a0, e64, m1, tu, ma
568; CHECK-NEXT:    vfredusum.vs v8, v9, v10
569; CHECK-NEXT:    fsrm a1
570; CHECK-NEXT:    ret
571entry:
572  %a = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv1f64(
573    <vscale x 1 x double> %0,
574    <vscale x 1 x double> %1,
575    <vscale x 1 x double> %2,
576    iXLen 0, iXLen %3)
577
578  ret <vscale x 1 x double> %a
579}
580
581declare <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.nxv1i1(
582  <vscale x 1 x double>,
583  <vscale x 1 x double>,
584  <vscale x 1 x double>,
585  <vscale x 1 x i1>,
586  iXLen, iXLen);
587
588define <vscale x 1 x double> @intrinsic_vfredusum_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
589; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv1f64_nxv1f64:
590; CHECK:       # %bb.0: # %entry
591; CHECK-NEXT:    fsrmi a1, 0
592; CHECK-NEXT:    vsetvli zero, a0, e64, m1, tu, ma
593; CHECK-NEXT:    vfredusum.vs v8, v9, v10, v0.t
594; CHECK-NEXT:    fsrm a1
595; CHECK-NEXT:    ret
596entry:
597  %a = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.nxv1i1(
598    <vscale x 1 x double> %0,
599    <vscale x 1 x double> %1,
600    <vscale x 1 x double> %2,
601    <vscale x 1 x i1> %3,
602    iXLen 0, iXLen %4)
603
604  ret <vscale x 1 x double> %a
605}
606
607declare <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv2f64(
608  <vscale x 1 x double>,
609  <vscale x 2 x double>,
610  <vscale x 1 x double>,
611  iXLen, iXLen);
612
613define <vscale x 1 x double> @intrinsic_vfredusum_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
614; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv2f64_nxv1f64:
615; CHECK:       # %bb.0: # %entry
616; CHECK-NEXT:    fsrmi a1, 0
617; CHECK-NEXT:    vsetvli zero, a0, e64, m2, tu, ma
618; CHECK-NEXT:    vfredusum.vs v8, v10, v9
619; CHECK-NEXT:    fsrm a1
620; CHECK-NEXT:    ret
621entry:
622  %a = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv2f64(
623    <vscale x 1 x double> %0,
624    <vscale x 2 x double> %1,
625    <vscale x 1 x double> %2,
626    iXLen 0, iXLen %3)
627
628  ret <vscale x 1 x double> %a
629}
630
631declare <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.nxv2i1(
632  <vscale x 1 x double>,
633  <vscale x 2 x double>,
634  <vscale x 1 x double>,
635  <vscale x 2 x i1>,
636  iXLen, iXLen);
637
638define <vscale x 1 x double> @intrinsic_vfredusum_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
639; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv2f64_nxv1f64:
640; CHECK:       # %bb.0: # %entry
641; CHECK-NEXT:    fsrmi a1, 0
642; CHECK-NEXT:    vsetvli zero, a0, e64, m2, tu, ma
643; CHECK-NEXT:    vfredusum.vs v8, v10, v9, v0.t
644; CHECK-NEXT:    fsrm a1
645; CHECK-NEXT:    ret
646entry:
647  %a = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.nxv2i1(
648    <vscale x 1 x double> %0,
649    <vscale x 2 x double> %1,
650    <vscale x 1 x double> %2,
651    <vscale x 2 x i1> %3,
652    iXLen 0, iXLen %4)
653
654  ret <vscale x 1 x double> %a
655}
656
657declare <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv4f64(
658  <vscale x 1 x double>,
659  <vscale x 4 x double>,
660  <vscale x 1 x double>,
661  iXLen, iXLen);
662
663define <vscale x 1 x double> @intrinsic_vfredusum_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
664; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv4f64_nxv1f64:
665; CHECK:       # %bb.0: # %entry
666; CHECK-NEXT:    fsrmi a1, 0
667; CHECK-NEXT:    vsetvli zero, a0, e64, m4, tu, ma
668; CHECK-NEXT:    vfredusum.vs v8, v12, v9
669; CHECK-NEXT:    fsrm a1
670; CHECK-NEXT:    ret
671entry:
672  %a = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv4f64(
673    <vscale x 1 x double> %0,
674    <vscale x 4 x double> %1,
675    <vscale x 1 x double> %2,
676    iXLen 0, iXLen %3)
677
678  ret <vscale x 1 x double> %a
679}
680
681declare <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.nxv4i1(
682  <vscale x 1 x double>,
683  <vscale x 4 x double>,
684  <vscale x 1 x double>,
685  <vscale x 4 x i1>,
686  iXLen, iXLen);
687
688define <vscale x 1 x double> @intrinsic_vfredusum_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
689; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv4f64_nxv1f64:
690; CHECK:       # %bb.0: # %entry
691; CHECK-NEXT:    fsrmi a1, 0
692; CHECK-NEXT:    vsetvli zero, a0, e64, m4, tu, ma
693; CHECK-NEXT:    vfredusum.vs v8, v12, v9, v0.t
694; CHECK-NEXT:    fsrm a1
695; CHECK-NEXT:    ret
696entry:
697  %a = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.nxv4i1(
698    <vscale x 1 x double> %0,
699    <vscale x 4 x double> %1,
700    <vscale x 1 x double> %2,
701    <vscale x 4 x i1> %3,
702    iXLen 0, iXLen %4)
703
704  ret <vscale x 1 x double> %a
705}
706
707declare <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv8f64(
708  <vscale x 1 x double>,
709  <vscale x 8 x double>,
710  <vscale x 1 x double>,
711  iXLen, iXLen);
712
713define <vscale x 1 x double> @intrinsic_vfredusum_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
714; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv8f64_nxv1f64:
715; CHECK:       # %bb.0: # %entry
716; CHECK-NEXT:    fsrmi a1, 0
717; CHECK-NEXT:    vsetvli zero, a0, e64, m8, tu, ma
718; CHECK-NEXT:    vfredusum.vs v8, v16, v9
719; CHECK-NEXT:    fsrm a1
720; CHECK-NEXT:    ret
721entry:
722  %a = call <vscale x 1 x double> @llvm.riscv.vfredusum.nxv1f64.nxv8f64(
723    <vscale x 1 x double> %0,
724    <vscale x 8 x double> %1,
725    <vscale x 1 x double> %2,
726    iXLen 0, iXLen %3)
727
728  ret <vscale x 1 x double> %a
729}
730
731declare <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.nxv8i1(
732  <vscale x 1 x double>,
733  <vscale x 8 x double>,
734  <vscale x 1 x double>,
735  <vscale x 8 x i1>,
736  iXLen, iXLen);
737
738define <vscale x 1 x double> @intrinsic_vfredusum_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
739; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv8f64_nxv1f64:
740; CHECK:       # %bb.0: # %entry
741; CHECK-NEXT:    fsrmi a1, 0
742; CHECK-NEXT:    vsetvli zero, a0, e64, m8, tu, ma
743; CHECK-NEXT:    vfredusum.vs v8, v16, v9, v0.t
744; CHECK-NEXT:    fsrm a1
745; CHECK-NEXT:    ret
746entry:
747  %a = call <vscale x 1 x double> @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.nxv8i1(
748    <vscale x 1 x double> %0,
749    <vscale x 8 x double> %1,
750    <vscale x 1 x double> %2,
751    <vscale x 8 x i1> %3,
752    iXLen 0, iXLen %4)
753
754  ret <vscale x 1 x double> %a
755}
756