xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s
5; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s
6
7declare <vscale x 2 x float> @llvm.vp.fpext.nxv2f32.nxv2f16(<vscale x 2 x half>, <vscale x 2 x i1>, i32)
8
9define <vscale x 2 x float> @vfpext_nxv2f16_nxv2f32(<vscale x 2 x half> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
10; CHECK-LABEL: vfpext_nxv2f16_nxv2f32:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
13; CHECK-NEXT:    vfwcvt.f.f.v v9, v8, v0.t
14; CHECK-NEXT:    vmv1r.v v8, v9
15; CHECK-NEXT:    ret
16  %v = call <vscale x 2 x float> @llvm.vp.fpext.nxv2f32.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x i1> %m, i32 %vl)
17  ret <vscale x 2 x float> %v
18}
19
20define <vscale x 2 x float> @vfpext_nxv2f16_nxv2f32_unmasked(<vscale x 2 x half> %a, i32 zeroext %vl) {
21; CHECK-LABEL: vfpext_nxv2f16_nxv2f32_unmasked:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
24; CHECK-NEXT:    vfwcvt.f.f.v v9, v8
25; CHECK-NEXT:    vmv1r.v v8, v9
26; CHECK-NEXT:    ret
27  %v = call <vscale x 2 x float> @llvm.vp.fpext.nxv2f32.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)
28  ret <vscale x 2 x float> %v
29}
30
31declare <vscale x 2 x double> @llvm.vp.fpext.nxv2f64.nxv2f16(<vscale x 2 x half>, <vscale x 2 x i1>, i32)
32
33define <vscale x 2 x double> @vfpext_nxv2f16_nxv2f64(<vscale x 2 x half> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
34; CHECK-LABEL: vfpext_nxv2f16_nxv2f64:
35; CHECK:       # %bb.0:
36; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
37; CHECK-NEXT:    vfwcvt.f.f.v v10, v8, v0.t
38; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
39; CHECK-NEXT:    vfwcvt.f.f.v v8, v10, v0.t
40; CHECK-NEXT:    ret
41  %v = call <vscale x 2 x double> @llvm.vp.fpext.nxv2f64.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x i1> %m, i32 %vl)
42  ret <vscale x 2 x double> %v
43}
44
45define <vscale x 2 x double> @vfpext_nxv2f16_nxv2f64_unmasked(<vscale x 2 x half> %a, i32 zeroext %vl) {
46; CHECK-LABEL: vfpext_nxv2f16_nxv2f64_unmasked:
47; CHECK:       # %bb.0:
48; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
49; CHECK-NEXT:    vfwcvt.f.f.v v10, v8
50; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
51; CHECK-NEXT:    vfwcvt.f.f.v v8, v10
52; CHECK-NEXT:    ret
53  %v = call <vscale x 2 x double> @llvm.vp.fpext.nxv2f64.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)
54  ret <vscale x 2 x double> %v
55}
56
57declare <vscale x 2 x double> @llvm.vp.fpext.nxv2f64.nxv2f32(<vscale x 2 x float>, <vscale x 2 x i1>, i32)
58
59define <vscale x 2 x double> @vfpext_nxv2f32_nxv2f64(<vscale x 2 x float> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
60; CHECK-LABEL: vfpext_nxv2f32_nxv2f64:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
63; CHECK-NEXT:    vfwcvt.f.f.v v10, v8, v0.t
64; CHECK-NEXT:    vmv2r.v v8, v10
65; CHECK-NEXT:    ret
66  %v = call <vscale x 2 x double> @llvm.vp.fpext.nxv2f64.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x i1> %m, i32 %vl)
67  ret <vscale x 2 x double> %v
68}
69
70define <vscale x 2 x double> @vfpext_nxv2f32_nxv2f64_unmasked(<vscale x 2 x float> %a, i32 zeroext %vl) {
71; CHECK-LABEL: vfpext_nxv2f32_nxv2f64_unmasked:
72; CHECK:       # %bb.0:
73; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
74; CHECK-NEXT:    vfwcvt.f.f.v v10, v8
75; CHECK-NEXT:    vmv2r.v v8, v10
76; CHECK-NEXT:    ret
77  %v = call <vscale x 2 x double> @llvm.vp.fpext.nxv2f64.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)
78  ret <vscale x 2 x double> %v
79}
80
81declare <vscale x 7 x double> @llvm.vp.fpext.nxv7f64.nxv7f32(<vscale x 7 x float>, <vscale x 7 x i1>, i32)
82
83define <vscale x 7 x double> @vfpext_nxv7f32_nxv7f64(<vscale x 7 x float> %a, <vscale x 7 x i1> %m, i32 zeroext %vl) {
84; CHECK-LABEL: vfpext_nxv7f32_nxv7f64:
85; CHECK:       # %bb.0:
86; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
87; CHECK-NEXT:    vfwcvt.f.f.v v16, v8, v0.t
88; CHECK-NEXT:    vmv8r.v v8, v16
89; CHECK-NEXT:    ret
90  %v = call <vscale x 7 x double> @llvm.vp.fpext.nxv7f64.nxv7f32(<vscale x 7 x float> %a, <vscale x 7 x i1> %m, i32 %vl)
91  ret <vscale x 7 x double> %v
92}
93
94declare <vscale x 32 x float> @llvm.vp.fpext.nxv32f32.nxv32f16(<vscale x 32 x half>, <vscale x 32 x i1>, i32)
95
96define <vscale x 32 x float> @vfpext_nxv32f16_nxv32f32(<vscale x 32 x half> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
97; CHECK-LABEL: vfpext_nxv32f16_nxv32f32:
98; CHECK:       # %bb.0:
99; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
100; CHECK-NEXT:    vmv1r.v v24, v0
101; CHECK-NEXT:    csrr a1, vlenb
102; CHECK-NEXT:    srli a2, a1, 2
103; CHECK-NEXT:    slli a1, a1, 1
104; CHECK-NEXT:    vslidedown.vx v0, v0, a2
105; CHECK-NEXT:    sub a2, a0, a1
106; CHECK-NEXT:    sltu a3, a0, a2
107; CHECK-NEXT:    addi a3, a3, -1
108; CHECK-NEXT:    and a2, a3, a2
109; CHECK-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
110; CHECK-NEXT:    vfwcvt.f.f.v v16, v12, v0.t
111; CHECK-NEXT:    bltu a0, a1, .LBB7_2
112; CHECK-NEXT:  # %bb.1:
113; CHECK-NEXT:    mv a0, a1
114; CHECK-NEXT:  .LBB7_2:
115; CHECK-NEXT:    vmv1r.v v0, v24
116; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
117; CHECK-NEXT:    vfwcvt.f.f.v v24, v8, v0.t
118; CHECK-NEXT:    vmv8r.v v8, v24
119; CHECK-NEXT:    ret
120  %v = call <vscale x 32 x float> @llvm.vp.fpext.nxv32f32.nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x i1> %m, i32 %vl)
121  ret <vscale x 32 x float> %v
122}
123
124declare <vscale x 2 x float> @llvm.vp.fpext.nxv2f32.nxv2bf16(<vscale x 2 x bfloat>, <vscale x 2 x i1>, i32)
125
126define <vscale x 2 x float> @vfpext_nxv2bf16_nxv2f32(<vscale x 2 x bfloat> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
127; CHECK-LABEL: vfpext_nxv2bf16_nxv2f32:
128; CHECK:       # %bb.0:
129; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
130; CHECK-NEXT:    vfwcvtbf16.f.f.v v9, v8, v0.t
131; CHECK-NEXT:    vmv1r.v v8, v9
132; CHECK-NEXT:    ret
133  %v = call <vscale x 2 x float> @llvm.vp.fpext.nxv2f32.nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x i1> %m, i32 %vl)
134  ret <vscale x 2 x float> %v
135}
136
137define <vscale x 2 x float> @vfpext_nxv2bf16_nxv2f32_unmasked(<vscale x 2 x bfloat> %a, i32 zeroext %vl) {
138; CHECK-LABEL: vfpext_nxv2bf16_nxv2f32_unmasked:
139; CHECK:       # %bb.0:
140; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
141; CHECK-NEXT:    vfwcvtbf16.f.f.v v9, v8
142; CHECK-NEXT:    vmv1r.v v8, v9
143; CHECK-NEXT:    ret
144  %v = call <vscale x 2 x float> @llvm.vp.fpext.nxv2f32.nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)
145  ret <vscale x 2 x float> %v
146}
147
148declare <vscale x 2 x double> @llvm.vp.fpext.nxv2f64.nxv2bf16(<vscale x 2 x bfloat>, <vscale x 2 x i1>, i32)
149
150define <vscale x 2 x double> @vfpext_nxv2bf16_nxv2f64(<vscale x 2 x bfloat> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
151; CHECK-LABEL: vfpext_nxv2bf16_nxv2f64:
152; CHECK:       # %bb.0:
153; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
154; CHECK-NEXT:    vfwcvtbf16.f.f.v v10, v8, v0.t
155; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
156; CHECK-NEXT:    vfwcvt.f.f.v v8, v10, v0.t
157; CHECK-NEXT:    ret
158  %v = call <vscale x 2 x double> @llvm.vp.fpext.nxv2f64.nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x i1> %m, i32 %vl)
159  ret <vscale x 2 x double> %v
160}
161
162define <vscale x 2 x double> @vfpext_nxv2bf16_nxv2f64_unmasked(<vscale x 2 x bfloat> %a, i32 zeroext %vl) {
163; CHECK-LABEL: vfpext_nxv2bf16_nxv2f64_unmasked:
164; CHECK:       # %bb.0:
165; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
166; CHECK-NEXT:    vfwcvtbf16.f.f.v v10, v8
167; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
168; CHECK-NEXT:    vfwcvt.f.f.v v8, v10
169; CHECK-NEXT:    ret
170  %v = call <vscale x 2 x double> @llvm.vp.fpext.nxv2f64.nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)
171  ret <vscale x 2 x double> %v
172}
173
174