xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll (revision 8ce81f17a16b8b689895c7c093d0401a75c09882) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
6; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=ilp32d \
7; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
8; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=lp64d \
9; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
10
11declare <vscale x 1 x half> @llvm.vp.fmul.nxv1f16(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i32)
12
13define <vscale x 1 x half> @vfmul_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
14; ZVFH-LABEL: vfmul_vv_nxv1f16:
15; ZVFH:       # %bb.0:
16; ZVFH-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
17; ZVFH-NEXT:    vfmul.vv v8, v8, v9, v0.t
18; ZVFH-NEXT:    ret
19;
20; ZVFHMIN-LABEL: vfmul_vv_nxv1f16:
21; ZVFHMIN:       # %bb.0:
22; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
23; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9, v0.t
24; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8, v0.t
25; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
26; ZVFHMIN-NEXT:    vfmul.vv v9, v9, v10, v0.t
27; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
28; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9, v0.t
29; ZVFHMIN-NEXT:    ret
30  %v = call <vscale x 1 x half> @llvm.vp.fmul.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %b, <vscale x 1 x i1> %m, i32 %evl)
31  ret <vscale x 1 x half> %v
32}
33
34define <vscale x 1 x half> @vfmul_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, <vscale x 1 x half> %b, i32 zeroext %evl) {
35; ZVFH-LABEL: vfmul_vv_nxv1f16_unmasked:
36; ZVFH:       # %bb.0:
37; ZVFH-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
38; ZVFH-NEXT:    vfmul.vv v8, v8, v9
39; ZVFH-NEXT:    ret
40;
41; ZVFHMIN-LABEL: vfmul_vv_nxv1f16_unmasked:
42; ZVFHMIN:       # %bb.0:
43; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
44; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9
45; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8
46; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
47; ZVFHMIN-NEXT:    vfmul.vv v9, v9, v10
48; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
49; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
50; ZVFHMIN-NEXT:    ret
51  %v = call <vscale x 1 x half> @llvm.vp.fmul.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
52  ret <vscale x 1 x half> %v
53}
54
55define <vscale x 1 x half> @vfmul_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
56; ZVFH-LABEL: vfmul_vf_nxv1f16:
57; ZVFH:       # %bb.0:
58; ZVFH-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
59; ZVFH-NEXT:    vfmul.vf v8, v8, fa0, v0.t
60; ZVFH-NEXT:    ret
61;
62; ZVFHMIN-LABEL: vfmul_vf_nxv1f16:
63; ZVFHMIN:       # %bb.0:
64; ZVFHMIN-NEXT:    fmv.x.h a1, fa0
65; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
66; ZVFHMIN-NEXT:    vmv.v.x v9, a1
67; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8, v0.t
68; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v9, v0.t
69; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
70; ZVFHMIN-NEXT:    vfmul.vv v9, v10, v8, v0.t
71; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
72; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9, v0.t
73; ZVFHMIN-NEXT:    ret
74  %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
75  %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
76  %v = call <vscale x 1 x half> @llvm.vp.fmul.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 %evl)
77  ret <vscale x 1 x half> %v
78}
79
80define <vscale x 1 x half> @vfmul_vf_nxv1f16_unmasked(<vscale x 1 x half> %va, half %b, i32 zeroext %evl) {
81; ZVFH-LABEL: vfmul_vf_nxv1f16_unmasked:
82; ZVFH:       # %bb.0:
83; ZVFH-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
84; ZVFH-NEXT:    vfmul.vf v8, v8, fa0
85; ZVFH-NEXT:    ret
86;
87; ZVFHMIN-LABEL: vfmul_vf_nxv1f16_unmasked:
88; ZVFHMIN:       # %bb.0:
89; ZVFHMIN-NEXT:    fmv.x.h a1, fa0
90; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
91; ZVFHMIN-NEXT:    vmv.v.x v9, a1
92; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
93; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v9
94; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
95; ZVFHMIN-NEXT:    vfmul.vv v9, v10, v8
96; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
97; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
98; ZVFHMIN-NEXT:    ret
99  %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
100  %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
101  %v = call <vscale x 1 x half> @llvm.vp.fmul.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)
102  ret <vscale x 1 x half> %v
103}
104
105declare <vscale x 2 x half> @llvm.vp.fmul.nxv2f16(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i32)
106
107define <vscale x 2 x half> @vfmul_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
108; ZVFH-LABEL: vfmul_vv_nxv2f16:
109; ZVFH:       # %bb.0:
110; ZVFH-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
111; ZVFH-NEXT:    vfmul.vv v8, v8, v9, v0.t
112; ZVFH-NEXT:    ret
113;
114; ZVFHMIN-LABEL: vfmul_vv_nxv2f16:
115; ZVFHMIN:       # %bb.0:
116; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
117; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9, v0.t
118; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8, v0.t
119; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
120; ZVFHMIN-NEXT:    vfmul.vv v9, v9, v10, v0.t
121; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
122; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9, v0.t
123; ZVFHMIN-NEXT:    ret
124  %v = call <vscale x 2 x half> @llvm.vp.fmul.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %b, <vscale x 2 x i1> %m, i32 %evl)
125  ret <vscale x 2 x half> %v
126}
127
128define <vscale x 2 x half> @vfmul_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, <vscale x 2 x half> %b, i32 zeroext %evl) {
129; ZVFH-LABEL: vfmul_vv_nxv2f16_unmasked:
130; ZVFH:       # %bb.0:
131; ZVFH-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
132; ZVFH-NEXT:    vfmul.vv v8, v8, v9
133; ZVFH-NEXT:    ret
134;
135; ZVFHMIN-LABEL: vfmul_vv_nxv2f16_unmasked:
136; ZVFHMIN:       # %bb.0:
137; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
138; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9
139; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8
140; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
141; ZVFHMIN-NEXT:    vfmul.vv v9, v9, v10
142; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
143; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
144; ZVFHMIN-NEXT:    ret
145  %v = call <vscale x 2 x half> @llvm.vp.fmul.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
146  ret <vscale x 2 x half> %v
147}
148
149define <vscale x 2 x half> @vfmul_vf_nxv2f16(<vscale x 2 x half> %va, half %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
150; ZVFH-LABEL: vfmul_vf_nxv2f16:
151; ZVFH:       # %bb.0:
152; ZVFH-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
153; ZVFH-NEXT:    vfmul.vf v8, v8, fa0, v0.t
154; ZVFH-NEXT:    ret
155;
156; ZVFHMIN-LABEL: vfmul_vf_nxv2f16:
157; ZVFHMIN:       # %bb.0:
158; ZVFHMIN-NEXT:    fmv.x.h a1, fa0
159; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
160; ZVFHMIN-NEXT:    vmv.v.x v9, a1
161; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8, v0.t
162; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v9, v0.t
163; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
164; ZVFHMIN-NEXT:    vfmul.vv v9, v10, v8, v0.t
165; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
166; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9, v0.t
167; ZVFHMIN-NEXT:    ret
168  %elt.head = insertelement <vscale x 2 x half> poison, half %b, i32 0
169  %vb = shufflevector <vscale x 2 x half> %elt.head, <vscale x 2 x half> poison, <vscale x 2 x i32> zeroinitializer
170  %v = call <vscale x 2 x half> @llvm.vp.fmul.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> %m, i32 %evl)
171  ret <vscale x 2 x half> %v
172}
173
174define <vscale x 2 x half> @vfmul_vf_nxv2f16_unmasked(<vscale x 2 x half> %va, half %b, i32 zeroext %evl) {
175; ZVFH-LABEL: vfmul_vf_nxv2f16_unmasked:
176; ZVFH:       # %bb.0:
177; ZVFH-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
178; ZVFH-NEXT:    vfmul.vf v8, v8, fa0
179; ZVFH-NEXT:    ret
180;
181; ZVFHMIN-LABEL: vfmul_vf_nxv2f16_unmasked:
182; ZVFHMIN:       # %bb.0:
183; ZVFHMIN-NEXT:    fmv.x.h a1, fa0
184; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
185; ZVFHMIN-NEXT:    vmv.v.x v9, a1
186; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
187; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v9
188; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
189; ZVFHMIN-NEXT:    vfmul.vv v9, v10, v8
190; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
191; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
192; ZVFHMIN-NEXT:    ret
193  %elt.head = insertelement <vscale x 2 x half> poison, half %b, i32 0
194  %vb = shufflevector <vscale x 2 x half> %elt.head, <vscale x 2 x half> poison, <vscale x 2 x i32> zeroinitializer
195  %v = call <vscale x 2 x half> @llvm.vp.fmul.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)
196  ret <vscale x 2 x half> %v
197}
198
199declare <vscale x 4 x half> @llvm.vp.fmul.nxv4f16(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i32)
200
201define <vscale x 4 x half> @vfmul_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
202; ZVFH-LABEL: vfmul_vv_nxv4f16:
203; ZVFH:       # %bb.0:
204; ZVFH-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
205; ZVFH-NEXT:    vfmul.vv v8, v8, v9, v0.t
206; ZVFH-NEXT:    ret
207;
208; ZVFHMIN-LABEL: vfmul_vv_nxv4f16:
209; ZVFHMIN:       # %bb.0:
210; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
211; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9, v0.t
212; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v8, v0.t
213; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
214; ZVFHMIN-NEXT:    vfmul.vv v10, v12, v10, v0.t
215; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
216; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v10, v0.t
217; ZVFHMIN-NEXT:    ret
218  %v = call <vscale x 4 x half> @llvm.vp.fmul.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %b, <vscale x 4 x i1> %m, i32 %evl)
219  ret <vscale x 4 x half> %v
220}
221
222define <vscale x 4 x half> @vfmul_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, <vscale x 4 x half> %b, i32 zeroext %evl) {
223; ZVFH-LABEL: vfmul_vv_nxv4f16_unmasked:
224; ZVFH:       # %bb.0:
225; ZVFH-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
226; ZVFH-NEXT:    vfmul.vv v8, v8, v9
227; ZVFH-NEXT:    ret
228;
229; ZVFHMIN-LABEL: vfmul_vv_nxv4f16_unmasked:
230; ZVFHMIN:       # %bb.0:
231; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
232; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9
233; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v8
234; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
235; ZVFHMIN-NEXT:    vfmul.vv v10, v12, v10
236; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
237; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v10
238; ZVFHMIN-NEXT:    ret
239  %v = call <vscale x 4 x half> @llvm.vp.fmul.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
240  ret <vscale x 4 x half> %v
241}
242
243define <vscale x 4 x half> @vfmul_vf_nxv4f16(<vscale x 4 x half> %va, half %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
244; ZVFH-LABEL: vfmul_vf_nxv4f16:
245; ZVFH:       # %bb.0:
246; ZVFH-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
247; ZVFH-NEXT:    vfmul.vf v8, v8, fa0, v0.t
248; ZVFH-NEXT:    ret
249;
250; ZVFHMIN-LABEL: vfmul_vf_nxv4f16:
251; ZVFHMIN:       # %bb.0:
252; ZVFHMIN-NEXT:    fmv.x.h a1, fa0
253; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
254; ZVFHMIN-NEXT:    vmv.v.x v9, a1
255; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8, v0.t
256; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v9, v0.t
257; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
258; ZVFHMIN-NEXT:    vfmul.vv v10, v10, v12, v0.t
259; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
260; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v10, v0.t
261; ZVFHMIN-NEXT:    ret
262  %elt.head = insertelement <vscale x 4 x half> poison, half %b, i32 0
263  %vb = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> poison, <vscale x 4 x i32> zeroinitializer
264  %v = call <vscale x 4 x half> @llvm.vp.fmul.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> %m, i32 %evl)
265  ret <vscale x 4 x half> %v
266}
267
268define <vscale x 4 x half> @vfmul_vf_nxv4f16_unmasked(<vscale x 4 x half> %va, half %b, i32 zeroext %evl) {
269; ZVFH-LABEL: vfmul_vf_nxv4f16_unmasked:
270; ZVFH:       # %bb.0:
271; ZVFH-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
272; ZVFH-NEXT:    vfmul.vf v8, v8, fa0
273; ZVFH-NEXT:    ret
274;
275; ZVFHMIN-LABEL: vfmul_vf_nxv4f16_unmasked:
276; ZVFHMIN:       # %bb.0:
277; ZVFHMIN-NEXT:    fmv.x.h a1, fa0
278; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
279; ZVFHMIN-NEXT:    vmv.v.x v9, a1
280; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v8
281; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v9
282; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
283; ZVFHMIN-NEXT:    vfmul.vv v10, v10, v12
284; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
285; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v10
286; ZVFHMIN-NEXT:    ret
287  %elt.head = insertelement <vscale x 4 x half> poison, half %b, i32 0
288  %vb = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> poison, <vscale x 4 x i32> zeroinitializer
289  %v = call <vscale x 4 x half> @llvm.vp.fmul.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)
290  ret <vscale x 4 x half> %v
291}
292
293declare <vscale x 8 x half> @llvm.vp.fmul.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i32)
294
295define <vscale x 8 x half> @vfmul_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
296; ZVFH-LABEL: vfmul_vv_nxv8f16:
297; ZVFH:       # %bb.0:
298; ZVFH-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
299; ZVFH-NEXT:    vfmul.vv v8, v8, v10, v0.t
300; ZVFH-NEXT:    ret
301;
302; ZVFHMIN-LABEL: vfmul_vv_nxv8f16:
303; ZVFHMIN:       # %bb.0:
304; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
305; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v10, v0.t
306; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v8, v0.t
307; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
308; ZVFHMIN-NEXT:    vfmul.vv v12, v16, v12, v0.t
309; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
310; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v12, v0.t
311; ZVFHMIN-NEXT:    ret
312  %v = call <vscale x 8 x half> @llvm.vp.fmul.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %b, <vscale x 8 x i1> %m, i32 %evl)
313  ret <vscale x 8 x half> %v
314}
315
316define <vscale x 8 x half> @vfmul_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, <vscale x 8 x half> %b, i32 zeroext %evl) {
317; ZVFH-LABEL: vfmul_vv_nxv8f16_unmasked:
318; ZVFH:       # %bb.0:
319; ZVFH-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
320; ZVFH-NEXT:    vfmul.vv v8, v8, v10
321; ZVFH-NEXT:    ret
322;
323; ZVFHMIN-LABEL: vfmul_vv_nxv8f16_unmasked:
324; ZVFHMIN:       # %bb.0:
325; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
326; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v10
327; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v8
328; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
329; ZVFHMIN-NEXT:    vfmul.vv v12, v16, v12
330; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
331; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v12
332; ZVFHMIN-NEXT:    ret
333  %v = call <vscale x 8 x half> @llvm.vp.fmul.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
334  ret <vscale x 8 x half> %v
335}
336
337define <vscale x 8 x half> @vfmul_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
338; ZVFH-LABEL: vfmul_vf_nxv8f16:
339; ZVFH:       # %bb.0:
340; ZVFH-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
341; ZVFH-NEXT:    vfmul.vf v8, v8, fa0, v0.t
342; ZVFH-NEXT:    ret
343;
344; ZVFHMIN-LABEL: vfmul_vf_nxv8f16:
345; ZVFHMIN:       # %bb.0:
346; ZVFHMIN-NEXT:    fmv.x.h a1, fa0
347; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
348; ZVFHMIN-NEXT:    vmv.v.x v10, a1
349; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v8, v0.t
350; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v10, v0.t
351; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
352; ZVFHMIN-NEXT:    vfmul.vv v12, v12, v16, v0.t
353; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
354; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v12, v0.t
355; ZVFHMIN-NEXT:    ret
356  %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
357  %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
358  %v = call <vscale x 8 x half> @llvm.vp.fmul.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 %evl)
359  ret <vscale x 8 x half> %v
360}
361
362define <vscale x 8 x half> @vfmul_vf_nxv8f16_unmasked(<vscale x 8 x half> %va, half %b, i32 zeroext %evl) {
363; ZVFH-LABEL: vfmul_vf_nxv8f16_unmasked:
364; ZVFH:       # %bb.0:
365; ZVFH-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
366; ZVFH-NEXT:    vfmul.vf v8, v8, fa0
367; ZVFH-NEXT:    ret
368;
369; ZVFHMIN-LABEL: vfmul_vf_nxv8f16_unmasked:
370; ZVFHMIN:       # %bb.0:
371; ZVFHMIN-NEXT:    fmv.x.h a1, fa0
372; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
373; ZVFHMIN-NEXT:    vmv.v.x v10, a1
374; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v8
375; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v10
376; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
377; ZVFHMIN-NEXT:    vfmul.vv v12, v12, v16
378; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
379; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v12
380; ZVFHMIN-NEXT:    ret
381  %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
382  %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
383  %v = call <vscale x 8 x half> @llvm.vp.fmul.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)
384  ret <vscale x 8 x half> %v
385}
386
387declare <vscale x 16 x half> @llvm.vp.fmul.nxv16f16(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i32)
388
389define <vscale x 16 x half> @vfmul_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
390; ZVFH-LABEL: vfmul_vv_nxv16f16:
391; ZVFH:       # %bb.0:
392; ZVFH-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
393; ZVFH-NEXT:    vfmul.vv v8, v8, v12, v0.t
394; ZVFH-NEXT:    ret
395;
396; ZVFHMIN-LABEL: vfmul_vv_nxv16f16:
397; ZVFHMIN:       # %bb.0:
398; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
399; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v12, v0.t
400; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v8, v0.t
401; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
402; ZVFHMIN-NEXT:    vfmul.vv v16, v24, v16, v0.t
403; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
404; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v16, v0.t
405; ZVFHMIN-NEXT:    ret
406  %v = call <vscale x 16 x half> @llvm.vp.fmul.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %b, <vscale x 16 x i1> %m, i32 %evl)
407  ret <vscale x 16 x half> %v
408}
409
410define <vscale x 16 x half> @vfmul_vv_nxv16f16_unmasked(<vscale x 16 x half> %va, <vscale x 16 x half> %b, i32 zeroext %evl) {
411; ZVFH-LABEL: vfmul_vv_nxv16f16_unmasked:
412; ZVFH:       # %bb.0:
413; ZVFH-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
414; ZVFH-NEXT:    vfmul.vv v8, v8, v12
415; ZVFH-NEXT:    ret
416;
417; ZVFHMIN-LABEL: vfmul_vv_nxv16f16_unmasked:
418; ZVFHMIN:       # %bb.0:
419; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
420; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v12
421; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v8
422; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
423; ZVFHMIN-NEXT:    vfmul.vv v16, v24, v16
424; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
425; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v16
426; ZVFHMIN-NEXT:    ret
427  %v = call <vscale x 16 x half> @llvm.vp.fmul.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)
428  ret <vscale x 16 x half> %v
429}
430
431define <vscale x 16 x half> @vfmul_vf_nxv16f16(<vscale x 16 x half> %va, half %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
432; ZVFH-LABEL: vfmul_vf_nxv16f16:
433; ZVFH:       # %bb.0:
434; ZVFH-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
435; ZVFH-NEXT:    vfmul.vf v8, v8, fa0, v0.t
436; ZVFH-NEXT:    ret
437;
438; ZVFHMIN-LABEL: vfmul_vf_nxv16f16:
439; ZVFHMIN:       # %bb.0:
440; ZVFHMIN-NEXT:    fmv.x.h a1, fa0
441; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
442; ZVFHMIN-NEXT:    vmv.v.x v12, a1
443; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v8, v0.t
444; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v12, v0.t
445; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
446; ZVFHMIN-NEXT:    vfmul.vv v16, v16, v24, v0.t
447; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
448; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v16, v0.t
449; ZVFHMIN-NEXT:    ret
450  %elt.head = insertelement <vscale x 16 x half> poison, half %b, i32 0
451  %vb = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> poison, <vscale x 16 x i32> zeroinitializer
452  %v = call <vscale x 16 x half> @llvm.vp.fmul.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> %m, i32 %evl)
453  ret <vscale x 16 x half> %v
454}
455
456define <vscale x 16 x half> @vfmul_vf_nxv16f16_unmasked(<vscale x 16 x half> %va, half %b, i32 zeroext %evl) {
457; ZVFH-LABEL: vfmul_vf_nxv16f16_unmasked:
458; ZVFH:       # %bb.0:
459; ZVFH-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
460; ZVFH-NEXT:    vfmul.vf v8, v8, fa0
461; ZVFH-NEXT:    ret
462;
463; ZVFHMIN-LABEL: vfmul_vf_nxv16f16_unmasked:
464; ZVFHMIN:       # %bb.0:
465; ZVFHMIN-NEXT:    fmv.x.h a1, fa0
466; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
467; ZVFHMIN-NEXT:    vmv.v.x v12, a1
468; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v8
469; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v12
470; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
471; ZVFHMIN-NEXT:    vfmul.vv v16, v16, v24
472; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
473; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v16
474; ZVFHMIN-NEXT:    ret
475  %elt.head = insertelement <vscale x 16 x half> poison, half %b, i32 0
476  %vb = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> poison, <vscale x 16 x i32> zeroinitializer
477  %v = call <vscale x 16 x half> @llvm.vp.fmul.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)
478  ret <vscale x 16 x half> %v
479}
480
481declare <vscale x 32 x half> @llvm.vp.fmul.nxv32f16(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i32)
482
483define <vscale x 32 x half> @vfmul_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
484; ZVFH-LABEL: vfmul_vv_nxv32f16:
485; ZVFH:       # %bb.0:
486; ZVFH-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
487; ZVFH-NEXT:    vfmul.vv v8, v8, v16, v0.t
488; ZVFH-NEXT:    ret
489;
490; ZVFHMIN-LABEL: vfmul_vv_nxv32f16:
491; ZVFHMIN:       # %bb.0:
492; ZVFHMIN-NEXT:    addi sp, sp, -16
493; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 16
494; ZVFHMIN-NEXT:    csrr a1, vlenb
495; ZVFHMIN-NEXT:    slli a1, a1, 3
496; ZVFHMIN-NEXT:    mv a2, a1
497; ZVFHMIN-NEXT:    slli a1, a1, 1
498; ZVFHMIN-NEXT:    add a1, a1, a2
499; ZVFHMIN-NEXT:    sub sp, sp, a1
500; ZVFHMIN-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
501; ZVFHMIN-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
502; ZVFHMIN-NEXT:    vmv1r.v v7, v0
503; ZVFHMIN-NEXT:    csrr a1, vlenb
504; ZVFHMIN-NEXT:    slli a1, a1, 4
505; ZVFHMIN-NEXT:    add a1, sp, a1
506; ZVFHMIN-NEXT:    addi a1, a1, 16
507; ZVFHMIN-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
508; ZVFHMIN-NEXT:    csrr a2, vlenb
509; ZVFHMIN-NEXT:    slli a1, a2, 1
510; ZVFHMIN-NEXT:    srli a2, a2, 2
511; ZVFHMIN-NEXT:    sub a3, a0, a1
512; ZVFHMIN-NEXT:    vslidedown.vx v0, v0, a2
513; ZVFHMIN-NEXT:    sltu a2, a0, a3
514; ZVFHMIN-NEXT:    addi a2, a2, -1
515; ZVFHMIN-NEXT:    and a2, a2, a3
516; ZVFHMIN-NEXT:    vmv4r.v v8, v16
517; ZVFHMIN-NEXT:    csrr a3, vlenb
518; ZVFHMIN-NEXT:    slli a3, a3, 3
519; ZVFHMIN-NEXT:    add a3, sp, a3
520; ZVFHMIN-NEXT:    addi a3, a3, 16
521; ZVFHMIN-NEXT:    vs8r.v v8, (a3) # Unknown-size Folded Spill
522; ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
523; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v20, v0.t
524; ZVFHMIN-NEXT:    addi a2, sp, 16
525; ZVFHMIN-NEXT:    vs8r.v v8, (a2) # Unknown-size Folded Spill
526; ZVFHMIN-NEXT:    csrr a2, vlenb
527; ZVFHMIN-NEXT:    slli a2, a2, 4
528; ZVFHMIN-NEXT:    add a2, sp, a2
529; ZVFHMIN-NEXT:    addi a2, a2, 16
530; ZVFHMIN-NEXT:    vl8r.v v16, (a2) # Unknown-size Folded Reload
531; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v20, v0.t
532; ZVFHMIN-NEXT:    addi a2, sp, 16
533; ZVFHMIN-NEXT:    vl8r.v v16, (a2) # Unknown-size Folded Reload
534; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
535; ZVFHMIN-NEXT:    vfmul.vv v16, v8, v16, v0.t
536; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
537; ZVFHMIN-NEXT:    vfncvt.f.f.w v12, v16, v0.t
538; ZVFHMIN-NEXT:    bltu a0, a1, .LBB20_2
539; ZVFHMIN-NEXT:  # %bb.1:
540; ZVFHMIN-NEXT:    mv a0, a1
541; ZVFHMIN-NEXT:  .LBB20_2:
542; ZVFHMIN-NEXT:    vmv1r.v v0, v7
543; ZVFHMIN-NEXT:    csrr a1, vlenb
544; ZVFHMIN-NEXT:    slli a1, a1, 3
545; ZVFHMIN-NEXT:    add a1, sp, a1
546; ZVFHMIN-NEXT:    addi a1, a1, 16
547; ZVFHMIN-NEXT:    vl8r.v v16, (a1) # Unknown-size Folded Reload
548; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
549; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v16, v0.t
550; ZVFHMIN-NEXT:    addi a0, sp, 16
551; ZVFHMIN-NEXT:    vs8r.v v24, (a0) # Unknown-size Folded Spill
552; ZVFHMIN-NEXT:    csrr a0, vlenb
553; ZVFHMIN-NEXT:    slli a0, a0, 4
554; ZVFHMIN-NEXT:    add a0, sp, a0
555; ZVFHMIN-NEXT:    addi a0, a0, 16
556; ZVFHMIN-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
557; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v16, v0.t
558; ZVFHMIN-NEXT:    addi a0, sp, 16
559; ZVFHMIN-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
560; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
561; ZVFHMIN-NEXT:    vfmul.vv v16, v24, v16, v0.t
562; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
563; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v16, v0.t
564; ZVFHMIN-NEXT:    csrr a0, vlenb
565; ZVFHMIN-NEXT:    slli a0, a0, 3
566; ZVFHMIN-NEXT:    mv a1, a0
567; ZVFHMIN-NEXT:    slli a0, a0, 1
568; ZVFHMIN-NEXT:    add a0, a0, a1
569; ZVFHMIN-NEXT:    add sp, sp, a0
570; ZVFHMIN-NEXT:    .cfi_def_cfa sp, 16
571; ZVFHMIN-NEXT:    addi sp, sp, 16
572; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
573; ZVFHMIN-NEXT:    ret
574  %v = call <vscale x 32 x half> @llvm.vp.fmul.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %b, <vscale x 32 x i1> %m, i32 %evl)
575  ret <vscale x 32 x half> %v
576}
577
578define <vscale x 32 x half> @vfmul_vv_nxv32f16_unmasked(<vscale x 32 x half> %va, <vscale x 32 x half> %b, i32 zeroext %evl) {
579; ZVFH-LABEL: vfmul_vv_nxv32f16_unmasked:
580; ZVFH:       # %bb.0:
581; ZVFH-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
582; ZVFH-NEXT:    vfmul.vv v8, v8, v16
583; ZVFH-NEXT:    ret
584;
585; ZVFHMIN-LABEL: vfmul_vv_nxv32f16_unmasked:
586; ZVFHMIN:       # %bb.0:
587; ZVFHMIN-NEXT:    addi sp, sp, -16
588; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 16
589; ZVFHMIN-NEXT:    csrr a1, vlenb
590; ZVFHMIN-NEXT:    slli a1, a1, 3
591; ZVFHMIN-NEXT:    sub sp, sp, a1
592; ZVFHMIN-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
593; ZVFHMIN-NEXT:    csrr a2, vlenb
594; ZVFHMIN-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
595; ZVFHMIN-NEXT:    vmset.m v24
596; ZVFHMIN-NEXT:    slli a1, a2, 1
597; ZVFHMIN-NEXT:    srli a2, a2, 2
598; ZVFHMIN-NEXT:    sub a3, a0, a1
599; ZVFHMIN-NEXT:    vsetvli a4, zero, e8, mf2, ta, ma
600; ZVFHMIN-NEXT:    vslidedown.vx v0, v24, a2
601; ZVFHMIN-NEXT:    sltu a2, a0, a3
602; ZVFHMIN-NEXT:    addi a2, a2, -1
603; ZVFHMIN-NEXT:    and a2, a2, a3
604; ZVFHMIN-NEXT:    addi a3, sp, 16
605; ZVFHMIN-NEXT:    vs8r.v v16, (a3) # Unknown-size Folded Spill
606; ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
607; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v20, v0.t
608; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v12, v0.t
609; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
610; ZVFHMIN-NEXT:    vfmul.vv v16, v16, v24, v0.t
611; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
612; ZVFHMIN-NEXT:    vfncvt.f.f.w v12, v16, v0.t
613; ZVFHMIN-NEXT:    bltu a0, a1, .LBB21_2
614; ZVFHMIN-NEXT:  # %bb.1:
615; ZVFHMIN-NEXT:    mv a0, a1
616; ZVFHMIN-NEXT:  .LBB21_2:
617; ZVFHMIN-NEXT:    addi a1, sp, 16
618; ZVFHMIN-NEXT:    vl8r.v v24, (a1) # Unknown-size Folded Reload
619; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
620; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
621; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v8
622; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
623; ZVFHMIN-NEXT:    vfmul.vv v16, v24, v16
624; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
625; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v16
626; ZVFHMIN-NEXT:    csrr a0, vlenb
627; ZVFHMIN-NEXT:    slli a0, a0, 3
628; ZVFHMIN-NEXT:    add sp, sp, a0
629; ZVFHMIN-NEXT:    .cfi_def_cfa sp, 16
630; ZVFHMIN-NEXT:    addi sp, sp, 16
631; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
632; ZVFHMIN-NEXT:    ret
633  %v = call <vscale x 32 x half> @llvm.vp.fmul.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)
634  ret <vscale x 32 x half> %v
635}
636
637define <vscale x 32 x half> @vfmul_vf_nxv32f16(<vscale x 32 x half> %va, half %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
638; ZVFH-LABEL: vfmul_vf_nxv32f16:
639; ZVFH:       # %bb.0:
640; ZVFH-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
641; ZVFH-NEXT:    vfmul.vf v8, v8, fa0, v0.t
642; ZVFH-NEXT:    ret
643;
644; ZVFHMIN-LABEL: vfmul_vf_nxv32f16:
645; ZVFHMIN:       # %bb.0:
646; ZVFHMIN-NEXT:    addi sp, sp, -16
647; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 16
648; ZVFHMIN-NEXT:    csrr a1, vlenb
649; ZVFHMIN-NEXT:    slli a1, a1, 3
650; ZVFHMIN-NEXT:    mv a2, a1
651; ZVFHMIN-NEXT:    slli a1, a1, 1
652; ZVFHMIN-NEXT:    add a1, a1, a2
653; ZVFHMIN-NEXT:    sub sp, sp, a1
654; ZVFHMIN-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
655; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
656; ZVFHMIN-NEXT:    vmv1r.v v7, v0
657; ZVFHMIN-NEXT:    vmv8r.v v16, v8
658; ZVFHMIN-NEXT:    fmv.x.h a1, fa0
659; ZVFHMIN-NEXT:    csrr a2, vlenb
660; ZVFHMIN-NEXT:    vmv.v.x v8, a1
661; ZVFHMIN-NEXT:    slli a1, a2, 1
662; ZVFHMIN-NEXT:    srli a2, a2, 2
663; ZVFHMIN-NEXT:    sub a3, a0, a1
664; ZVFHMIN-NEXT:    vsetvli a4, zero, e8, mf2, ta, ma
665; ZVFHMIN-NEXT:    vslidedown.vx v0, v0, a2
666; ZVFHMIN-NEXT:    sltu a2, a0, a3
667; ZVFHMIN-NEXT:    addi a2, a2, -1
668; ZVFHMIN-NEXT:    and a2, a2, a3
669; ZVFHMIN-NEXT:    csrr a3, vlenb
670; ZVFHMIN-NEXT:    slli a3, a3, 3
671; ZVFHMIN-NEXT:    add a3, sp, a3
672; ZVFHMIN-NEXT:    addi a3, a3, 16
673; ZVFHMIN-NEXT:    vs8r.v v8, (a3) # Unknown-size Folded Spill
674; ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
675; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v12, v0.t
676; ZVFHMIN-NEXT:    vmv4r.v v8, v16
677; ZVFHMIN-NEXT:    csrr a2, vlenb
678; ZVFHMIN-NEXT:    slli a2, a2, 4
679; ZVFHMIN-NEXT:    add a2, sp, a2
680; ZVFHMIN-NEXT:    addi a2, a2, 16
681; ZVFHMIN-NEXT:    vs8r.v v8, (a2) # Unknown-size Folded Spill
682; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v20, v0.t
683; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
684; ZVFHMIN-NEXT:    vfmul.vv v24, v8, v24, v0.t
685; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
686; ZVFHMIN-NEXT:    vfncvt.f.f.w v12, v24, v0.t
687; ZVFHMIN-NEXT:    bltu a0, a1, .LBB22_2
688; ZVFHMIN-NEXT:  # %bb.1:
689; ZVFHMIN-NEXT:    mv a0, a1
690; ZVFHMIN-NEXT:  .LBB22_2:
691; ZVFHMIN-NEXT:    vmv1r.v v0, v7
692; ZVFHMIN-NEXT:    csrr a1, vlenb
693; ZVFHMIN-NEXT:    slli a1, a1, 4
694; ZVFHMIN-NEXT:    add a1, sp, a1
695; ZVFHMIN-NEXT:    addi a1, a1, 16
696; ZVFHMIN-NEXT:    vl8r.v v24, (a1) # Unknown-size Folded Reload
697; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
698; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24, v0.t
699; ZVFHMIN-NEXT:    addi a0, sp, 16
700; ZVFHMIN-NEXT:    vs8r.v v16, (a0) # Unknown-size Folded Spill
701; ZVFHMIN-NEXT:    csrr a0, vlenb
702; ZVFHMIN-NEXT:    slli a0, a0, 3
703; ZVFHMIN-NEXT:    add a0, sp, a0
704; ZVFHMIN-NEXT:    addi a0, a0, 16
705; ZVFHMIN-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
706; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24, v0.t
707; ZVFHMIN-NEXT:    vmv8r.v v24, v16
708; ZVFHMIN-NEXT:    addi a0, sp, 16
709; ZVFHMIN-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
710; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
711; ZVFHMIN-NEXT:    vfmul.vv v24, v16, v24, v0.t
712; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
713; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v24, v0.t
714; ZVFHMIN-NEXT:    csrr a0, vlenb
715; ZVFHMIN-NEXT:    slli a0, a0, 3
716; ZVFHMIN-NEXT:    mv a1, a0
717; ZVFHMIN-NEXT:    slli a0, a0, 1
718; ZVFHMIN-NEXT:    add a0, a0, a1
719; ZVFHMIN-NEXT:    add sp, sp, a0
720; ZVFHMIN-NEXT:    .cfi_def_cfa sp, 16
721; ZVFHMIN-NEXT:    addi sp, sp, 16
722; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
723; ZVFHMIN-NEXT:    ret
724  %elt.head = insertelement <vscale x 32 x half> poison, half %b, i32 0
725  %vb = shufflevector <vscale x 32 x half> %elt.head, <vscale x 32 x half> poison, <vscale x 32 x i32> zeroinitializer
726  %v = call <vscale x 32 x half> @llvm.vp.fmul.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> %m, i32 %evl)
727  ret <vscale x 32 x half> %v
728}
729
730define <vscale x 32 x half> @vfmul_vf_nxv32f16_unmasked(<vscale x 32 x half> %va, half %b, i32 zeroext %evl) {
731; ZVFH-LABEL: vfmul_vf_nxv32f16_unmasked:
732; ZVFH:       # %bb.0:
733; ZVFH-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
734; ZVFH-NEXT:    vfmul.vf v8, v8, fa0
735; ZVFH-NEXT:    ret
736;
737; ZVFHMIN-LABEL: vfmul_vf_nxv32f16_unmasked:
738; ZVFHMIN:       # %bb.0:
739; ZVFHMIN-NEXT:    addi sp, sp, -16
740; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 16
741; ZVFHMIN-NEXT:    csrr a1, vlenb
742; ZVFHMIN-NEXT:    slli a1, a1, 3
743; ZVFHMIN-NEXT:    sub sp, sp, a1
744; ZVFHMIN-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
745; ZVFHMIN-NEXT:    fmv.x.h a1, fa0
746; ZVFHMIN-NEXT:    csrr a2, vlenb
747; ZVFHMIN-NEXT:    vsetvli a3, zero, e16, m8, ta, ma
748; ZVFHMIN-NEXT:    vmset.m v24
749; ZVFHMIN-NEXT:    vmv.v.x v16, a1
750; ZVFHMIN-NEXT:    slli a1, a2, 1
751; ZVFHMIN-NEXT:    srli a2, a2, 2
752; ZVFHMIN-NEXT:    sub a3, a0, a1
753; ZVFHMIN-NEXT:    vsetvli a4, zero, e8, mf2, ta, ma
754; ZVFHMIN-NEXT:    vslidedown.vx v0, v24, a2
755; ZVFHMIN-NEXT:    sltu a2, a0, a3
756; ZVFHMIN-NEXT:    addi a2, a2, -1
757; ZVFHMIN-NEXT:    and a2, a2, a3
758; ZVFHMIN-NEXT:    addi a3, sp, 16
759; ZVFHMIN-NEXT:    vs8r.v v16, (a3) # Unknown-size Folded Spill
760; ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
761; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v20, v0.t
762; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v12, v0.t
763; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
764; ZVFHMIN-NEXT:    vfmul.vv v16, v16, v24, v0.t
765; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
766; ZVFHMIN-NEXT:    vfncvt.f.f.w v12, v16, v0.t
767; ZVFHMIN-NEXT:    bltu a0, a1, .LBB23_2
768; ZVFHMIN-NEXT:  # %bb.1:
769; ZVFHMIN-NEXT:    mv a0, a1
770; ZVFHMIN-NEXT:  .LBB23_2:
771; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
772; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v8
773; ZVFHMIN-NEXT:    addi a0, sp, 16
774; ZVFHMIN-NEXT:    vl8r.v v0, (a0) # Unknown-size Folded Reload
775; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v0
776; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
777; ZVFHMIN-NEXT:    vfmul.vv v16, v16, v24
778; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
779; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v16
780; ZVFHMIN-NEXT:    csrr a0, vlenb
781; ZVFHMIN-NEXT:    slli a0, a0, 3
782; ZVFHMIN-NEXT:    add sp, sp, a0
783; ZVFHMIN-NEXT:    .cfi_def_cfa sp, 16
784; ZVFHMIN-NEXT:    addi sp, sp, 16
785; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
786; ZVFHMIN-NEXT:    ret
787  %elt.head = insertelement <vscale x 32 x half> poison, half %b, i32 0
788  %vb = shufflevector <vscale x 32 x half> %elt.head, <vscale x 32 x half> poison, <vscale x 32 x i32> zeroinitializer
789  %v = call <vscale x 32 x half> @llvm.vp.fmul.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)
790  ret <vscale x 32 x half> %v
791}
792
793declare <vscale x 1 x float> @llvm.vp.fmul.nxv1f32(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i32)
794
795define <vscale x 1 x float> @vfmul_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
796; CHECK-LABEL: vfmul_vv_nxv1f32:
797; CHECK:       # %bb.0:
798; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
799; CHECK-NEXT:    vfmul.vv v8, v8, v9, v0.t
800; CHECK-NEXT:    ret
801  %v = call <vscale x 1 x float> @llvm.vp.fmul.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %b, <vscale x 1 x i1> %m, i32 %evl)
802  ret <vscale x 1 x float> %v
803}
804
805define <vscale x 1 x float> @vfmul_vv_nxv1f32_unmasked(<vscale x 1 x float> %va, <vscale x 1 x float> %b, i32 zeroext %evl) {
806; CHECK-LABEL: vfmul_vv_nxv1f32_unmasked:
807; CHECK:       # %bb.0:
808; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
809; CHECK-NEXT:    vfmul.vv v8, v8, v9
810; CHECK-NEXT:    ret
811  %v = call <vscale x 1 x float> @llvm.vp.fmul.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
812  ret <vscale x 1 x float> %v
813}
814
815define <vscale x 1 x float> @vfmul_vf_nxv1f32(<vscale x 1 x float> %va, float %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
816; CHECK-LABEL: vfmul_vf_nxv1f32:
817; CHECK:       # %bb.0:
818; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
819; CHECK-NEXT:    vfmul.vf v8, v8, fa0, v0.t
820; CHECK-NEXT:    ret
821  %elt.head = insertelement <vscale x 1 x float> poison, float %b, i32 0
822  %vb = shufflevector <vscale x 1 x float> %elt.head, <vscale x 1 x float> poison, <vscale x 1 x i32> zeroinitializer
823  %v = call <vscale x 1 x float> @llvm.vp.fmul.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x i1> %m, i32 %evl)
824  ret <vscale x 1 x float> %v
825}
826
827define <vscale x 1 x float> @vfmul_vf_nxv1f32_unmasked(<vscale x 1 x float> %va, float %b, i32 zeroext %evl) {
828; CHECK-LABEL: vfmul_vf_nxv1f32_unmasked:
829; CHECK:       # %bb.0:
830; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
831; CHECK-NEXT:    vfmul.vf v8, v8, fa0
832; CHECK-NEXT:    ret
833  %elt.head = insertelement <vscale x 1 x float> poison, float %b, i32 0
834  %vb = shufflevector <vscale x 1 x float> %elt.head, <vscale x 1 x float> poison, <vscale x 1 x i32> zeroinitializer
835  %v = call <vscale x 1 x float> @llvm.vp.fmul.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)
836  ret <vscale x 1 x float> %v
837}
838
839declare <vscale x 2 x float> @llvm.vp.fmul.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i32)
840
841define <vscale x 2 x float> @vfmul_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
842; CHECK-LABEL: vfmul_vv_nxv2f32:
843; CHECK:       # %bb.0:
844; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
845; CHECK-NEXT:    vfmul.vv v8, v8, v9, v0.t
846; CHECK-NEXT:    ret
847  %v = call <vscale x 2 x float> @llvm.vp.fmul.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %b, <vscale x 2 x i1> %m, i32 %evl)
848  ret <vscale x 2 x float> %v
849}
850
851define <vscale x 2 x float> @vfmul_vv_nxv2f32_unmasked(<vscale x 2 x float> %va, <vscale x 2 x float> %b, i32 zeroext %evl) {
852; CHECK-LABEL: vfmul_vv_nxv2f32_unmasked:
853; CHECK:       # %bb.0:
854; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
855; CHECK-NEXT:    vfmul.vv v8, v8, v9
856; CHECK-NEXT:    ret
857  %v = call <vscale x 2 x float> @llvm.vp.fmul.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
858  ret <vscale x 2 x float> %v
859}
860
861define <vscale x 2 x float> @vfmul_vf_nxv2f32(<vscale x 2 x float> %va, float %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
862; CHECK-LABEL: vfmul_vf_nxv2f32:
863; CHECK:       # %bb.0:
864; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
865; CHECK-NEXT:    vfmul.vf v8, v8, fa0, v0.t
866; CHECK-NEXT:    ret
867  %elt.head = insertelement <vscale x 2 x float> poison, float %b, i32 0
868  %vb = shufflevector <vscale x 2 x float> %elt.head, <vscale x 2 x float> poison, <vscale x 2 x i32> zeroinitializer
869  %v = call <vscale x 2 x float> @llvm.vp.fmul.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> %m, i32 %evl)
870  ret <vscale x 2 x float> %v
871}
872
873define <vscale x 2 x float> @vfmul_vf_nxv2f32_unmasked(<vscale x 2 x float> %va, float %b, i32 zeroext %evl) {
874; CHECK-LABEL: vfmul_vf_nxv2f32_unmasked:
875; CHECK:       # %bb.0:
876; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
877; CHECK-NEXT:    vfmul.vf v8, v8, fa0
878; CHECK-NEXT:    ret
879  %elt.head = insertelement <vscale x 2 x float> poison, float %b, i32 0
880  %vb = shufflevector <vscale x 2 x float> %elt.head, <vscale x 2 x float> poison, <vscale x 2 x i32> zeroinitializer
881  %v = call <vscale x 2 x float> @llvm.vp.fmul.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)
882  ret <vscale x 2 x float> %v
883}
884
885declare <vscale x 4 x float> @llvm.vp.fmul.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i32)
886
887define <vscale x 4 x float> @vfmul_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
888; CHECK-LABEL: vfmul_vv_nxv4f32:
889; CHECK:       # %bb.0:
890; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
891; CHECK-NEXT:    vfmul.vv v8, v8, v10, v0.t
892; CHECK-NEXT:    ret
893  %v = call <vscale x 4 x float> @llvm.vp.fmul.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %b, <vscale x 4 x i1> %m, i32 %evl)
894  ret <vscale x 4 x float> %v
895}
896
897define <vscale x 4 x float> @vfmul_vv_nxv4f32_unmasked(<vscale x 4 x float> %va, <vscale x 4 x float> %b, i32 zeroext %evl) {
898; CHECK-LABEL: vfmul_vv_nxv4f32_unmasked:
899; CHECK:       # %bb.0:
900; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
901; CHECK-NEXT:    vfmul.vv v8, v8, v10
902; CHECK-NEXT:    ret
903  %v = call <vscale x 4 x float> @llvm.vp.fmul.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
904  ret <vscale x 4 x float> %v
905}
906
907define <vscale x 4 x float> @vfmul_vf_nxv4f32(<vscale x 4 x float> %va, float %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
908; CHECK-LABEL: vfmul_vf_nxv4f32:
909; CHECK:       # %bb.0:
910; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
911; CHECK-NEXT:    vfmul.vf v8, v8, fa0, v0.t
912; CHECK-NEXT:    ret
913  %elt.head = insertelement <vscale x 4 x float> poison, float %b, i32 0
914  %vb = shufflevector <vscale x 4 x float> %elt.head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
915  %v = call <vscale x 4 x float> @llvm.vp.fmul.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x i1> %m, i32 %evl)
916  ret <vscale x 4 x float> %v
917}
918
919define <vscale x 4 x float> @vfmul_vf_nxv4f32_unmasked(<vscale x 4 x float> %va, float %b, i32 zeroext %evl) {
920; CHECK-LABEL: vfmul_vf_nxv4f32_unmasked:
921; CHECK:       # %bb.0:
922; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
923; CHECK-NEXT:    vfmul.vf v8, v8, fa0
924; CHECK-NEXT:    ret
925  %elt.head = insertelement <vscale x 4 x float> poison, float %b, i32 0
926  %vb = shufflevector <vscale x 4 x float> %elt.head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
927  %v = call <vscale x 4 x float> @llvm.vp.fmul.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)
928  ret <vscale x 4 x float> %v
929}
930
931declare <vscale x 8 x float> @llvm.vp.fmul.nxv8f32(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x i1>, i32)
932
933define <vscale x 8 x float> @vfmul_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
934; CHECK-LABEL: vfmul_vv_nxv8f32:
935; CHECK:       # %bb.0:
936; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
937; CHECK-NEXT:    vfmul.vv v8, v8, v12, v0.t
938; CHECK-NEXT:    ret
939  %v = call <vscale x 8 x float> @llvm.vp.fmul.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %b, <vscale x 8 x i1> %m, i32 %evl)
940  ret <vscale x 8 x float> %v
941}
942
943define <vscale x 8 x float> @vfmul_vv_nxv8f32_unmasked(<vscale x 8 x float> %va, <vscale x 8 x float> %b, i32 zeroext %evl) {
944; CHECK-LABEL: vfmul_vv_nxv8f32_unmasked:
945; CHECK:       # %bb.0:
946; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
947; CHECK-NEXT:    vfmul.vv v8, v8, v12
948; CHECK-NEXT:    ret
949  %v = call <vscale x 8 x float> @llvm.vp.fmul.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
950  ret <vscale x 8 x float> %v
951}
952
953define <vscale x 8 x float> @vfmul_vf_nxv8f32(<vscale x 8 x float> %va, float %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
954; CHECK-LABEL: vfmul_vf_nxv8f32:
955; CHECK:       # %bb.0:
956; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
957; CHECK-NEXT:    vfmul.vf v8, v8, fa0, v0.t
958; CHECK-NEXT:    ret
959  %elt.head = insertelement <vscale x 8 x float> poison, float %b, i32 0
960  %vb = shufflevector <vscale x 8 x float> %elt.head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
961  %v = call <vscale x 8 x float> @llvm.vp.fmul.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %m, i32 %evl)
962  ret <vscale x 8 x float> %v
963}
964
965define <vscale x 8 x float> @vfmul_vf_nxv8f32_unmasked(<vscale x 8 x float> %va, float %b, i32 zeroext %evl) {
966; CHECK-LABEL: vfmul_vf_nxv8f32_unmasked:
967; CHECK:       # %bb.0:
968; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
969; CHECK-NEXT:    vfmul.vf v8, v8, fa0
970; CHECK-NEXT:    ret
971  %elt.head = insertelement <vscale x 8 x float> poison, float %b, i32 0
972  %vb = shufflevector <vscale x 8 x float> %elt.head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
973  %v = call <vscale x 8 x float> @llvm.vp.fmul.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)
974  ret <vscale x 8 x float> %v
975}
976
977declare <vscale x 16 x float> @llvm.vp.fmul.nxv16f32(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x i1>, i32)
978
979define <vscale x 16 x float> @vfmul_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
980; CHECK-LABEL: vfmul_vv_nxv16f32:
981; CHECK:       # %bb.0:
982; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
983; CHECK-NEXT:    vfmul.vv v8, v8, v16, v0.t
984; CHECK-NEXT:    ret
985  %v = call <vscale x 16 x float> @llvm.vp.fmul.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %b, <vscale x 16 x i1> %m, i32 %evl)
986  ret <vscale x 16 x float> %v
987}
988
989define <vscale x 16 x float> @vfmul_vv_nxv16f32_unmasked(<vscale x 16 x float> %va, <vscale x 16 x float> %b, i32 zeroext %evl) {
990; CHECK-LABEL: vfmul_vv_nxv16f32_unmasked:
991; CHECK:       # %bb.0:
992; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
993; CHECK-NEXT:    vfmul.vv v8, v8, v16
994; CHECK-NEXT:    ret
995  %v = call <vscale x 16 x float> @llvm.vp.fmul.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)
996  ret <vscale x 16 x float> %v
997}
998
999define <vscale x 16 x float> @vfmul_vf_nxv16f32(<vscale x 16 x float> %va, float %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
1000; CHECK-LABEL: vfmul_vf_nxv16f32:
1001; CHECK:       # %bb.0:
1002; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
1003; CHECK-NEXT:    vfmul.vf v8, v8, fa0, v0.t
1004; CHECK-NEXT:    ret
1005  %elt.head = insertelement <vscale x 16 x float> poison, float %b, i32 0
1006  %vb = shufflevector <vscale x 16 x float> %elt.head, <vscale x 16 x float> poison, <vscale x 16 x i32> zeroinitializer
1007  %v = call <vscale x 16 x float> @llvm.vp.fmul.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x i1> %m, i32 %evl)
1008  ret <vscale x 16 x float> %v
1009}
1010
1011define <vscale x 16 x float> @vfmul_vf_nxv16f32_unmasked(<vscale x 16 x float> %va, float %b, i32 zeroext %evl) {
1012; CHECK-LABEL: vfmul_vf_nxv16f32_unmasked:
1013; CHECK:       # %bb.0:
1014; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
1015; CHECK-NEXT:    vfmul.vf v8, v8, fa0
1016; CHECK-NEXT:    ret
1017  %elt.head = insertelement <vscale x 16 x float> poison, float %b, i32 0
1018  %vb = shufflevector <vscale x 16 x float> %elt.head, <vscale x 16 x float> poison, <vscale x 16 x i32> zeroinitializer
1019  %v = call <vscale x 16 x float> @llvm.vp.fmul.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)
1020  ret <vscale x 16 x float> %v
1021}
1022
1023declare <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i32)
1024
1025define <vscale x 1 x double> @vfmul_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
1026; CHECK-LABEL: vfmul_vv_nxv1f64:
1027; CHECK:       # %bb.0:
1028; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1029; CHECK-NEXT:    vfmul.vv v8, v8, v9, v0.t
1030; CHECK-NEXT:    ret
1031  %v = call <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %b, <vscale x 1 x i1> %m, i32 %evl)
1032  ret <vscale x 1 x double> %v
1033}
1034
1035define <vscale x 1 x double> @vfmul_vv_nxv1f64_unmasked(<vscale x 1 x double> %va, <vscale x 1 x double> %b, i32 zeroext %evl) {
1036; CHECK-LABEL: vfmul_vv_nxv1f64_unmasked:
1037; CHECK:       # %bb.0:
1038; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1039; CHECK-NEXT:    vfmul.vv v8, v8, v9
1040; CHECK-NEXT:    ret
1041  %v = call <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)
1042  ret <vscale x 1 x double> %v
1043}
1044
1045define <vscale x 1 x double> @vfmul_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
1046; CHECK-LABEL: vfmul_vf_nxv1f64:
1047; CHECK:       # %bb.0:
1048; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1049; CHECK-NEXT:    vfmul.vf v8, v8, fa0, v0.t
1050; CHECK-NEXT:    ret
1051  %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
1052  %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
1053  %v = call <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 %evl)
1054  ret <vscale x 1 x double> %v
1055}
1056
1057define <vscale x 1 x double> @vfmul_vf_nxv1f64_unmasked(<vscale x 1 x double> %va, double %b, i32 zeroext %evl) {
1058; CHECK-LABEL: vfmul_vf_nxv1f64_unmasked:
1059; CHECK:       # %bb.0:
1060; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1061; CHECK-NEXT:    vfmul.vf v8, v8, fa0
1062; CHECK-NEXT:    ret
1063  %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
1064  %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
1065  %v = call <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)
1066  ret <vscale x 1 x double> %v
1067}
1068
1069declare <vscale x 2 x double> @llvm.vp.fmul.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i32)
1070
1071define <vscale x 2 x double> @vfmul_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
1072; CHECK-LABEL: vfmul_vv_nxv2f64:
1073; CHECK:       # %bb.0:
1074; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1075; CHECK-NEXT:    vfmul.vv v8, v8, v10, v0.t
1076; CHECK-NEXT:    ret
1077  %v = call <vscale x 2 x double> @llvm.vp.fmul.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %b, <vscale x 2 x i1> %m, i32 %evl)
1078  ret <vscale x 2 x double> %v
1079}
1080
1081define <vscale x 2 x double> @vfmul_vv_nxv2f64_unmasked(<vscale x 2 x double> %va, <vscale x 2 x double> %b, i32 zeroext %evl) {
1082; CHECK-LABEL: vfmul_vv_nxv2f64_unmasked:
1083; CHECK:       # %bb.0:
1084; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1085; CHECK-NEXT:    vfmul.vv v8, v8, v10
1086; CHECK-NEXT:    ret
1087  %v = call <vscale x 2 x double> @llvm.vp.fmul.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)
1088  ret <vscale x 2 x double> %v
1089}
1090
1091define <vscale x 2 x double> @vfmul_vf_nxv2f64(<vscale x 2 x double> %va, double %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
1092; CHECK-LABEL: vfmul_vf_nxv2f64:
1093; CHECK:       # %bb.0:
1094; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1095; CHECK-NEXT:    vfmul.vf v8, v8, fa0, v0.t
1096; CHECK-NEXT:    ret
1097  %elt.head = insertelement <vscale x 2 x double> poison, double %b, i32 0
1098  %vb = shufflevector <vscale x 2 x double> %elt.head, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
1099  %v = call <vscale x 2 x double> @llvm.vp.fmul.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x i1> %m, i32 %evl)
1100  ret <vscale x 2 x double> %v
1101}
1102
1103define <vscale x 2 x double> @vfmul_vf_nxv2f64_unmasked(<vscale x 2 x double> %va, double %b, i32 zeroext %evl) {
1104; CHECK-LABEL: vfmul_vf_nxv2f64_unmasked:
1105; CHECK:       # %bb.0:
1106; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1107; CHECK-NEXT:    vfmul.vf v8, v8, fa0
1108; CHECK-NEXT:    ret
1109  %elt.head = insertelement <vscale x 2 x double> poison, double %b, i32 0
1110  %vb = shufflevector <vscale x 2 x double> %elt.head, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
1111  %v = call <vscale x 2 x double> @llvm.vp.fmul.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)
1112  ret <vscale x 2 x double> %v
1113}
1114
1115declare <vscale x 4 x double> @llvm.vp.fmul.nxv4f64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i32)
1116
1117define <vscale x 4 x double> @vfmul_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
1118; CHECK-LABEL: vfmul_vv_nxv4f64:
1119; CHECK:       # %bb.0:
1120; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1121; CHECK-NEXT:    vfmul.vv v8, v8, v12, v0.t
1122; CHECK-NEXT:    ret
1123  %v = call <vscale x 4 x double> @llvm.vp.fmul.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %b, <vscale x 4 x i1> %m, i32 %evl)
1124  ret <vscale x 4 x double> %v
1125}
1126
1127define <vscale x 4 x double> @vfmul_vv_nxv4f64_unmasked(<vscale x 4 x double> %va, <vscale x 4 x double> %b, i32 zeroext %evl) {
1128; CHECK-LABEL: vfmul_vv_nxv4f64_unmasked:
1129; CHECK:       # %bb.0:
1130; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1131; CHECK-NEXT:    vfmul.vv v8, v8, v12
1132; CHECK-NEXT:    ret
1133  %v = call <vscale x 4 x double> @llvm.vp.fmul.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)
1134  ret <vscale x 4 x double> %v
1135}
1136
1137define <vscale x 4 x double> @vfmul_vf_nxv4f64(<vscale x 4 x double> %va, double %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
1138; CHECK-LABEL: vfmul_vf_nxv4f64:
1139; CHECK:       # %bb.0:
1140; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1141; CHECK-NEXT:    vfmul.vf v8, v8, fa0, v0.t
1142; CHECK-NEXT:    ret
1143  %elt.head = insertelement <vscale x 4 x double> poison, double %b, i32 0
1144  %vb = shufflevector <vscale x 4 x double> %elt.head, <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer
1145  %v = call <vscale x 4 x double> @llvm.vp.fmul.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x i1> %m, i32 %evl)
1146  ret <vscale x 4 x double> %v
1147}
1148
1149define <vscale x 4 x double> @vfmul_vf_nxv4f64_unmasked(<vscale x 4 x double> %va, double %b, i32 zeroext %evl) {
1150; CHECK-LABEL: vfmul_vf_nxv4f64_unmasked:
1151; CHECK:       # %bb.0:
1152; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1153; CHECK-NEXT:    vfmul.vf v8, v8, fa0
1154; CHECK-NEXT:    ret
1155  %elt.head = insertelement <vscale x 4 x double> poison, double %b, i32 0
1156  %vb = shufflevector <vscale x 4 x double> %elt.head, <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer
1157  %v = call <vscale x 4 x double> @llvm.vp.fmul.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)
1158  ret <vscale x 4 x double> %v
1159}
1160
1161declare <vscale x 7 x double> @llvm.vp.fmul.nxv7f64(<vscale x 7 x double>, <vscale x 7 x double>, <vscale x 7 x i1>, i32)
1162
1163define <vscale x 7 x double> @vfmul_vv_nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x double> %b, <vscale x 7 x i1> %m, i32 zeroext %evl) {
1164; CHECK-LABEL: vfmul_vv_nxv7f64:
1165; CHECK:       # %bb.0:
1166; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1167; CHECK-NEXT:    vfmul.vv v8, v8, v16, v0.t
1168; CHECK-NEXT:    ret
1169  %v = call <vscale x 7 x double> @llvm.vp.fmul.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x double> %b, <vscale x 7 x i1> %m, i32 %evl)
1170  ret <vscale x 7 x double> %v
1171}
1172
1173declare <vscale x 8 x double> @llvm.vp.fmul.nxv8f64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i32)
1174
1175define <vscale x 8 x double> @vfmul_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
1176; CHECK-LABEL: vfmul_vv_nxv8f64:
1177; CHECK:       # %bb.0:
1178; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1179; CHECK-NEXT:    vfmul.vv v8, v8, v16, v0.t
1180; CHECK-NEXT:    ret
1181  %v = call <vscale x 8 x double> @llvm.vp.fmul.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %b, <vscale x 8 x i1> %m, i32 %evl)
1182  ret <vscale x 8 x double> %v
1183}
1184
1185define <vscale x 8 x double> @vfmul_vv_nxv8f64_unmasked(<vscale x 8 x double> %va, <vscale x 8 x double> %b, i32 zeroext %evl) {
1186; CHECK-LABEL: vfmul_vv_nxv8f64_unmasked:
1187; CHECK:       # %bb.0:
1188; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1189; CHECK-NEXT:    vfmul.vv v8, v8, v16
1190; CHECK-NEXT:    ret
1191  %v = call <vscale x 8 x double> @llvm.vp.fmul.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)
1192  ret <vscale x 8 x double> %v
1193}
1194
1195define <vscale x 8 x double> @vfmul_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
1196; CHECK-LABEL: vfmul_vf_nxv8f64:
1197; CHECK:       # %bb.0:
1198; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1199; CHECK-NEXT:    vfmul.vf v8, v8, fa0, v0.t
1200; CHECK-NEXT:    ret
1201  %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
1202  %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
1203  %v = call <vscale x 8 x double> @llvm.vp.fmul.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 %evl)
1204  ret <vscale x 8 x double> %v
1205}
1206
1207define <vscale x 8 x double> @vfmul_vf_nxv8f64_unmasked(<vscale x 8 x double> %va, double %b, i32 zeroext %evl) {
1208; CHECK-LABEL: vfmul_vf_nxv8f64_unmasked:
1209; CHECK:       # %bb.0:
1210; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1211; CHECK-NEXT:    vfmul.vf v8, v8, fa0
1212; CHECK-NEXT:    ret
1213  %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
1214  %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
1215  %v = call <vscale x 8 x double> @llvm.vp.fmul.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)
1216  ret <vscale x 8 x double> %v
1217}
1218