xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll (revision 8ce81f17a16b8b689895c7c093d0401a75c09882) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \
3; RUN:     -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
4; RUN:     --check-prefixes=CHECK,ZVFH
5; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \
6; RUN:     -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
7; RUN:     --check-prefixes=CHECK,ZVFH
8; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \
9; RUN:     -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
10; RUN:     --check-prefixes=CHECK,ZVFHMIN
11; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \
12; RUN:     -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
13; RUN:     --check-prefixes=CHECK,ZVFHMIN
14
15declare <vscale x 1 x bfloat> @llvm.vp.minnum.nxv1bf16(<vscale x 1 x bfloat>, <vscale x 1 x bfloat>, <vscale x 1 x i1>, i32)
16
17define <vscale x 1 x bfloat> @vfmin_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
18; CHECK-LABEL: vfmin_vv_nxv1bf16:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
21; CHECK-NEXT:    vfwcvtbf16.f.f.v v10, v9, v0.t
22; CHECK-NEXT:    vfwcvtbf16.f.f.v v9, v8, v0.t
23; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
24; CHECK-NEXT:    vfmin.vv v9, v9, v10, v0.t
25; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
26; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v9, v0.t
27; CHECK-NEXT:    ret
28  %v = call <vscale x 1 x bfloat> @llvm.vp.minnum.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x i1> %m, i32 %evl)
29  ret <vscale x 1 x bfloat> %v
30}
31
32define <vscale x 1 x bfloat> @vfmin_vv_nxv1bf16_unmasked(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, i32 zeroext %evl) {
33; CHECK-LABEL: vfmin_vv_nxv1bf16_unmasked:
34; CHECK:       # %bb.0:
35; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
36; CHECK-NEXT:    vfwcvtbf16.f.f.v v10, v9
37; CHECK-NEXT:    vfwcvtbf16.f.f.v v9, v8
38; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
39; CHECK-NEXT:    vfmin.vv v9, v9, v10
40; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
41; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v9
42; CHECK-NEXT:    ret
43  %v = call <vscale x 1 x bfloat> @llvm.vp.minnum.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)
44  ret <vscale x 1 x bfloat> %v
45}
46
47declare <vscale x 2 x bfloat> @llvm.vp.minnum.nxv2bf16(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, <vscale x 2 x i1>, i32)
48
49define <vscale x 2 x bfloat> @vfmin_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {
50; CHECK-LABEL: vfmin_vv_nxv2bf16:
51; CHECK:       # %bb.0:
52; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
53; CHECK-NEXT:    vfwcvtbf16.f.f.v v10, v9, v0.t
54; CHECK-NEXT:    vfwcvtbf16.f.f.v v9, v8, v0.t
55; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
56; CHECK-NEXT:    vfmin.vv v9, v9, v10, v0.t
57; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
58; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v9, v0.t
59; CHECK-NEXT:    ret
60  %v = call <vscale x 2 x bfloat> @llvm.vp.minnum.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %m, i32 %evl)
61  ret <vscale x 2 x bfloat> %v
62}
63
64define <vscale x 2 x bfloat> @vfmin_vv_nxv2bf16_unmasked(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 zeroext %evl) {
65; CHECK-LABEL: vfmin_vv_nxv2bf16_unmasked:
66; CHECK:       # %bb.0:
67; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
68; CHECK-NEXT:    vfwcvtbf16.f.f.v v10, v9
69; CHECK-NEXT:    vfwcvtbf16.f.f.v v9, v8
70; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
71; CHECK-NEXT:    vfmin.vv v9, v9, v10
72; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
73; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v9
74; CHECK-NEXT:    ret
75  %v = call <vscale x 2 x bfloat> @llvm.vp.minnum.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)
76  ret <vscale x 2 x bfloat> %v
77}
78
79declare <vscale x 4 x bfloat> @llvm.vp.minnum.nxv4bf16(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, <vscale x 4 x i1>, i32)
80
81define <vscale x 4 x bfloat> @vfmin_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
82; CHECK-LABEL: vfmin_vv_nxv4bf16:
83; CHECK:       # %bb.0:
84; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
85; CHECK-NEXT:    vfwcvtbf16.f.f.v v10, v9, v0.t
86; CHECK-NEXT:    vfwcvtbf16.f.f.v v12, v8, v0.t
87; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
88; CHECK-NEXT:    vfmin.vv v10, v12, v10, v0.t
89; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
90; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v10, v0.t
91; CHECK-NEXT:    ret
92  %v = call <vscale x 4 x bfloat> @llvm.vp.minnum.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> %m, i32 %evl)
93  ret <vscale x 4 x bfloat> %v
94}
95
96define <vscale x 4 x bfloat> @vfmin_vv_nxv4bf16_unmasked(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, i32 zeroext %evl) {
97; CHECK-LABEL: vfmin_vv_nxv4bf16_unmasked:
98; CHECK:       # %bb.0:
99; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
100; CHECK-NEXT:    vfwcvtbf16.f.f.v v10, v9
101; CHECK-NEXT:    vfwcvtbf16.f.f.v v12, v8
102; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
103; CHECK-NEXT:    vfmin.vv v10, v12, v10
104; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
105; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v10
106; CHECK-NEXT:    ret
107  %v = call <vscale x 4 x bfloat> @llvm.vp.minnum.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)
108  ret <vscale x 4 x bfloat> %v
109}
110
111declare <vscale x 8 x bfloat> @llvm.vp.minnum.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x i1>, i32)
112
113define <vscale x 8 x bfloat> @vfmin_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
114; CHECK-LABEL: vfmin_vv_nxv8bf16:
115; CHECK:       # %bb.0:
116; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
117; CHECK-NEXT:    vfwcvtbf16.f.f.v v12, v10, v0.t
118; CHECK-NEXT:    vfwcvtbf16.f.f.v v16, v8, v0.t
119; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
120; CHECK-NEXT:    vfmin.vv v12, v16, v12, v0.t
121; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
122; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v12, v0.t
123; CHECK-NEXT:    ret
124  %v = call <vscale x 8 x bfloat> @llvm.vp.minnum.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> %m, i32 %evl)
125  ret <vscale x 8 x bfloat> %v
126}
127
128define <vscale x 8 x bfloat> @vfmin_vv_nxv8bf16_unmasked(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, i32 zeroext %evl) {
129; CHECK-LABEL: vfmin_vv_nxv8bf16_unmasked:
130; CHECK:       # %bb.0:
131; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
132; CHECK-NEXT:    vfwcvtbf16.f.f.v v12, v10
133; CHECK-NEXT:    vfwcvtbf16.f.f.v v16, v8
134; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
135; CHECK-NEXT:    vfmin.vv v12, v16, v12
136; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
137; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v12
138; CHECK-NEXT:    ret
139  %v = call <vscale x 8 x bfloat> @llvm.vp.minnum.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)
140  ret <vscale x 8 x bfloat> %v
141}
142
143declare <vscale x 16 x bfloat> @llvm.vp.minnum.nxv16bf16(<vscale x 16 x bfloat>, <vscale x 16 x bfloat>, <vscale x 16 x i1>, i32)
144
145define <vscale x 16 x bfloat> @vfmin_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {
146; CHECK-LABEL: vfmin_vv_nxv16bf16:
147; CHECK:       # %bb.0:
148; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
149; CHECK-NEXT:    vfwcvtbf16.f.f.v v16, v12, v0.t
150; CHECK-NEXT:    vfwcvtbf16.f.f.v v24, v8, v0.t
151; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
152; CHECK-NEXT:    vfmin.vv v16, v24, v16, v0.t
153; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
154; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v16, v0.t
155; CHECK-NEXT:    ret
156  %v = call <vscale x 16 x bfloat> @llvm.vp.minnum.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, <vscale x 16 x i1> %m, i32 %evl)
157  ret <vscale x 16 x bfloat> %v
158}
159
160define <vscale x 16 x bfloat> @vfmin_vv_nxv16bf16_unmasked(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, i32 zeroext %evl) {
161; CHECK-LABEL: vfmin_vv_nxv16bf16_unmasked:
162; CHECK:       # %bb.0:
163; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
164; CHECK-NEXT:    vfwcvtbf16.f.f.v v16, v12
165; CHECK-NEXT:    vfwcvtbf16.f.f.v v24, v8
166; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
167; CHECK-NEXT:    vfmin.vv v16, v24, v16
168; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
169; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v16
170; CHECK-NEXT:    ret
171  %v = call <vscale x 16 x bfloat> @llvm.vp.minnum.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)
172  ret <vscale x 16 x bfloat> %v
173}
174
175declare <vscale x 32 x bfloat> @llvm.vp.minnum.nxv32bf16(<vscale x 32 x bfloat>, <vscale x 32 x bfloat>, <vscale x 32 x i1>, i32)
176
177define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {
178; CHECK-LABEL: vfmin_vv_nxv32bf16:
179; CHECK:       # %bb.0:
180; CHECK-NEXT:    addi sp, sp, -16
181; CHECK-NEXT:    .cfi_def_cfa_offset 16
182; CHECK-NEXT:    csrr a1, vlenb
183; CHECK-NEXT:    slli a1, a1, 3
184; CHECK-NEXT:    mv a2, a1
185; CHECK-NEXT:    slli a1, a1, 1
186; CHECK-NEXT:    add a1, a1, a2
187; CHECK-NEXT:    sub sp, sp, a1
188; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
189; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
190; CHECK-NEXT:    vmv1r.v v7, v0
191; CHECK-NEXT:    csrr a1, vlenb
192; CHECK-NEXT:    slli a1, a1, 4
193; CHECK-NEXT:    add a1, sp, a1
194; CHECK-NEXT:    addi a1, a1, 16
195; CHECK-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
196; CHECK-NEXT:    csrr a2, vlenb
197; CHECK-NEXT:    slli a1, a2, 1
198; CHECK-NEXT:    srli a2, a2, 2
199; CHECK-NEXT:    sub a3, a0, a1
200; CHECK-NEXT:    vslidedown.vx v0, v0, a2
201; CHECK-NEXT:    sltu a2, a0, a3
202; CHECK-NEXT:    addi a2, a2, -1
203; CHECK-NEXT:    and a2, a2, a3
204; CHECK-NEXT:    vmv4r.v v8, v16
205; CHECK-NEXT:    csrr a3, vlenb
206; CHECK-NEXT:    slli a3, a3, 3
207; CHECK-NEXT:    add a3, sp, a3
208; CHECK-NEXT:    addi a3, a3, 16
209; CHECK-NEXT:    vs8r.v v8, (a3) # Unknown-size Folded Spill
210; CHECK-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
211; CHECK-NEXT:    vfwcvtbf16.f.f.v v8, v20, v0.t
212; CHECK-NEXT:    addi a2, sp, 16
213; CHECK-NEXT:    vs8r.v v8, (a2) # Unknown-size Folded Spill
214; CHECK-NEXT:    csrr a2, vlenb
215; CHECK-NEXT:    slli a2, a2, 4
216; CHECK-NEXT:    add a2, sp, a2
217; CHECK-NEXT:    addi a2, a2, 16
218; CHECK-NEXT:    vl8r.v v16, (a2) # Unknown-size Folded Reload
219; CHECK-NEXT:    vfwcvtbf16.f.f.v v8, v20, v0.t
220; CHECK-NEXT:    addi a2, sp, 16
221; CHECK-NEXT:    vl8r.v v16, (a2) # Unknown-size Folded Reload
222; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
223; CHECK-NEXT:    vfmin.vv v16, v8, v16, v0.t
224; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
225; CHECK-NEXT:    vfncvtbf16.f.f.w v12, v16, v0.t
226; CHECK-NEXT:    bltu a0, a1, .LBB10_2
227; CHECK-NEXT:  # %bb.1:
228; CHECK-NEXT:    mv a0, a1
229; CHECK-NEXT:  .LBB10_2:
230; CHECK-NEXT:    vmv1r.v v0, v7
231; CHECK-NEXT:    csrr a1, vlenb
232; CHECK-NEXT:    slli a1, a1, 3
233; CHECK-NEXT:    add a1, sp, a1
234; CHECK-NEXT:    addi a1, a1, 16
235; CHECK-NEXT:    vl8r.v v16, (a1) # Unknown-size Folded Reload
236; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
237; CHECK-NEXT:    vfwcvtbf16.f.f.v v24, v16, v0.t
238; CHECK-NEXT:    addi a0, sp, 16
239; CHECK-NEXT:    vs8r.v v24, (a0) # Unknown-size Folded Spill
240; CHECK-NEXT:    csrr a0, vlenb
241; CHECK-NEXT:    slli a0, a0, 4
242; CHECK-NEXT:    add a0, sp, a0
243; CHECK-NEXT:    addi a0, a0, 16
244; CHECK-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
245; CHECK-NEXT:    vfwcvtbf16.f.f.v v24, v16, v0.t
246; CHECK-NEXT:    addi a0, sp, 16
247; CHECK-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
248; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
249; CHECK-NEXT:    vfmin.vv v16, v24, v16, v0.t
250; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
251; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v16, v0.t
252; CHECK-NEXT:    csrr a0, vlenb
253; CHECK-NEXT:    slli a0, a0, 3
254; CHECK-NEXT:    mv a1, a0
255; CHECK-NEXT:    slli a0, a0, 1
256; CHECK-NEXT:    add a0, a0, a1
257; CHECK-NEXT:    add sp, sp, a0
258; CHECK-NEXT:    .cfi_def_cfa sp, 16
259; CHECK-NEXT:    addi sp, sp, 16
260; CHECK-NEXT:    .cfi_def_cfa_offset 0
261; CHECK-NEXT:    ret
262  %v = call <vscale x 32 x bfloat> @llvm.vp.minnum.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, <vscale x 32 x i1> %m, i32 %evl)
263  ret <vscale x 32 x bfloat> %v
264}
265
266define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, i32 zeroext %evl) {
267; CHECK-LABEL: vfmin_vv_nxv32bf16_unmasked:
268; CHECK:       # %bb.0:
269; CHECK-NEXT:    addi sp, sp, -16
270; CHECK-NEXT:    .cfi_def_cfa_offset 16
271; CHECK-NEXT:    csrr a1, vlenb
272; CHECK-NEXT:    slli a1, a1, 3
273; CHECK-NEXT:    sub sp, sp, a1
274; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
275; CHECK-NEXT:    csrr a2, vlenb
276; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
277; CHECK-NEXT:    vmset.m v24
278; CHECK-NEXT:    slli a1, a2, 1
279; CHECK-NEXT:    srli a2, a2, 2
280; CHECK-NEXT:    sub a3, a0, a1
281; CHECK-NEXT:    vsetvli a4, zero, e8, mf2, ta, ma
282; CHECK-NEXT:    vslidedown.vx v0, v24, a2
283; CHECK-NEXT:    sltu a2, a0, a3
284; CHECK-NEXT:    addi a2, a2, -1
285; CHECK-NEXT:    and a2, a2, a3
286; CHECK-NEXT:    addi a3, sp, 16
287; CHECK-NEXT:    vs8r.v v16, (a3) # Unknown-size Folded Spill
288; CHECK-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
289; CHECK-NEXT:    vfwcvtbf16.f.f.v v24, v20, v0.t
290; CHECK-NEXT:    vfwcvtbf16.f.f.v v16, v12, v0.t
291; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
292; CHECK-NEXT:    vfmin.vv v16, v16, v24, v0.t
293; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
294; CHECK-NEXT:    vfncvtbf16.f.f.w v12, v16, v0.t
295; CHECK-NEXT:    bltu a0, a1, .LBB11_2
296; CHECK-NEXT:  # %bb.1:
297; CHECK-NEXT:    mv a0, a1
298; CHECK-NEXT:  .LBB11_2:
299; CHECK-NEXT:    addi a1, sp, 16
300; CHECK-NEXT:    vl8r.v v24, (a1) # Unknown-size Folded Reload
301; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
302; CHECK-NEXT:    vfwcvtbf16.f.f.v v16, v24
303; CHECK-NEXT:    vfwcvtbf16.f.f.v v24, v8
304; CHECK-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
305; CHECK-NEXT:    vfmin.vv v16, v24, v16
306; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
307; CHECK-NEXT:    vfncvtbf16.f.f.w v8, v16
308; CHECK-NEXT:    csrr a0, vlenb
309; CHECK-NEXT:    slli a0, a0, 3
310; CHECK-NEXT:    add sp, sp, a0
311; CHECK-NEXT:    .cfi_def_cfa sp, 16
312; CHECK-NEXT:    addi sp, sp, 16
313; CHECK-NEXT:    .cfi_def_cfa_offset 0
314; CHECK-NEXT:    ret
315  %v = call <vscale x 32 x bfloat> @llvm.vp.minnum.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)
316  ret <vscale x 32 x bfloat> %v
317}
318declare <vscale x 1 x half> @llvm.vp.minnum.nxv1f16(<vscale x 1 x half>, <vscale x 1 x half>, <vscale x 1 x i1>, i32)
319
320define <vscale x 1 x half> @vfmin_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
321; ZVFH-LABEL: vfmin_vv_nxv1f16:
322; ZVFH:       # %bb.0:
323; ZVFH-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
324; ZVFH-NEXT:    vfmin.vv v8, v8, v9, v0.t
325; ZVFH-NEXT:    ret
326;
327; ZVFHMIN-LABEL: vfmin_vv_nxv1f16:
328; ZVFHMIN:       # %bb.0:
329; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
330; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9, v0.t
331; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8, v0.t
332; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
333; ZVFHMIN-NEXT:    vfmin.vv v9, v9, v10, v0.t
334; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
335; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9, v0.t
336; ZVFHMIN-NEXT:    ret
337  %v = call <vscale x 1 x half> @llvm.vp.minnum.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 %evl)
338  ret <vscale x 1 x half> %v
339}
340
341define <vscale x 1 x half> @vfmin_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, i32 zeroext %evl) {
342; ZVFH-LABEL: vfmin_vv_nxv1f16_unmasked:
343; ZVFH:       # %bb.0:
344; ZVFH-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
345; ZVFH-NEXT:    vfmin.vv v8, v8, v9
346; ZVFH-NEXT:    ret
347;
348; ZVFHMIN-LABEL: vfmin_vv_nxv1f16_unmasked:
349; ZVFHMIN:       # %bb.0:
350; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
351; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9
352; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8
353; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
354; ZVFHMIN-NEXT:    vfmin.vv v9, v9, v10
355; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
356; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
357; ZVFHMIN-NEXT:    ret
358  %v = call <vscale x 1 x half> @llvm.vp.minnum.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)
359  ret <vscale x 1 x half> %v
360}
361
362declare <vscale x 2 x half> @llvm.vp.minnum.nxv2f16(<vscale x 2 x half>, <vscale x 2 x half>, <vscale x 2 x i1>, i32)
363
364define <vscale x 2 x half> @vfmin_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {
365; ZVFH-LABEL: vfmin_vv_nxv2f16:
366; ZVFH:       # %bb.0:
367; ZVFH-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
368; ZVFH-NEXT:    vfmin.vv v8, v8, v9, v0.t
369; ZVFH-NEXT:    ret
370;
371; ZVFHMIN-LABEL: vfmin_vv_nxv2f16:
372; ZVFHMIN:       # %bb.0:
373; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
374; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9, v0.t
375; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8, v0.t
376; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
377; ZVFHMIN-NEXT:    vfmin.vv v9, v9, v10, v0.t
378; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
379; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9, v0.t
380; ZVFHMIN-NEXT:    ret
381  %v = call <vscale x 2 x half> @llvm.vp.minnum.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> %m, i32 %evl)
382  ret <vscale x 2 x half> %v
383}
384
385define <vscale x 2 x half> @vfmin_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 zeroext %evl) {
386; ZVFH-LABEL: vfmin_vv_nxv2f16_unmasked:
387; ZVFH:       # %bb.0:
388; ZVFH-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
389; ZVFH-NEXT:    vfmin.vv v8, v8, v9
390; ZVFH-NEXT:    ret
391;
392; ZVFHMIN-LABEL: vfmin_vv_nxv2f16_unmasked:
393; ZVFHMIN:       # %bb.0:
394; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
395; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9
396; ZVFHMIN-NEXT:    vfwcvt.f.f.v v9, v8
397; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
398; ZVFHMIN-NEXT:    vfmin.vv v9, v9, v10
399; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
400; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v9
401; ZVFHMIN-NEXT:    ret
402  %v = call <vscale x 2 x half> @llvm.vp.minnum.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)
403  ret <vscale x 2 x half> %v
404}
405
406declare <vscale x 4 x half> @llvm.vp.minnum.nxv4f16(<vscale x 4 x half>, <vscale x 4 x half>, <vscale x 4 x i1>, i32)
407
408define <vscale x 4 x half> @vfmin_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
409; ZVFH-LABEL: vfmin_vv_nxv4f16:
410; ZVFH:       # %bb.0:
411; ZVFH-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
412; ZVFH-NEXT:    vfmin.vv v8, v8, v9, v0.t
413; ZVFH-NEXT:    ret
414;
415; ZVFHMIN-LABEL: vfmin_vv_nxv4f16:
416; ZVFHMIN:       # %bb.0:
417; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
418; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9, v0.t
419; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v8, v0.t
420; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
421; ZVFHMIN-NEXT:    vfmin.vv v10, v12, v10, v0.t
422; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
423; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v10, v0.t
424; ZVFHMIN-NEXT:    ret
425  %v = call <vscale x 4 x half> @llvm.vp.minnum.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> %m, i32 %evl)
426  ret <vscale x 4 x half> %v
427}
428
429define <vscale x 4 x half> @vfmin_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, i32 zeroext %evl) {
430; ZVFH-LABEL: vfmin_vv_nxv4f16_unmasked:
431; ZVFH:       # %bb.0:
432; ZVFH-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
433; ZVFH-NEXT:    vfmin.vv v8, v8, v9
434; ZVFH-NEXT:    ret
435;
436; ZVFHMIN-LABEL: vfmin_vv_nxv4f16_unmasked:
437; ZVFHMIN:       # %bb.0:
438; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
439; ZVFHMIN-NEXT:    vfwcvt.f.f.v v10, v9
440; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v8
441; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
442; ZVFHMIN-NEXT:    vfmin.vv v10, v12, v10
443; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
444; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v10
445; ZVFHMIN-NEXT:    ret
446  %v = call <vscale x 4 x half> @llvm.vp.minnum.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)
447  ret <vscale x 4 x half> %v
448}
449
450declare <vscale x 8 x half> @llvm.vp.minnum.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, i32)
451
452define <vscale x 8 x half> @vfmin_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
453; ZVFH-LABEL: vfmin_vv_nxv8f16:
454; ZVFH:       # %bb.0:
455; ZVFH-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
456; ZVFH-NEXT:    vfmin.vv v8, v8, v10, v0.t
457; ZVFH-NEXT:    ret
458;
459; ZVFHMIN-LABEL: vfmin_vv_nxv8f16:
460; ZVFHMIN:       # %bb.0:
461; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
462; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v10, v0.t
463; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v8, v0.t
464; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
465; ZVFHMIN-NEXT:    vfmin.vv v12, v16, v12, v0.t
466; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
467; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v12, v0.t
468; ZVFHMIN-NEXT:    ret
469  %v = call <vscale x 8 x half> @llvm.vp.minnum.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 %evl)
470  ret <vscale x 8 x half> %v
471}
472
473define <vscale x 8 x half> @vfmin_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, i32 zeroext %evl) {
474; ZVFH-LABEL: vfmin_vv_nxv8f16_unmasked:
475; ZVFH:       # %bb.0:
476; ZVFH-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
477; ZVFH-NEXT:    vfmin.vv v8, v8, v10
478; ZVFH-NEXT:    ret
479;
480; ZVFHMIN-LABEL: vfmin_vv_nxv8f16_unmasked:
481; ZVFHMIN:       # %bb.0:
482; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
483; ZVFHMIN-NEXT:    vfwcvt.f.f.v v12, v10
484; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v8
485; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
486; ZVFHMIN-NEXT:    vfmin.vv v12, v16, v12
487; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
488; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v12
489; ZVFHMIN-NEXT:    ret
490  %v = call <vscale x 8 x half> @llvm.vp.minnum.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)
491  ret <vscale x 8 x half> %v
492}
493
494declare <vscale x 16 x half> @llvm.vp.minnum.nxv16f16(<vscale x 16 x half>, <vscale x 16 x half>, <vscale x 16 x i1>, i32)
495
496define <vscale x 16 x half> @vfmin_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {
497; ZVFH-LABEL: vfmin_vv_nxv16f16:
498; ZVFH:       # %bb.0:
499; ZVFH-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
500; ZVFH-NEXT:    vfmin.vv v8, v8, v12, v0.t
501; ZVFH-NEXT:    ret
502;
503; ZVFHMIN-LABEL: vfmin_vv_nxv16f16:
504; ZVFHMIN:       # %bb.0:
505; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
506; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v12, v0.t
507; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v8, v0.t
508; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
509; ZVFHMIN-NEXT:    vfmin.vv v16, v24, v16, v0.t
510; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
511; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v16, v0.t
512; ZVFHMIN-NEXT:    ret
513  %v = call <vscale x 16 x half> @llvm.vp.minnum.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> %m, i32 %evl)
514  ret <vscale x 16 x half> %v
515}
516
517define <vscale x 16 x half> @vfmin_vv_nxv16f16_unmasked(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, i32 zeroext %evl) {
518; ZVFH-LABEL: vfmin_vv_nxv16f16_unmasked:
519; ZVFH:       # %bb.0:
520; ZVFH-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
521; ZVFH-NEXT:    vfmin.vv v8, v8, v12
522; ZVFH-NEXT:    ret
523;
524; ZVFHMIN-LABEL: vfmin_vv_nxv16f16_unmasked:
525; ZVFHMIN:       # %bb.0:
526; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
527; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v12
528; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v8
529; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
530; ZVFHMIN-NEXT:    vfmin.vv v16, v24, v16
531; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
532; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v16
533; ZVFHMIN-NEXT:    ret
534  %v = call <vscale x 16 x half> @llvm.vp.minnum.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)
535  ret <vscale x 16 x half> %v
536}
537
538declare <vscale x 32 x half> @llvm.vp.minnum.nxv32f16(<vscale x 32 x half>, <vscale x 32 x half>, <vscale x 32 x i1>, i32)
539
540define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {
541; ZVFH-LABEL: vfmin_vv_nxv32f16:
542; ZVFH:       # %bb.0:
543; ZVFH-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
544; ZVFH-NEXT:    vfmin.vv v8, v8, v16, v0.t
545; ZVFH-NEXT:    ret
546;
547; ZVFHMIN-LABEL: vfmin_vv_nxv32f16:
548; ZVFHMIN:       # %bb.0:
549; ZVFHMIN-NEXT:    addi sp, sp, -16
550; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 16
551; ZVFHMIN-NEXT:    csrr a1, vlenb
552; ZVFHMIN-NEXT:    slli a1, a1, 3
553; ZVFHMIN-NEXT:    mv a2, a1
554; ZVFHMIN-NEXT:    slli a1, a1, 1
555; ZVFHMIN-NEXT:    add a1, a1, a2
556; ZVFHMIN-NEXT:    sub sp, sp, a1
557; ZVFHMIN-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
558; ZVFHMIN-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
559; ZVFHMIN-NEXT:    vmv1r.v v7, v0
560; ZVFHMIN-NEXT:    csrr a1, vlenb
561; ZVFHMIN-NEXT:    slli a1, a1, 4
562; ZVFHMIN-NEXT:    add a1, sp, a1
563; ZVFHMIN-NEXT:    addi a1, a1, 16
564; ZVFHMIN-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
565; ZVFHMIN-NEXT:    csrr a2, vlenb
566; ZVFHMIN-NEXT:    slli a1, a2, 1
567; ZVFHMIN-NEXT:    srli a2, a2, 2
568; ZVFHMIN-NEXT:    sub a3, a0, a1
569; ZVFHMIN-NEXT:    vslidedown.vx v0, v0, a2
570; ZVFHMIN-NEXT:    sltu a2, a0, a3
571; ZVFHMIN-NEXT:    addi a2, a2, -1
572; ZVFHMIN-NEXT:    and a2, a2, a3
573; ZVFHMIN-NEXT:    vmv4r.v v8, v16
574; ZVFHMIN-NEXT:    csrr a3, vlenb
575; ZVFHMIN-NEXT:    slli a3, a3, 3
576; ZVFHMIN-NEXT:    add a3, sp, a3
577; ZVFHMIN-NEXT:    addi a3, a3, 16
578; ZVFHMIN-NEXT:    vs8r.v v8, (a3) # Unknown-size Folded Spill
579; ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
580; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v20, v0.t
581; ZVFHMIN-NEXT:    addi a2, sp, 16
582; ZVFHMIN-NEXT:    vs8r.v v8, (a2) # Unknown-size Folded Spill
583; ZVFHMIN-NEXT:    csrr a2, vlenb
584; ZVFHMIN-NEXT:    slli a2, a2, 4
585; ZVFHMIN-NEXT:    add a2, sp, a2
586; ZVFHMIN-NEXT:    addi a2, a2, 16
587; ZVFHMIN-NEXT:    vl8r.v v16, (a2) # Unknown-size Folded Reload
588; ZVFHMIN-NEXT:    vfwcvt.f.f.v v8, v20, v0.t
589; ZVFHMIN-NEXT:    addi a2, sp, 16
590; ZVFHMIN-NEXT:    vl8r.v v16, (a2) # Unknown-size Folded Reload
591; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
592; ZVFHMIN-NEXT:    vfmin.vv v16, v8, v16, v0.t
593; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
594; ZVFHMIN-NEXT:    vfncvt.f.f.w v12, v16, v0.t
595; ZVFHMIN-NEXT:    bltu a0, a1, .LBB22_2
596; ZVFHMIN-NEXT:  # %bb.1:
597; ZVFHMIN-NEXT:    mv a0, a1
598; ZVFHMIN-NEXT:  .LBB22_2:
599; ZVFHMIN-NEXT:    vmv1r.v v0, v7
600; ZVFHMIN-NEXT:    csrr a1, vlenb
601; ZVFHMIN-NEXT:    slli a1, a1, 3
602; ZVFHMIN-NEXT:    add a1, sp, a1
603; ZVFHMIN-NEXT:    addi a1, a1, 16
604; ZVFHMIN-NEXT:    vl8r.v v16, (a1) # Unknown-size Folded Reload
605; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
606; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v16, v0.t
607; ZVFHMIN-NEXT:    addi a0, sp, 16
608; ZVFHMIN-NEXT:    vs8r.v v24, (a0) # Unknown-size Folded Spill
609; ZVFHMIN-NEXT:    csrr a0, vlenb
610; ZVFHMIN-NEXT:    slli a0, a0, 4
611; ZVFHMIN-NEXT:    add a0, sp, a0
612; ZVFHMIN-NEXT:    addi a0, a0, 16
613; ZVFHMIN-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
614; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v16, v0.t
615; ZVFHMIN-NEXT:    addi a0, sp, 16
616; ZVFHMIN-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
617; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
618; ZVFHMIN-NEXT:    vfmin.vv v16, v24, v16, v0.t
619; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
620; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v16, v0.t
621; ZVFHMIN-NEXT:    csrr a0, vlenb
622; ZVFHMIN-NEXT:    slli a0, a0, 3
623; ZVFHMIN-NEXT:    mv a1, a0
624; ZVFHMIN-NEXT:    slli a0, a0, 1
625; ZVFHMIN-NEXT:    add a0, a0, a1
626; ZVFHMIN-NEXT:    add sp, sp, a0
627; ZVFHMIN-NEXT:    .cfi_def_cfa sp, 16
628; ZVFHMIN-NEXT:    addi sp, sp, 16
629; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
630; ZVFHMIN-NEXT:    ret
631  %v = call <vscale x 32 x half> @llvm.vp.minnum.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> %m, i32 %evl)
632  ret <vscale x 32 x half> %v
633}
634
635define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, i32 zeroext %evl) {
636; ZVFH-LABEL: vfmin_vv_nxv32f16_unmasked:
637; ZVFH:       # %bb.0:
638; ZVFH-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
639; ZVFH-NEXT:    vfmin.vv v8, v8, v16
640; ZVFH-NEXT:    ret
641;
642; ZVFHMIN-LABEL: vfmin_vv_nxv32f16_unmasked:
643; ZVFHMIN:       # %bb.0:
644; ZVFHMIN-NEXT:    addi sp, sp, -16
645; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 16
646; ZVFHMIN-NEXT:    csrr a1, vlenb
647; ZVFHMIN-NEXT:    slli a1, a1, 3
648; ZVFHMIN-NEXT:    sub sp, sp, a1
649; ZVFHMIN-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
650; ZVFHMIN-NEXT:    csrr a2, vlenb
651; ZVFHMIN-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
652; ZVFHMIN-NEXT:    vmset.m v24
653; ZVFHMIN-NEXT:    slli a1, a2, 1
654; ZVFHMIN-NEXT:    srli a2, a2, 2
655; ZVFHMIN-NEXT:    sub a3, a0, a1
656; ZVFHMIN-NEXT:    vsetvli a4, zero, e8, mf2, ta, ma
657; ZVFHMIN-NEXT:    vslidedown.vx v0, v24, a2
658; ZVFHMIN-NEXT:    sltu a2, a0, a3
659; ZVFHMIN-NEXT:    addi a2, a2, -1
660; ZVFHMIN-NEXT:    and a2, a2, a3
661; ZVFHMIN-NEXT:    addi a3, sp, 16
662; ZVFHMIN-NEXT:    vs8r.v v16, (a3) # Unknown-size Folded Spill
663; ZVFHMIN-NEXT:    vsetvli zero, a2, e16, m4, ta, ma
664; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v20, v0.t
665; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v12, v0.t
666; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
667; ZVFHMIN-NEXT:    vfmin.vv v16, v16, v24, v0.t
668; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
669; ZVFHMIN-NEXT:    vfncvt.f.f.w v12, v16, v0.t
670; ZVFHMIN-NEXT:    bltu a0, a1, .LBB23_2
671; ZVFHMIN-NEXT:  # %bb.1:
672; ZVFHMIN-NEXT:    mv a0, a1
673; ZVFHMIN-NEXT:  .LBB23_2:
674; ZVFHMIN-NEXT:    addi a1, sp, 16
675; ZVFHMIN-NEXT:    vl8r.v v24, (a1) # Unknown-size Folded Reload
676; ZVFHMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
677; ZVFHMIN-NEXT:    vfwcvt.f.f.v v16, v24
678; ZVFHMIN-NEXT:    vfwcvt.f.f.v v24, v8
679; ZVFHMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
680; ZVFHMIN-NEXT:    vfmin.vv v16, v24, v16
681; ZVFHMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
682; ZVFHMIN-NEXT:    vfncvt.f.f.w v8, v16
683; ZVFHMIN-NEXT:    csrr a0, vlenb
684; ZVFHMIN-NEXT:    slli a0, a0, 3
685; ZVFHMIN-NEXT:    add sp, sp, a0
686; ZVFHMIN-NEXT:    .cfi_def_cfa sp, 16
687; ZVFHMIN-NEXT:    addi sp, sp, 16
688; ZVFHMIN-NEXT:    .cfi_def_cfa_offset 0
689; ZVFHMIN-NEXT:    ret
690  %v = call <vscale x 32 x half> @llvm.vp.minnum.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)
691  ret <vscale x 32 x half> %v
692}
693
694declare <vscale x 1 x float> @llvm.vp.minnum.nxv1f32(<vscale x 1 x float>, <vscale x 1 x float>, <vscale x 1 x i1>, i32)
695
696define <vscale x 1 x float> @vfmin_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
697; CHECK-LABEL: vfmin_vv_nxv1f32:
698; CHECK:       # %bb.0:
699; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
700; CHECK-NEXT:    vfmin.vv v8, v8, v9, v0.t
701; CHECK-NEXT:    ret
702  %v = call <vscale x 1 x float> @llvm.vp.minnum.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x i1> %m, i32 %evl)
703  ret <vscale x 1 x float> %v
704}
705
706define <vscale x 1 x float> @vfmin_vv_nxv1f32_unmasked(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, i32 zeroext %evl) {
707; CHECK-LABEL: vfmin_vv_nxv1f32_unmasked:
708; CHECK:       # %bb.0:
709; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
710; CHECK-NEXT:    vfmin.vv v8, v8, v9
711; CHECK-NEXT:    ret
712  %v = call <vscale x 1 x float> @llvm.vp.minnum.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)
713  ret <vscale x 1 x float> %v
714}
715
716declare <vscale x 2 x float> @llvm.vp.minnum.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>, <vscale x 2 x i1>, i32)
717
718define <vscale x 2 x float> @vfmin_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {
719; CHECK-LABEL: vfmin_vv_nxv2f32:
720; CHECK:       # %bb.0:
721; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
722; CHECK-NEXT:    vfmin.vv v8, v8, v9, v0.t
723; CHECK-NEXT:    ret
724  %v = call <vscale x 2 x float> @llvm.vp.minnum.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> %m, i32 %evl)
725  ret <vscale x 2 x float> %v
726}
727
728define <vscale x 2 x float> @vfmin_vv_nxv2f32_unmasked(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 zeroext %evl) {
729; CHECK-LABEL: vfmin_vv_nxv2f32_unmasked:
730; CHECK:       # %bb.0:
731; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
732; CHECK-NEXT:    vfmin.vv v8, v8, v9
733; CHECK-NEXT:    ret
734  %v = call <vscale x 2 x float> @llvm.vp.minnum.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)
735  ret <vscale x 2 x float> %v
736}
737
738declare <vscale x 4 x float> @llvm.vp.minnum.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, i32)
739
740define <vscale x 4 x float> @vfmin_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
741; CHECK-LABEL: vfmin_vv_nxv4f32:
742; CHECK:       # %bb.0:
743; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
744; CHECK-NEXT:    vfmin.vv v8, v8, v10, v0.t
745; CHECK-NEXT:    ret
746  %v = call <vscale x 4 x float> @llvm.vp.minnum.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x i1> %m, i32 %evl)
747  ret <vscale x 4 x float> %v
748}
749
750define <vscale x 4 x float> @vfmin_vv_nxv4f32_unmasked(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, i32 zeroext %evl) {
751; CHECK-LABEL: vfmin_vv_nxv4f32_unmasked:
752; CHECK:       # %bb.0:
753; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
754; CHECK-NEXT:    vfmin.vv v8, v8, v10
755; CHECK-NEXT:    ret
756  %v = call <vscale x 4 x float> @llvm.vp.minnum.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)
757  ret <vscale x 4 x float> %v
758}
759
760declare <vscale x 8 x float> @llvm.vp.minnum.nxv8f32(<vscale x 8 x float>, <vscale x 8 x float>, <vscale x 8 x i1>, i32)
761
762define <vscale x 8 x float> @vfmin_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
763; CHECK-LABEL: vfmin_vv_nxv8f32:
764; CHECK:       # %bb.0:
765; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
766; CHECK-NEXT:    vfmin.vv v8, v8, v12, v0.t
767; CHECK-NEXT:    ret
768  %v = call <vscale x 8 x float> @llvm.vp.minnum.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %m, i32 %evl)
769  ret <vscale x 8 x float> %v
770}
771
772define <vscale x 8 x float> @vfmin_vv_nxv8f32_unmasked(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, i32 zeroext %evl) {
773; CHECK-LABEL: vfmin_vv_nxv8f32_unmasked:
774; CHECK:       # %bb.0:
775; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
776; CHECK-NEXT:    vfmin.vv v8, v8, v12
777; CHECK-NEXT:    ret
778  %v = call <vscale x 8 x float> @llvm.vp.minnum.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)
779  ret <vscale x 8 x float> %v
780}
781
782declare <vscale x 16 x float> @llvm.vp.minnum.nxv16f32(<vscale x 16 x float>, <vscale x 16 x float>, <vscale x 16 x i1>, i32)
783
784define <vscale x 16 x float> @vfmin_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {
785; CHECK-LABEL: vfmin_vv_nxv16f32:
786; CHECK:       # %bb.0:
787; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
788; CHECK-NEXT:    vfmin.vv v8, v8, v16, v0.t
789; CHECK-NEXT:    ret
790  %v = call <vscale x 16 x float> @llvm.vp.minnum.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x i1> %m, i32 %evl)
791  ret <vscale x 16 x float> %v
792}
793
794define <vscale x 16 x float> @vfmin_vv_nxv16f32_unmasked(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, i32 zeroext %evl) {
795; CHECK-LABEL: vfmin_vv_nxv16f32_unmasked:
796; CHECK:       # %bb.0:
797; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
798; CHECK-NEXT:    vfmin.vv v8, v8, v16
799; CHECK-NEXT:    ret
800  %v = call <vscale x 16 x float> @llvm.vp.minnum.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)
801  ret <vscale x 16 x float> %v
802}
803
804declare <vscale x 1 x double> @llvm.vp.minnum.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, <vscale x 1 x i1>, i32)
805
806define <vscale x 1 x double> @vfmin_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
807; CHECK-LABEL: vfmin_vv_nxv1f64:
808; CHECK:       # %bb.0:
809; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
810; CHECK-NEXT:    vfmin.vv v8, v8, v9, v0.t
811; CHECK-NEXT:    ret
812  %v = call <vscale x 1 x double> @llvm.vp.minnum.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 %evl)
813  ret <vscale x 1 x double> %v
814}
815
816define <vscale x 1 x double> @vfmin_vv_nxv1f64_unmasked(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 zeroext %evl) {
817; CHECK-LABEL: vfmin_vv_nxv1f64_unmasked:
818; CHECK:       # %bb.0:
819; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
820; CHECK-NEXT:    vfmin.vv v8, v8, v9
821; CHECK-NEXT:    ret
822  %v = call <vscale x 1 x double> @llvm.vp.minnum.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)
823  ret <vscale x 1 x double> %v
824}
825
826declare <vscale x 2 x double> @llvm.vp.minnum.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, i32)
827
828define <vscale x 2 x double> @vfmin_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {
829; CHECK-LABEL: vfmin_vv_nxv2f64:
830; CHECK:       # %bb.0:
831; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
832; CHECK-NEXT:    vfmin.vv v8, v8, v10, v0.t
833; CHECK-NEXT:    ret
834  %v = call <vscale x 2 x double> @llvm.vp.minnum.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x i1> %m, i32 %evl)
835  ret <vscale x 2 x double> %v
836}
837
838define <vscale x 2 x double> @vfmin_vv_nxv2f64_unmasked(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, i32 zeroext %evl) {
839; CHECK-LABEL: vfmin_vv_nxv2f64_unmasked:
840; CHECK:       # %bb.0:
841; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
842; CHECK-NEXT:    vfmin.vv v8, v8, v10
843; CHECK-NEXT:    ret
844  %v = call <vscale x 2 x double> @llvm.vp.minnum.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)
845  ret <vscale x 2 x double> %v
846}
847
848declare <vscale x 4 x double> @llvm.vp.minnum.nxv4f64(<vscale x 4 x double>, <vscale x 4 x double>, <vscale x 4 x i1>, i32)
849
850define <vscale x 4 x double> @vfmin_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
851; CHECK-LABEL: vfmin_vv_nxv4f64:
852; CHECK:       # %bb.0:
853; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
854; CHECK-NEXT:    vfmin.vv v8, v8, v12, v0.t
855; CHECK-NEXT:    ret
856  %v = call <vscale x 4 x double> @llvm.vp.minnum.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x i1> %m, i32 %evl)
857  ret <vscale x 4 x double> %v
858}
859
860define <vscale x 4 x double> @vfmin_vv_nxv4f64_unmasked(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, i32 zeroext %evl) {
861; CHECK-LABEL: vfmin_vv_nxv4f64_unmasked:
862; CHECK:       # %bb.0:
863; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
864; CHECK-NEXT:    vfmin.vv v8, v8, v12
865; CHECK-NEXT:    ret
866  %v = call <vscale x 4 x double> @llvm.vp.minnum.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)
867  ret <vscale x 4 x double> %v
868}
869
870declare <vscale x 8 x double> @llvm.vp.minnum.nxv8f64(<vscale x 8 x double>, <vscale x 8 x double>, <vscale x 8 x i1>, i32)
871
872define <vscale x 8 x double> @vfmin_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
873; CHECK-LABEL: vfmin_vv_nxv8f64:
874; CHECK:       # %bb.0:
875; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
876; CHECK-NEXT:    vfmin.vv v8, v8, v16, v0.t
877; CHECK-NEXT:    ret
878  %v = call <vscale x 8 x double> @llvm.vp.minnum.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 %evl)
879  ret <vscale x 8 x double> %v
880}
881
882define <vscale x 8 x double> @vfmin_vv_nxv8f64_unmasked(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, i32 zeroext %evl) {
883; CHECK-LABEL: vfmin_vv_nxv8f64_unmasked:
884; CHECK:       # %bb.0:
885; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
886; CHECK-NEXT:    vfmin.vv v8, v8, v16
887; CHECK-NEXT:    ret
888  %v = call <vscale x 8 x double> @llvm.vp.minnum.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)
889  ret <vscale x 8 x double> %v
890}
891