xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll (revision bc74a1edbe5e6a3603e65efe06116fa72747acab) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin,+m | FileCheck --check-prefixes=CHECK,RV32 %s
3; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin,+m | FileCheck --check-prefixes=CHECK,RV64 %s
4; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin,+m | FileCheck --check-prefixes=CHECK,RV32 %s
5; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin,+m | FileCheck --check-prefixes=CHECK,RV64 %s
6
7; Integers
8
9define {<vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_load_nxv16i1_nxv32i1(ptr %p) {
10; CHECK-LABEL: vector_deinterleave_load_nxv16i1_nxv32i1:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
13; CHECK-NEXT:    vlm.v v8, (a0)
14; CHECK-NEXT:    csrr a0, vlenb
15; CHECK-NEXT:    srli a0, a0, 2
16; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
17; CHECK-NEXT:    vslidedown.vx v0, v8, a0
18; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
19; CHECK-NEXT:    vmv.v.i v10, 0
20; CHECK-NEXT:    vmerge.vim v14, v10, 1, v0
21; CHECK-NEXT:    vmv1r.v v0, v8
22; CHECK-NEXT:    vmerge.vim v12, v10, 1, v0
23; CHECK-NEXT:    vnsrl.wi v8, v12, 0
24; CHECK-NEXT:    vnsrl.wi v10, v12, 8
25; CHECK-NEXT:    vmsne.vi v0, v8, 0
26; CHECK-NEXT:    vmsne.vi v8, v10, 0
27; CHECK-NEXT:    ret
28  %vec = load <vscale x 32 x i1>, ptr %p
29  %deinterleaved.results = call {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.vector.deinterleave2.nxv32i1(<vscale x 32 x i1> %vec)
30  %t0 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %deinterleaved.results, 0
31  %t1 = extractvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %deinterleaved.results, 1
32  %res0 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } undef, <vscale x 16 x i1> %t0, 0
33  %res1 = insertvalue { <vscale x 16 x i1>, <vscale x 16 x i1> } %res0, <vscale x 16 x i1> %t1, 1
34  ret {<vscale x 16 x i1>, <vscale x 16 x i1>} %res1
35}
36
37define {<vscale x 16 x i8>, <vscale x 16 x i8>} @vector_deinterleave_load_nxv16i8_nxv32i8(ptr %p) {
38; CHECK-LABEL: vector_deinterleave_load_nxv16i8_nxv32i8:
39; CHECK:       # %bb.0:
40; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
41; CHECK-NEXT:    vlseg2e8.v v8, (a0)
42; CHECK-NEXT:    ret
43  %vec = load <vscale x 32 x i8>, ptr %p
44  %deinterleaved.results = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> %vec)
45  %t0 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %deinterleaved.results, 0
46  %t1 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %deinterleaved.results, 1
47  %res0 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } undef, <vscale x 16 x i8> %t0, 0
48  %res1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %res0, <vscale x 16 x i8> %t1, 1
49  ret {<vscale x 16 x i8>, <vscale x 16 x i8>} %res1
50}
51
52; Shouldn't be lowered to vlseg because it's unaligned
53define {<vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_load_nxv8i16_nxv16i16_align1(ptr %p) {
54; CHECK-LABEL: vector_deinterleave_load_nxv8i16_nxv16i16_align1:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    vl4r.v v12, (a0)
57; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
58; CHECK-NEXT:    vnsrl.wi v8, v12, 0
59; CHECK-NEXT:    vnsrl.wi v10, v12, 16
60; CHECK-NEXT:    ret
61  %vec = load <vscale x 16 x i16>, ptr %p, align 1
62  %deinterleaved.results = call {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> %vec)
63  %t0 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %deinterleaved.results, 0
64  %t1 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %deinterleaved.results, 1
65  %res0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } undef, <vscale x 8 x i16> %t0, 0
66  %res1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %res0, <vscale x 8 x i16> %t1, 1
67  ret {<vscale x 8 x i16>, <vscale x 8 x i16>} %res1
68}
69
70define {<vscale x 8 x i16>, <vscale x 8 x i16>} @vector_deinterleave_load_nxv8i16_nxv16i16(ptr %p) {
71; CHECK-LABEL: vector_deinterleave_load_nxv8i16_nxv16i16:
72; CHECK:       # %bb.0:
73; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
74; CHECK-NEXT:    vlseg2e16.v v8, (a0)
75; CHECK-NEXT:    ret
76  %vec = load <vscale x 16 x i16>, ptr %p
77  %deinterleaved.results = call {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16> %vec)
78  %t0 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %deinterleaved.results, 0
79  %t1 = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %deinterleaved.results, 1
80  %res0 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } undef, <vscale x 8 x i16> %t0, 0
81  %res1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16> } %res0, <vscale x 8 x i16> %t1, 1
82  ret {<vscale x 8 x i16>, <vscale x 8 x i16>} %res1
83}
84
85define {<vscale x 4 x i32>, <vscale x 4 x i32>} @vector_deinterleave_load_nxv4i32_nxvv8i32(ptr %p) {
86; CHECK-LABEL: vector_deinterleave_load_nxv4i32_nxvv8i32:
87; CHECK:       # %bb.0:
88; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
89; CHECK-NEXT:    vlseg2e32.v v8, (a0)
90; CHECK-NEXT:    ret
91  %vec = load <vscale x 8 x i32>, ptr %p
92  %deinterleaved.results = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %vec)
93  %t0 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %deinterleaved.results, 0
94  %t1 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %deinterleaved.results, 1
95  %res0 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } undef, <vscale x 4 x i32> %t0, 0
96  %res1 = insertvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %res0, <vscale x 4 x i32> %t1, 1
97  ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %res1
98}
99
100define {<vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_load_nxv2i64_nxv4i64(ptr %p) {
101; CHECK-LABEL: vector_deinterleave_load_nxv2i64_nxv4i64:
102; CHECK:       # %bb.0:
103; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
104; CHECK-NEXT:    vlseg2e64.v v8, (a0)
105; CHECK-NEXT:    ret
106  %vec = load <vscale x 4 x i64>, ptr %p
107  %deinterleaved.results = call {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.vector.deinterleave2.nxv4i64(<vscale x 4 x i64> %vec)
108  %t0 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %deinterleaved.results, 0
109  %t1 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %deinterleaved.results, 1
110  %res0 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } undef, <vscale x 2 x i64> %t0, 0
111  %res1 = insertvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %res0, <vscale x 2 x i64> %t1, 1
112  ret {<vscale x 2 x i64>, <vscale x 2 x i64>} %res1
113}
114
115define {<vscale x 4 x i64>, <vscale x 4 x i64>} @vector_deinterleave_load_nxv4i64_nxv8i64(ptr %p) {
116; CHECK-LABEL: vector_deinterleave_load_nxv4i64_nxv8i64:
117; CHECK:       # %bb.0:
118; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
119; CHECK-NEXT:    vlseg2e64.v v8, (a0)
120; CHECK-NEXT:    ret
121  %vec = load <vscale x 8 x i64>, ptr %p
122  %deinterleaved.results = call {<vscale x 4 x i64>, <vscale x 4 x i64>} @llvm.vector.deinterleave2.nxv8i64(<vscale x 8 x i64> %vec)
123  %t0 = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } %deinterleaved.results, 0
124  %t1 = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } %deinterleaved.results, 1
125  %res0 = insertvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } undef, <vscale x 4 x i64> %t0, 0
126  %res1 = insertvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } %res0, <vscale x 4 x i64> %t1, 1
127  ret {<vscale x 4 x i64>, <vscale x 4 x i64>} %res1
128}
129
130; This shouldn't be lowered to a vlseg because EMUL * NFIELDS >= 8
131define {<vscale x 8 x i64>, <vscale x 8 x i64>} @vector_deinterleave_load_nxv8i64_nxv16i64(ptr %p) {
132; CHECK-LABEL: vector_deinterleave_load_nxv8i64_nxv16i64:
133; CHECK:       # %bb.0:
134; CHECK-NEXT:    addi sp, sp, -16
135; CHECK-NEXT:    .cfi_def_cfa_offset 16
136; CHECK-NEXT:    csrr a1, vlenb
137; CHECK-NEXT:    slli a1, a1, 4
138; CHECK-NEXT:    sub sp, sp, a1
139; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
140; CHECK-NEXT:    li a1, 85
141; CHECK-NEXT:    vsetvli a2, zero, e8, mf8, ta, ma
142; CHECK-NEXT:    vmv.v.x v16, a1
143; CHECK-NEXT:    csrr a1, vlenb
144; CHECK-NEXT:    vl8re64.v v24, (a0)
145; CHECK-NEXT:    slli a1, a1, 3
146; CHECK-NEXT:    add a0, a0, a1
147; CHECK-NEXT:    li a1, 170
148; CHECK-NEXT:    vl8re64.v v0, (a0)
149; CHECK-NEXT:    vmv.v.x v17, a1
150; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
151; CHECK-NEXT:    vcompress.vm v8, v24, v16
152; CHECK-NEXT:    vmv1r.v v12, v16
153; CHECK-NEXT:    vmv1r.v v13, v17
154; CHECK-NEXT:    vcompress.vm v16, v24, v13
155; CHECK-NEXT:    vcompress.vm v24, v0, v12
156; CHECK-NEXT:    addi a0, sp, 16
157; CHECK-NEXT:    vs8r.v v24, (a0) # Unknown-size Folded Spill
158; CHECK-NEXT:    vcompress.vm v24, v0, v13
159; CHECK-NEXT:    csrr a0, vlenb
160; CHECK-NEXT:    slli a0, a0, 3
161; CHECK-NEXT:    add a0, sp, a0
162; CHECK-NEXT:    addi a0, a0, 16
163; CHECK-NEXT:    vs8r.v v24, (a0) # Unknown-size Folded Spill
164; CHECK-NEXT:    addi a0, sp, 16
165; CHECK-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
166; CHECK-NEXT:    vmv4r.v v12, v24
167; CHECK-NEXT:    csrr a0, vlenb
168; CHECK-NEXT:    slli a0, a0, 3
169; CHECK-NEXT:    add a0, sp, a0
170; CHECK-NEXT:    addi a0, a0, 16
171; CHECK-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
172; CHECK-NEXT:    vmv4r.v v20, v24
173; CHECK-NEXT:    csrr a0, vlenb
174; CHECK-NEXT:    slli a0, a0, 4
175; CHECK-NEXT:    add sp, sp, a0
176; CHECK-NEXT:    .cfi_def_cfa sp, 16
177; CHECK-NEXT:    addi sp, sp, 16
178; CHECK-NEXT:    .cfi_def_cfa_offset 0
179; CHECK-NEXT:    ret
180  %vec = load <vscale x 16 x i64>, ptr %p
181  %deinterleaved.results = call {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.vector.deinterleave2.nxv16i64(<vscale x 16 x i64> %vec)
182  %t0 = extractvalue { <vscale x 8 x i64>, <vscale x 8 x i64> } %deinterleaved.results, 0
183  %t1 = extractvalue { <vscale x 8 x i64>, <vscale x 8 x i64> } %deinterleaved.results, 1
184  %res0 = insertvalue { <vscale x 8 x i64>, <vscale x 8 x i64> } undef, <vscale x 8 x i64> %t0, 0
185  %res1 = insertvalue { <vscale x 8 x i64>, <vscale x 8 x i64> } %res0, <vscale x 8 x i64> %t1, 1
186  ret {<vscale x 8 x i64>, <vscale x 8 x i64>} %res1
187}
188
189; Floats
190
191define {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @vector_deinterleave_load_nxv2bf16_nxv4bf16(ptr %p) {
192; CHECK-LABEL: vector_deinterleave_load_nxv2bf16_nxv4bf16:
193; CHECK:       # %bb.0:
194; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
195; CHECK-NEXT:    vlseg2e16.v v8, (a0)
196; CHECK-NEXT:    ret
197  %vec = load <vscale x 4 x bfloat>, ptr %p
198  %deinterleaved.results = call {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} @llvm.vector.deinterleave2.nxv4bf16(<vscale x 4 x bfloat> %vec)
199  %t0 = extractvalue { <vscale x 2 x bfloat>, <vscale x 2 x bfloat> } %deinterleaved.results, 0
200  %t1 = extractvalue { <vscale x 2 x bfloat>, <vscale x 2 x bfloat> } %deinterleaved.results, 1
201  %res0 = insertvalue { <vscale x 2 x bfloat>, <vscale x 2 x bfloat> } undef, <vscale x 2 x bfloat> %t0, 0
202  %res1 = insertvalue { <vscale x 2 x bfloat>, <vscale x 2 x bfloat> } %res0, <vscale x 2 x bfloat> %t1, 1
203  ret {<vscale x 2 x bfloat>, <vscale x 2 x bfloat>} %res1
204}
205
206define {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @vector_deinterleave_load_nxv4bf16_nxv8bf16(ptr %p) {
207; CHECK-LABEL: vector_deinterleave_load_nxv4bf16_nxv8bf16:
208; CHECK:       # %bb.0:
209; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
210; CHECK-NEXT:    vlseg2e16.v v8, (a0)
211; CHECK-NEXT:    ret
212  %vec = load <vscale x 8 x bfloat>, ptr %p
213  %deinterleaved.results = call {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} @llvm.vector.deinterleave2.nxv8bf16(<vscale x 8 x bfloat> %vec)
214  %t0 = extractvalue { <vscale x 4 x bfloat>, <vscale x 4 x bfloat> } %deinterleaved.results, 0
215  %t1 = extractvalue { <vscale x 4 x bfloat>, <vscale x 4 x bfloat> } %deinterleaved.results, 1
216  %res0 = insertvalue { <vscale x 4 x bfloat>, <vscale x 4 x bfloat> } undef, <vscale x 4 x bfloat> %t0, 0
217  %res1 = insertvalue { <vscale x 4 x bfloat>, <vscale x 4 x bfloat> } %res0, <vscale x 4 x bfloat> %t1, 1
218  ret {<vscale x 4 x bfloat>, <vscale x 4 x bfloat>} %res1
219}
220
221define {<vscale x 2 x half>, <vscale x 2 x half>} @vector_deinterleave_load_nxv2f16_nxv4f16(ptr %p) {
222; CHECK-LABEL: vector_deinterleave_load_nxv2f16_nxv4f16:
223; CHECK:       # %bb.0:
224; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
225; CHECK-NEXT:    vlseg2e16.v v8, (a0)
226; CHECK-NEXT:    ret
227  %vec = load <vscale x 4 x half>, ptr %p
228  %deinterleaved.results = call {<vscale x 2 x half>, <vscale x 2 x half>} @llvm.vector.deinterleave2.nxv4f16(<vscale x 4 x half> %vec)
229  %t0 = extractvalue { <vscale x 2 x half>, <vscale x 2 x half> } %deinterleaved.results, 0
230  %t1 = extractvalue { <vscale x 2 x half>, <vscale x 2 x half> } %deinterleaved.results, 1
231  %res0 = insertvalue { <vscale x 2 x half>, <vscale x 2 x half> } undef, <vscale x 2 x half> %t0, 0
232  %res1 = insertvalue { <vscale x 2 x half>, <vscale x 2 x half> } %res0, <vscale x 2 x half> %t1, 1
233  ret {<vscale x 2 x half>, <vscale x 2 x half>} %res1
234}
235
236define {<vscale x 4 x half>, <vscale x 4 x half>} @vector_deinterleave_load_nxv4f16_nxv8f16(ptr %p) {
237; CHECK-LABEL: vector_deinterleave_load_nxv4f16_nxv8f16:
238; CHECK:       # %bb.0:
239; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
240; CHECK-NEXT:    vlseg2e16.v v8, (a0)
241; CHECK-NEXT:    ret
242  %vec = load <vscale x 8 x half>, ptr %p
243  %deinterleaved.results = call {<vscale x 4 x half>, <vscale x 4 x half>} @llvm.vector.deinterleave2.nxv8f16(<vscale x 8 x half> %vec)
244  %t0 = extractvalue { <vscale x 4 x half>, <vscale x 4 x half> } %deinterleaved.results, 0
245  %t1 = extractvalue { <vscale x 4 x half>, <vscale x 4 x half> } %deinterleaved.results, 1
246  %res0 = insertvalue { <vscale x 4 x half>, <vscale x 4 x half> } undef, <vscale x 4 x half> %t0, 0
247  %res1 = insertvalue { <vscale x 4 x half>, <vscale x 4 x half> } %res0, <vscale x 4 x half> %t1, 1
248  ret {<vscale x 4 x half>, <vscale x 4 x half>} %res1
249}
250
251define {<vscale x 2 x float>, <vscale x 2 x float>} @vector_deinterleave_load_nxv2f32_nxv4f32(ptr %p) {
252; CHECK-LABEL: vector_deinterleave_load_nxv2f32_nxv4f32:
253; CHECK:       # %bb.0:
254; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
255; CHECK-NEXT:    vlseg2e32.v v8, (a0)
256; CHECK-NEXT:    ret
257  %vec = load <vscale x 4 x float>, ptr %p
258  %deinterleaved.results = call {<vscale x 2 x float>, <vscale x 2 x float>} @llvm.vector.deinterleave2.nxv4f32(<vscale x 4 x float> %vec)
259  %t0 = extractvalue { <vscale x 2 x float>, <vscale x 2 x float> } %deinterleaved.results, 0
260  %t1 = extractvalue { <vscale x 2 x float>, <vscale x 2 x float> } %deinterleaved.results, 1
261  %res0 = insertvalue { <vscale x 2 x float>, <vscale x 2 x float> } undef, <vscale x 2 x float> %t0, 0
262  %res1 = insertvalue { <vscale x 2 x float>, <vscale x 2 x float> } %res0, <vscale x 2 x float> %t1, 1
263  ret {<vscale x 2 x float>, <vscale x 2 x float>} %res1
264}
265
266define {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @vector_deinterleave_load_nxv8bf16_nxv16bf16(ptr %p) {
267; CHECK-LABEL: vector_deinterleave_load_nxv8bf16_nxv16bf16:
268; CHECK:       # %bb.0:
269; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
270; CHECK-NEXT:    vlseg2e16.v v8, (a0)
271; CHECK-NEXT:    ret
272  %vec = load <vscale x 16 x bfloat>, ptr %p
273  %deinterleaved.results = call {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} @llvm.vector.deinterleave2.nxv16bf16(<vscale x 16 x bfloat> %vec)
274  %t0 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %deinterleaved.results, 0
275  %t1 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %deinterleaved.results, 1
276  %res0 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } undef, <vscale x 8 x bfloat> %t0, 0
277  %res1 = insertvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res0, <vscale x 8 x bfloat> %t1, 1
278  ret {<vscale x 8 x bfloat>, <vscale x 8 x bfloat>} %res1
279}
280
281define {<vscale x 8 x half>, <vscale x 8 x half>} @vector_deinterleave_load_nxv8f16_nxv16f16(ptr %p) {
282; CHECK-LABEL: vector_deinterleave_load_nxv8f16_nxv16f16:
283; CHECK:       # %bb.0:
284; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
285; CHECK-NEXT:    vlseg2e16.v v8, (a0)
286; CHECK-NEXT:    ret
287  %vec = load <vscale x 16 x half>, ptr %p
288  %deinterleaved.results = call {<vscale x 8 x half>, <vscale x 8 x half>} @llvm.vector.deinterleave2.nxv16f16(<vscale x 16 x half> %vec)
289  %t0 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %deinterleaved.results, 0
290  %t1 = extractvalue { <vscale x 8 x half>, <vscale x 8 x half> } %deinterleaved.results, 1
291  %res0 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } undef, <vscale x 8 x half> %t0, 0
292  %res1 = insertvalue { <vscale x 8 x half>, <vscale x 8 x half> } %res0, <vscale x 8 x half> %t1, 1
293  ret {<vscale x 8 x half>, <vscale x 8 x half>} %res1
294}
295
296define {<vscale x 4 x float>, <vscale x 4 x float>} @vector_deinterleave_load_nxv4f32_nxv8f32(ptr %p) {
297; CHECK-LABEL: vector_deinterleave_load_nxv4f32_nxv8f32:
298; CHECK:       # %bb.0:
299; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
300; CHECK-NEXT:    vlseg2e32.v v8, (a0)
301; CHECK-NEXT:    ret
302  %vec = load <vscale x 8 x float>, ptr %p
303  %deinterleaved.results = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.vector.deinterleave2.nxv8f32(<vscale x 8 x float> %vec)
304  %t0 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %deinterleaved.results, 0
305  %t1 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %deinterleaved.results, 1
306  %res0 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } undef, <vscale x 4 x float> %t0, 0
307  %res1 = insertvalue { <vscale x 4 x float>, <vscale x 4 x float> } %res0, <vscale x 4 x float> %t1, 1
308  ret {<vscale x 4 x float>, <vscale x 4 x float>} %res1
309}
310
311define {<vscale x 2 x double>, <vscale x 2 x double>} @vector_deinterleave_load_nxv2f64_nxv4f64(ptr %p) {
312; CHECK-LABEL: vector_deinterleave_load_nxv2f64_nxv4f64:
313; CHECK:       # %bb.0:
314; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
315; CHECK-NEXT:    vlseg2e64.v v8, (a0)
316; CHECK-NEXT:    ret
317  %vec = load <vscale x 4 x double>, ptr %p
318  %deinterleaved.results = call {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.vector.deinterleave2.nxv4f64(<vscale x 4 x double> %vec)
319  %t0 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %deinterleaved.results, 0
320  %t1 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %deinterleaved.results, 1
321  %res0 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } undef, <vscale x 2 x double> %t0, 0
322  %res1 = insertvalue { <vscale x 2 x double>, <vscale x 2 x double> } %res0, <vscale x 2 x double> %t1, 1
323  ret {<vscale x 2 x double>, <vscale x 2 x double>} %res1
324}
325
326define {<vscale x 2 x ptr>, <vscale x 2 x ptr>} @vector_deinterleave_load_nxv2p0_nxv4p0(ptr %p) {
327; RV32-LABEL: vector_deinterleave_load_nxv2p0_nxv4p0:
328; RV32:       # %bb.0:
329; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
330; RV32-NEXT:    vlseg2e32.v v8, (a0)
331; RV32-NEXT:    ret
332;
333; RV64-LABEL: vector_deinterleave_load_nxv2p0_nxv4p0:
334; RV64:       # %bb.0:
335; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
336; RV64-NEXT:    vlseg2e64.v v8, (a0)
337; RV64-NEXT:    ret
338  %vec = load <vscale x 4 x ptr>, ptr %p
339  %deinterleaved.results = call {<vscale x 2 x ptr>, <vscale x 2 x ptr>} @llvm.vector.deinterleave2.nxv4p0(<vscale x 4 x ptr> %vec)
340  %t0 = extractvalue { <vscale x 2 x ptr>, <vscale x 2 x ptr> } %deinterleaved.results, 0
341  %t1 = extractvalue { <vscale x 2 x ptr>, <vscale x 2 x ptr> } %deinterleaved.results, 1
342  %res0 = insertvalue { <vscale x 2 x ptr>, <vscale x 2 x ptr> } undef, <vscale x 2 x ptr> %t0, 0
343  %res1 = insertvalue { <vscale x 2 x ptr>, <vscale x 2 x ptr> } %res0, <vscale x 2 x ptr> %t1, 1
344  ret {<vscale x 2 x ptr>, <vscale x 2 x ptr>} %res1
345}
346
347define { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } @vector_deinterleave_load_factor4(ptr %p) {
348; CHECK-LABEL: vector_deinterleave_load_factor4:
349; CHECK:       # %bb.0:
350; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
351; CHECK-NEXT:    vlseg4e8.v v8, (a0)
352; CHECK-NEXT:    ret
353  %vec = load <vscale x 32 x i8>, ptr %p
354  %d0 = call {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8> %vec)
355  %d0.0 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %d0, 0
356  %d0.1 = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %d0, 1
357  %d1 = call {<vscale x 8 x i8>, <vscale x 8 x i8>} @llvm.vector.deinterleave2.nxv16i8(<vscale x 16 x i8> %d0.0)
358  %t0 = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } %d1, 0
359  %t2 = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } %d1, 1
360  %d2 = call {<vscale x 8 x i8>, <vscale x 8 x i8>} @llvm.vector.deinterleave2.nxv16i8(<vscale x 16 x i8> %d0.1)
361  %t1 = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } %d2, 0
362  %t3 = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i8> } %d2, 1
363
364  %res0 = insertvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } undef, <vscale x 8 x i8> %t0, 0
365  %res1 = insertvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } %res0, <vscale x 8 x i8> %t1, 1
366  %res2 = insertvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } %res1, <vscale x 8 x i8> %t2, 2
367  %res3 = insertvalue { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } %res2, <vscale x 8 x i8> %t3, 3
368  ret { <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8> } %res3
369}
370
371define {<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>} @vector_deinterleave_load_factor8(ptr %ptr) {
372; CHECK-LABEL: vector_deinterleave_load_factor8:
373; CHECK:       # %bb.0:
374; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
375; CHECK-NEXT:    vlseg8e32.v v8, (a0)
376; CHECK-NEXT:    ret
377  %vec = load <vscale x 16 x i32>, ptr %ptr
378  %d0 = call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.vector.deinterleave2.nxv16i32(<vscale x 16 x i32> %vec)
379  %d0.0 = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } %d0, 0
380  %d0.1 = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } %d0, 1
381  %d1 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %d0.0)
382  %d1.0 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %d1, 0
383  %d1.1 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %d1, 1
384  %d2 = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %d0.1)
385  %d2.0 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %d2, 0
386  %d2.1 = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %d2, 1
387
388  %d3 = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %d1.0)
389  %t0 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %d3, 0
390  %t4 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %d3, 1
391  %d4 = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %d1.1)
392  %t2 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %d4, 0
393  %t6 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %d4, 1
394  %d5 = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %d2.0)
395  %t1 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %d5, 0
396  %t5 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %d5, 1
397  %d6 = call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %d2.1)
398  %t3 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %d6, 0
399  %t7 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %d6, 1
400
401  %res0 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } undef, <vscale x 2 x i32> %t0, 0
402  %res1 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res0, <vscale x 2 x i32> %t1, 1
403  %res2 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res1, <vscale x 2 x i32> %t2, 2
404  %res3 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res2, <vscale x 2 x i32> %t3, 3
405  %res4 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res3, <vscale x 2 x i32> %t4, 4
406  %res5 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res4, <vscale x 2 x i32> %t5, 5
407  %res6 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res5, <vscale x 2 x i32> %t6, 6
408  %res7 = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res6, <vscale x 2 x i32> %t7, 7
409  ret { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %res7
410}
411