1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \ 3; RUN: -riscv-v-vector-bits-min=0 < %s | FileCheck %s --check-prefix=RV32 4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \ 5; RUN: -riscv-v-vector-bits-min=0 < %s | FileCheck %s --check-prefix=RV64 6 7; This test would lead one of the DAGCombiner's visitVSELECT optimizations to 8; call getSetCCResultType, from which we'd return an invalid MVT (<3 x i1>) 9; upon seeing that the V extension is enabled. The invalid MVT has a null 10; Type*, which then segfaulted when accessed (as an EVT). 11define void @vec3_setcc_crash(ptr %in, ptr %out) { 12; RV32-LABEL: vec3_setcc_crash: 13; RV32: # %bb.0: 14; RV32-NEXT: lw a0, 0(a0) 15; RV32-NEXT: srli a2, a0, 16 16; RV32-NEXT: slli a3, a0, 16 17; RV32-NEXT: slli a4, a0, 24 18; RV32-NEXT: slli a5, a0, 8 19; RV32-NEXT: srli a6, a3, 24 20; RV32-NEXT: srai a3, a3, 24 21; RV32-NEXT: srai a4, a4, 24 22; RV32-NEXT: srai a5, a5, 24 23; RV32-NEXT: sgtz a5, a5 24; RV32-NEXT: sgtz a4, a4 25; RV32-NEXT: sgtz a3, a3 26; RV32-NEXT: neg a3, a3 27; RV32-NEXT: neg a4, a4 28; RV32-NEXT: neg a5, a5 29; RV32-NEXT: and a3, a3, a6 30; RV32-NEXT: and a0, a4, a0 31; RV32-NEXT: and a2, a5, a2 32; RV32-NEXT: slli a3, a3, 8 33; RV32-NEXT: andi a0, a0, 255 34; RV32-NEXT: or a0, a0, a3 35; RV32-NEXT: sh a0, 0(a1) 36; RV32-NEXT: sb a2, 2(a1) 37; RV32-NEXT: ret 38; 39; RV64-LABEL: vec3_setcc_crash: 40; RV64: # %bb.0: 41; RV64-NEXT: lw a0, 0(a0) 42; RV64-NEXT: srliw a2, a0, 16 43; RV64-NEXT: slli a3, a0, 48 44; RV64-NEXT: slli a4, a0, 56 45; RV64-NEXT: slli a5, a0, 40 46; RV64-NEXT: srli a6, a3, 56 47; RV64-NEXT: srai a3, a3, 56 48; RV64-NEXT: srai a4, a4, 56 49; RV64-NEXT: srai a5, a5, 56 50; RV64-NEXT: sgtz a5, a5 51; RV64-NEXT: sgtz a4, a4 52; RV64-NEXT: sgtz a3, a3 53; RV64-NEXT: negw a3, a3 54; RV64-NEXT: negw a4, a4 55; RV64-NEXT: negw a5, a5 56; RV64-NEXT: and a3, a3, a6 57; RV64-NEXT: and a0, a4, a0 58; RV64-NEXT: and a2, a5, a2 59; RV64-NEXT: slli a3, a3, 8 60; RV64-NEXT: andi a0, a0, 255 61; RV64-NEXT: or a0, a0, a3 62; RV64-NEXT: sh a0, 0(a1) 63; RV64-NEXT: sb a2, 2(a1) 64; RV64-NEXT: ret 65 %a = load <3 x i8>, ptr %in 66 %cmp = icmp sgt <3 x i8> %a, zeroinitializer 67 %c = select <3 x i1> %cmp, <3 x i8> %a, <3 x i8> zeroinitializer 68 store <3 x i8> %c, ptr %out 69 ret void 70} 71