xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll (revision 97982a8c605fac7c86d02e641a6cd7898b3ca343) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-V
3; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,ZVE64X
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-V
5; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,ZVE64X
6
7define <vscale x 1 x i8> @vdivu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
8; CHECK-LABEL: vdivu_vv_nxv1i8:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
11; CHECK-NEXT:    vdivu.vv v8, v8, v9
12; CHECK-NEXT:    ret
13  %vc = udiv <vscale x 1 x i8> %va, %vb
14  ret <vscale x 1 x i8> %vc
15}
16
17define <vscale x 1 x i8> @vdivu_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
18; CHECK-LABEL: vdivu_vx_nxv1i8:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
21; CHECK-NEXT:    vdivu.vx v8, v8, a0
22; CHECK-NEXT:    ret
23  %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
24  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
25  %vc = udiv <vscale x 1 x i8> %va, %splat
26  ret <vscale x 1 x i8> %vc
27}
28
29define <vscale x 1 x i8> @vdivu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
30; CHECK-LABEL: vdivu_vi_nxv1i8_0:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    li a0, 33
33; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
34; CHECK-NEXT:    vmulhu.vx v8, v8, a0
35; CHECK-NEXT:    vsrl.vi v8, v8, 5
36; CHECK-NEXT:    ret
37  %vc = udiv <vscale x 1 x i8> %va, splat (i8 -7)
38  ret <vscale x 1 x i8> %vc
39}
40
41; Test V/1 to see if we can optimize it away for scalable vectors.
42define <vscale x 1 x i8> @vdivu_vi_nxv1i8_1(<vscale x 1 x i8> %va) {
43; CHECK-LABEL: vdivu_vi_nxv1i8_1:
44; CHECK:       # %bb.0:
45; CHECK-NEXT:    ret
46  %vc = udiv <vscale x 1 x i8> %va, splat (i8 1)
47  ret <vscale x 1 x i8> %vc
48}
49
50; Test 0/V to see if we can optimize it away for scalable vectors.
51define <vscale x 1 x i8> @vdivu_iv_nxv1i8_0(<vscale x 1 x i8> %va) {
52; CHECK-LABEL: vdivu_iv_nxv1i8_0:
53; CHECK:       # %bb.0:
54; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
55; CHECK-NEXT:    vmv.v.i v8, 0
56; CHECK-NEXT:    ret
57  %vc = udiv <vscale x 1 x i8> splat (i8 0), %va
58  ret <vscale x 1 x i8> %vc
59}
60
61define <vscale x 2 x i8> @vdivu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
62; CHECK-LABEL: vdivu_vv_nxv2i8:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
65; CHECK-NEXT:    vdivu.vv v8, v8, v9
66; CHECK-NEXT:    ret
67  %vc = udiv <vscale x 2 x i8> %va, %vb
68  ret <vscale x 2 x i8> %vc
69}
70
71define <vscale x 2 x i8> @vdivu_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
72; CHECK-LABEL: vdivu_vx_nxv2i8:
73; CHECK:       # %bb.0:
74; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
75; CHECK-NEXT:    vdivu.vx v8, v8, a0
76; CHECK-NEXT:    ret
77  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
78  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
79  %vc = udiv <vscale x 2 x i8> %va, %splat
80  ret <vscale x 2 x i8> %vc
81}
82
83define <vscale x 2 x i8> @vdivu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
84; CHECK-LABEL: vdivu_vi_nxv2i8_0:
85; CHECK:       # %bb.0:
86; CHECK-NEXT:    li a0, 33
87; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
88; CHECK-NEXT:    vmulhu.vx v8, v8, a0
89; CHECK-NEXT:    vsrl.vi v8, v8, 5
90; CHECK-NEXT:    ret
91  %vc = udiv <vscale x 2 x i8> %va, splat (i8 -7)
92  ret <vscale x 2 x i8> %vc
93}
94
95define <vscale x 4 x i8> @vdivu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
96; CHECK-LABEL: vdivu_vv_nxv4i8:
97; CHECK:       # %bb.0:
98; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
99; CHECK-NEXT:    vdivu.vv v8, v8, v9
100; CHECK-NEXT:    ret
101  %vc = udiv <vscale x 4 x i8> %va, %vb
102  ret <vscale x 4 x i8> %vc
103}
104
105define <vscale x 4 x i8> @vdivu_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
106; CHECK-LABEL: vdivu_vx_nxv4i8:
107; CHECK:       # %bb.0:
108; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
109; CHECK-NEXT:    vdivu.vx v8, v8, a0
110; CHECK-NEXT:    ret
111  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
112  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
113  %vc = udiv <vscale x 4 x i8> %va, %splat
114  ret <vscale x 4 x i8> %vc
115}
116
117define <vscale x 4 x i8> @vdivu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
118; CHECK-LABEL: vdivu_vi_nxv4i8_0:
119; CHECK:       # %bb.0:
120; CHECK-NEXT:    li a0, 33
121; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
122; CHECK-NEXT:    vmulhu.vx v8, v8, a0
123; CHECK-NEXT:    vsrl.vi v8, v8, 5
124; CHECK-NEXT:    ret
125  %vc = udiv <vscale x 4 x i8> %va, splat (i8 -7)
126  ret <vscale x 4 x i8> %vc
127}
128
129define <vscale x 8 x i8> @vdivu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
130; CHECK-LABEL: vdivu_vv_nxv8i8:
131; CHECK:       # %bb.0:
132; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
133; CHECK-NEXT:    vdivu.vv v8, v8, v9
134; CHECK-NEXT:    ret
135  %vc = udiv <vscale x 8 x i8> %va, %vb
136  ret <vscale x 8 x i8> %vc
137}
138
139define <vscale x 8 x i8> @vdivu_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
140; CHECK-LABEL: vdivu_vx_nxv8i8:
141; CHECK:       # %bb.0:
142; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
143; CHECK-NEXT:    vdivu.vx v8, v8, a0
144; CHECK-NEXT:    ret
145  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
146  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
147  %vc = udiv <vscale x 8 x i8> %va, %splat
148  ret <vscale x 8 x i8> %vc
149}
150
151define <vscale x 8 x i8> @vdivu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
152; CHECK-LABEL: vdivu_vi_nxv8i8_0:
153; CHECK:       # %bb.0:
154; CHECK-NEXT:    li a0, 33
155; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
156; CHECK-NEXT:    vmulhu.vx v8, v8, a0
157; CHECK-NEXT:    vsrl.vi v8, v8, 5
158; CHECK-NEXT:    ret
159  %vc = udiv <vscale x 8 x i8> %va, splat (i8 -7)
160  ret <vscale x 8 x i8> %vc
161}
162
163define <vscale x 16 x i8> @vdivu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
164; CHECK-LABEL: vdivu_vv_nxv16i8:
165; CHECK:       # %bb.0:
166; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
167; CHECK-NEXT:    vdivu.vv v8, v8, v10
168; CHECK-NEXT:    ret
169  %vc = udiv <vscale x 16 x i8> %va, %vb
170  ret <vscale x 16 x i8> %vc
171}
172
173define <vscale x 16 x i8> @vdivu_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
174; CHECK-LABEL: vdivu_vx_nxv16i8:
175; CHECK:       # %bb.0:
176; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
177; CHECK-NEXT:    vdivu.vx v8, v8, a0
178; CHECK-NEXT:    ret
179  %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
180  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
181  %vc = udiv <vscale x 16 x i8> %va, %splat
182  ret <vscale x 16 x i8> %vc
183}
184
185define <vscale x 16 x i8> @vdivu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
186; CHECK-LABEL: vdivu_vi_nxv16i8_0:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    li a0, 33
189; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
190; CHECK-NEXT:    vmulhu.vx v8, v8, a0
191; CHECK-NEXT:    vsrl.vi v8, v8, 5
192; CHECK-NEXT:    ret
193  %vc = udiv <vscale x 16 x i8> %va, splat (i8 -7)
194  ret <vscale x 16 x i8> %vc
195}
196
197define <vscale x 32 x i8> @vdivu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
198; CHECK-LABEL: vdivu_vv_nxv32i8:
199; CHECK:       # %bb.0:
200; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
201; CHECK-NEXT:    vdivu.vv v8, v8, v12
202; CHECK-NEXT:    ret
203  %vc = udiv <vscale x 32 x i8> %va, %vb
204  ret <vscale x 32 x i8> %vc
205}
206
207define <vscale x 32 x i8> @vdivu_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
208; CHECK-LABEL: vdivu_vx_nxv32i8:
209; CHECK:       # %bb.0:
210; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
211; CHECK-NEXT:    vdivu.vx v8, v8, a0
212; CHECK-NEXT:    ret
213  %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
214  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
215  %vc = udiv <vscale x 32 x i8> %va, %splat
216  ret <vscale x 32 x i8> %vc
217}
218
219define <vscale x 32 x i8> @vdivu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
220; CHECK-LABEL: vdivu_vi_nxv32i8_0:
221; CHECK:       # %bb.0:
222; CHECK-NEXT:    li a0, 33
223; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
224; CHECK-NEXT:    vmulhu.vx v8, v8, a0
225; CHECK-NEXT:    vsrl.vi v8, v8, 5
226; CHECK-NEXT:    ret
227  %vc = udiv <vscale x 32 x i8> %va, splat (i8 -7)
228  ret <vscale x 32 x i8> %vc
229}
230
231define <vscale x 64 x i8> @vdivu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
232; CHECK-LABEL: vdivu_vv_nxv64i8:
233; CHECK:       # %bb.0:
234; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
235; CHECK-NEXT:    vdivu.vv v8, v8, v16
236; CHECK-NEXT:    ret
237  %vc = udiv <vscale x 64 x i8> %va, %vb
238  ret <vscale x 64 x i8> %vc
239}
240
241define <vscale x 64 x i8> @vdivu_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
242; CHECK-LABEL: vdivu_vx_nxv64i8:
243; CHECK:       # %bb.0:
244; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
245; CHECK-NEXT:    vdivu.vx v8, v8, a0
246; CHECK-NEXT:    ret
247  %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
248  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
249  %vc = udiv <vscale x 64 x i8> %va, %splat
250  ret <vscale x 64 x i8> %vc
251}
252
253define <vscale x 64 x i8> @vdivu_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
254; CHECK-LABEL: vdivu_vi_nxv64i8_0:
255; CHECK:       # %bb.0:
256; CHECK-NEXT:    li a0, 33
257; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
258; CHECK-NEXT:    vmulhu.vx v8, v8, a0
259; CHECK-NEXT:    vsrl.vi v8, v8, 5
260; CHECK-NEXT:    ret
261  %vc = udiv <vscale x 64 x i8> %va, splat (i8 -7)
262  ret <vscale x 64 x i8> %vc
263}
264
265define <vscale x 1 x i16> @vdivu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
266; CHECK-LABEL: vdivu_vv_nxv1i16:
267; CHECK:       # %bb.0:
268; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
269; CHECK-NEXT:    vdivu.vv v8, v8, v9
270; CHECK-NEXT:    ret
271  %vc = udiv <vscale x 1 x i16> %va, %vb
272  ret <vscale x 1 x i16> %vc
273}
274
275define <vscale x 1 x i16> @vdivu_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
276; CHECK-LABEL: vdivu_vx_nxv1i16:
277; CHECK:       # %bb.0:
278; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
279; CHECK-NEXT:    vdivu.vx v8, v8, a0
280; CHECK-NEXT:    ret
281  %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
282  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
283  %vc = udiv <vscale x 1 x i16> %va, %splat
284  ret <vscale x 1 x i16> %vc
285}
286
287define <vscale x 1 x i16> @vdivu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
288; CHECK-LABEL: vdivu_vi_nxv1i16_0:
289; CHECK:       # %bb.0:
290; CHECK-NEXT:    lui a0, 2
291; CHECK-NEXT:    addi a0, a0, 1
292; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
293; CHECK-NEXT:    vmulhu.vx v8, v8, a0
294; CHECK-NEXT:    vsrl.vi v8, v8, 13
295; CHECK-NEXT:    ret
296  %vc = udiv <vscale x 1 x i16> %va, splat (i16 -7)
297  ret <vscale x 1 x i16> %vc
298}
299
300define <vscale x 2 x i16> @vdivu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
301; CHECK-LABEL: vdivu_vv_nxv2i16:
302; CHECK:       # %bb.0:
303; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
304; CHECK-NEXT:    vdivu.vv v8, v8, v9
305; CHECK-NEXT:    ret
306  %vc = udiv <vscale x 2 x i16> %va, %vb
307  ret <vscale x 2 x i16> %vc
308}
309
310define <vscale x 2 x i16> @vdivu_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
311; CHECK-LABEL: vdivu_vx_nxv2i16:
312; CHECK:       # %bb.0:
313; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
314; CHECK-NEXT:    vdivu.vx v8, v8, a0
315; CHECK-NEXT:    ret
316  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
317  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
318  %vc = udiv <vscale x 2 x i16> %va, %splat
319  ret <vscale x 2 x i16> %vc
320}
321
322define <vscale x 2 x i16> @vdivu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
323; CHECK-LABEL: vdivu_vi_nxv2i16_0:
324; CHECK:       # %bb.0:
325; CHECK-NEXT:    lui a0, 2
326; CHECK-NEXT:    addi a0, a0, 1
327; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
328; CHECK-NEXT:    vmulhu.vx v8, v8, a0
329; CHECK-NEXT:    vsrl.vi v8, v8, 13
330; CHECK-NEXT:    ret
331  %vc = udiv <vscale x 2 x i16> %va, splat (i16 -7)
332  ret <vscale x 2 x i16> %vc
333}
334
335define <vscale x 4 x i16> @vdivu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
336; CHECK-LABEL: vdivu_vv_nxv4i16:
337; CHECK:       # %bb.0:
338; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
339; CHECK-NEXT:    vdivu.vv v8, v8, v9
340; CHECK-NEXT:    ret
341  %vc = udiv <vscale x 4 x i16> %va, %vb
342  ret <vscale x 4 x i16> %vc
343}
344
345define <vscale x 4 x i16> @vdivu_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
346; CHECK-LABEL: vdivu_vx_nxv4i16:
347; CHECK:       # %bb.0:
348; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
349; CHECK-NEXT:    vdivu.vx v8, v8, a0
350; CHECK-NEXT:    ret
351  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
352  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
353  %vc = udiv <vscale x 4 x i16> %va, %splat
354  ret <vscale x 4 x i16> %vc
355}
356
357define <vscale x 4 x i16> @vdivu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
358; CHECK-LABEL: vdivu_vi_nxv4i16_0:
359; CHECK:       # %bb.0:
360; CHECK-NEXT:    lui a0, 2
361; CHECK-NEXT:    addi a0, a0, 1
362; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
363; CHECK-NEXT:    vmulhu.vx v8, v8, a0
364; CHECK-NEXT:    vsrl.vi v8, v8, 13
365; CHECK-NEXT:    ret
366  %vc = udiv <vscale x 4 x i16> %va, splat (i16 -7)
367  ret <vscale x 4 x i16> %vc
368}
369
370define <vscale x 8 x i16> @vdivu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
371; CHECK-LABEL: vdivu_vv_nxv8i16:
372; CHECK:       # %bb.0:
373; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
374; CHECK-NEXT:    vdivu.vv v8, v8, v10
375; CHECK-NEXT:    ret
376  %vc = udiv <vscale x 8 x i16> %va, %vb
377  ret <vscale x 8 x i16> %vc
378}
379
380define <vscale x 8 x i16> @vdivu_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
381; CHECK-LABEL: vdivu_vx_nxv8i16:
382; CHECK:       # %bb.0:
383; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
384; CHECK-NEXT:    vdivu.vx v8, v8, a0
385; CHECK-NEXT:    ret
386  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
387  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
388  %vc = udiv <vscale x 8 x i16> %va, %splat
389  ret <vscale x 8 x i16> %vc
390}
391
392define <vscale x 8 x i16> @vdivu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
393; CHECK-LABEL: vdivu_vi_nxv8i16_0:
394; CHECK:       # %bb.0:
395; CHECK-NEXT:    lui a0, 2
396; CHECK-NEXT:    addi a0, a0, 1
397; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
398; CHECK-NEXT:    vmulhu.vx v8, v8, a0
399; CHECK-NEXT:    vsrl.vi v8, v8, 13
400; CHECK-NEXT:    ret
401  %vc = udiv <vscale x 8 x i16> %va, splat (i16 -7)
402  ret <vscale x 8 x i16> %vc
403}
404
405define <vscale x 16 x i16> @vdivu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
406; CHECK-LABEL: vdivu_vv_nxv16i16:
407; CHECK:       # %bb.0:
408; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
409; CHECK-NEXT:    vdivu.vv v8, v8, v12
410; CHECK-NEXT:    ret
411  %vc = udiv <vscale x 16 x i16> %va, %vb
412  ret <vscale x 16 x i16> %vc
413}
414
415define <vscale x 16 x i16> @vdivu_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
416; CHECK-LABEL: vdivu_vx_nxv16i16:
417; CHECK:       # %bb.0:
418; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
419; CHECK-NEXT:    vdivu.vx v8, v8, a0
420; CHECK-NEXT:    ret
421  %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
422  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
423  %vc = udiv <vscale x 16 x i16> %va, %splat
424  ret <vscale x 16 x i16> %vc
425}
426
427define <vscale x 16 x i16> @vdivu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
428; CHECK-LABEL: vdivu_vi_nxv16i16_0:
429; CHECK:       # %bb.0:
430; CHECK-NEXT:    lui a0, 2
431; CHECK-NEXT:    addi a0, a0, 1
432; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
433; CHECK-NEXT:    vmulhu.vx v8, v8, a0
434; CHECK-NEXT:    vsrl.vi v8, v8, 13
435; CHECK-NEXT:    ret
436  %vc = udiv <vscale x 16 x i16> %va, splat (i16 -7)
437  ret <vscale x 16 x i16> %vc
438}
439
440define <vscale x 32 x i16> @vdivu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
441; CHECK-LABEL: vdivu_vv_nxv32i16:
442; CHECK:       # %bb.0:
443; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
444; CHECK-NEXT:    vdivu.vv v8, v8, v16
445; CHECK-NEXT:    ret
446  %vc = udiv <vscale x 32 x i16> %va, %vb
447  ret <vscale x 32 x i16> %vc
448}
449
450define <vscale x 32 x i16> @vdivu_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
451; CHECK-LABEL: vdivu_vx_nxv32i16:
452; CHECK:       # %bb.0:
453; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
454; CHECK-NEXT:    vdivu.vx v8, v8, a0
455; CHECK-NEXT:    ret
456  %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
457  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
458  %vc = udiv <vscale x 32 x i16> %va, %splat
459  ret <vscale x 32 x i16> %vc
460}
461
462define <vscale x 32 x i16> @vdivu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
463; CHECK-LABEL: vdivu_vi_nxv32i16_0:
464; CHECK:       # %bb.0:
465; CHECK-NEXT:    lui a0, 2
466; CHECK-NEXT:    addi a0, a0, 1
467; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
468; CHECK-NEXT:    vmulhu.vx v8, v8, a0
469; CHECK-NEXT:    vsrl.vi v8, v8, 13
470; CHECK-NEXT:    ret
471  %vc = udiv <vscale x 32 x i16> %va, splat (i16 -7)
472  ret <vscale x 32 x i16> %vc
473}
474
475define <vscale x 1 x i32> @vdivu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
476; CHECK-LABEL: vdivu_vv_nxv1i32:
477; CHECK:       # %bb.0:
478; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
479; CHECK-NEXT:    vdivu.vv v8, v8, v9
480; CHECK-NEXT:    ret
481  %vc = udiv <vscale x 1 x i32> %va, %vb
482  ret <vscale x 1 x i32> %vc
483}
484
485define <vscale x 1 x i32> @vdivu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
486; CHECK-LABEL: vdivu_vx_nxv1i32:
487; CHECK:       # %bb.0:
488; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
489; CHECK-NEXT:    vdivu.vx v8, v8, a0
490; CHECK-NEXT:    ret
491  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
492  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
493  %vc = udiv <vscale x 1 x i32> %va, %splat
494  ret <vscale x 1 x i32> %vc
495}
496
497define <vscale x 1 x i32> @vdivu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
498; CHECK-LABEL: vdivu_vi_nxv1i32_0:
499; CHECK:       # %bb.0:
500; CHECK-NEXT:    lui a0, 131072
501; CHECK-NEXT:    addi a0, a0, 1
502; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
503; CHECK-NEXT:    vmulhu.vx v8, v8, a0
504; CHECK-NEXT:    vsrl.vi v8, v8, 29
505; CHECK-NEXT:    ret
506  %vc = udiv <vscale x 1 x i32> %va, splat (i32 -7)
507  ret <vscale x 1 x i32> %vc
508}
509
510define <vscale x 2 x i32> @vdivu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
511; CHECK-LABEL: vdivu_vv_nxv2i32:
512; CHECK:       # %bb.0:
513; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
514; CHECK-NEXT:    vdivu.vv v8, v8, v9
515; CHECK-NEXT:    ret
516  %vc = udiv <vscale x 2 x i32> %va, %vb
517  ret <vscale x 2 x i32> %vc
518}
519
520define <vscale x 2 x i32> @vdivu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
521; CHECK-LABEL: vdivu_vx_nxv2i32:
522; CHECK:       # %bb.0:
523; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
524; CHECK-NEXT:    vdivu.vx v8, v8, a0
525; CHECK-NEXT:    ret
526  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
527  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
528  %vc = udiv <vscale x 2 x i32> %va, %splat
529  ret <vscale x 2 x i32> %vc
530}
531
532define <vscale x 2 x i32> @vdivu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
533; CHECK-LABEL: vdivu_vi_nxv2i32_0:
534; CHECK:       # %bb.0:
535; CHECK-NEXT:    lui a0, 131072
536; CHECK-NEXT:    addi a0, a0, 1
537; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
538; CHECK-NEXT:    vmulhu.vx v8, v8, a0
539; CHECK-NEXT:    vsrl.vi v8, v8, 29
540; CHECK-NEXT:    ret
541  %vc = udiv <vscale x 2 x i32> %va, splat (i32 -7)
542  ret <vscale x 2 x i32> %vc
543}
544
545define <vscale x 4 x i32> @vdivu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
546; CHECK-LABEL: vdivu_vv_nxv4i32:
547; CHECK:       # %bb.0:
548; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
549; CHECK-NEXT:    vdivu.vv v8, v8, v10
550; CHECK-NEXT:    ret
551  %vc = udiv <vscale x 4 x i32> %va, %vb
552  ret <vscale x 4 x i32> %vc
553}
554
555define <vscale x 4 x i32> @vdivu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
556; CHECK-LABEL: vdivu_vx_nxv4i32:
557; CHECK:       # %bb.0:
558; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
559; CHECK-NEXT:    vdivu.vx v8, v8, a0
560; CHECK-NEXT:    ret
561  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
562  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
563  %vc = udiv <vscale x 4 x i32> %va, %splat
564  ret <vscale x 4 x i32> %vc
565}
566
567define <vscale x 4 x i32> @vdivu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
568; CHECK-LABEL: vdivu_vi_nxv4i32_0:
569; CHECK:       # %bb.0:
570; CHECK-NEXT:    lui a0, 131072
571; CHECK-NEXT:    addi a0, a0, 1
572; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
573; CHECK-NEXT:    vmulhu.vx v8, v8, a0
574; CHECK-NEXT:    vsrl.vi v8, v8, 29
575; CHECK-NEXT:    ret
576  %vc = udiv <vscale x 4 x i32> %va, splat (i32 -7)
577  ret <vscale x 4 x i32> %vc
578}
579
580define <vscale x 8 x i32> @vdivu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
581; CHECK-LABEL: vdivu_vv_nxv8i32:
582; CHECK:       # %bb.0:
583; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
584; CHECK-NEXT:    vdivu.vv v8, v8, v12
585; CHECK-NEXT:    ret
586  %vc = udiv <vscale x 8 x i32> %va, %vb
587  ret <vscale x 8 x i32> %vc
588}
589
590define <vscale x 8 x i32> @vdivu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
591; CHECK-LABEL: vdivu_vx_nxv8i32:
592; CHECK:       # %bb.0:
593; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
594; CHECK-NEXT:    vdivu.vx v8, v8, a0
595; CHECK-NEXT:    ret
596  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
597  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
598  %vc = udiv <vscale x 8 x i32> %va, %splat
599  ret <vscale x 8 x i32> %vc
600}
601
602define <vscale x 8 x i32> @vdivu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
603; CHECK-LABEL: vdivu_vi_nxv8i32_0:
604; CHECK:       # %bb.0:
605; CHECK-NEXT:    lui a0, 131072
606; CHECK-NEXT:    addi a0, a0, 1
607; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
608; CHECK-NEXT:    vmulhu.vx v8, v8, a0
609; CHECK-NEXT:    vsrl.vi v8, v8, 29
610; CHECK-NEXT:    ret
611  %vc = udiv <vscale x 8 x i32> %va, splat (i32 -7)
612  ret <vscale x 8 x i32> %vc
613}
614
615define <vscale x 16 x i32> @vdivu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
616; CHECK-LABEL: vdivu_vv_nxv16i32:
617; CHECK:       # %bb.0:
618; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
619; CHECK-NEXT:    vdivu.vv v8, v8, v16
620; CHECK-NEXT:    ret
621  %vc = udiv <vscale x 16 x i32> %va, %vb
622  ret <vscale x 16 x i32> %vc
623}
624
625define <vscale x 16 x i32> @vdivu_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
626; CHECK-LABEL: vdivu_vx_nxv16i32:
627; CHECK:       # %bb.0:
628; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
629; CHECK-NEXT:    vdivu.vx v8, v8, a0
630; CHECK-NEXT:    ret
631  %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
632  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
633  %vc = udiv <vscale x 16 x i32> %va, %splat
634  ret <vscale x 16 x i32> %vc
635}
636
637define <vscale x 16 x i32> @vdivu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
638; CHECK-LABEL: vdivu_vi_nxv16i32_0:
639; CHECK:       # %bb.0:
640; CHECK-NEXT:    lui a0, 131072
641; CHECK-NEXT:    addi a0, a0, 1
642; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
643; CHECK-NEXT:    vmulhu.vx v8, v8, a0
644; CHECK-NEXT:    vsrl.vi v8, v8, 29
645; CHECK-NEXT:    ret
646  %vc = udiv <vscale x 16 x i32> %va, splat (i32 -7)
647  ret <vscale x 16 x i32> %vc
648}
649
650define <vscale x 1 x i64> @vdivu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
651; CHECK-LABEL: vdivu_vv_nxv1i64:
652; CHECK:       # %bb.0:
653; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
654; CHECK-NEXT:    vdivu.vv v8, v8, v9
655; CHECK-NEXT:    ret
656  %vc = udiv <vscale x 1 x i64> %va, %vb
657  ret <vscale x 1 x i64> %vc
658}
659
660define <vscale x 1 x i64> @vdivu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
661; RV32-LABEL: vdivu_vx_nxv1i64:
662; RV32:       # %bb.0:
663; RV32-NEXT:    addi sp, sp, -16
664; RV32-NEXT:    .cfi_def_cfa_offset 16
665; RV32-NEXT:    sw a0, 8(sp)
666; RV32-NEXT:    sw a1, 12(sp)
667; RV32-NEXT:    addi a0, sp, 8
668; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
669; RV32-NEXT:    vlse64.v v9, (a0), zero
670; RV32-NEXT:    vdivu.vv v8, v8, v9
671; RV32-NEXT:    addi sp, sp, 16
672; RV32-NEXT:    .cfi_def_cfa_offset 0
673; RV32-NEXT:    ret
674;
675; RV64-LABEL: vdivu_vx_nxv1i64:
676; RV64:       # %bb.0:
677; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
678; RV64-NEXT:    vdivu.vx v8, v8, a0
679; RV64-NEXT:    ret
680  %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
681  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
682  %vc = udiv <vscale x 1 x i64> %va, %splat
683  ret <vscale x 1 x i64> %vc
684}
685
686define <vscale x 1 x i64> @vdivu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
687; RV32-V-LABEL: vdivu_vi_nxv1i64_0:
688; RV32-V:       # %bb.0:
689; RV32-V-NEXT:    addi sp, sp, -16
690; RV32-V-NEXT:    .cfi_def_cfa_offset 16
691; RV32-V-NEXT:    lui a0, 131072
692; RV32-V-NEXT:    li a1, 1
693; RV32-V-NEXT:    sw a1, 8(sp)
694; RV32-V-NEXT:    sw a0, 12(sp)
695; RV32-V-NEXT:    addi a0, sp, 8
696; RV32-V-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
697; RV32-V-NEXT:    vlse64.v v9, (a0), zero
698; RV32-V-NEXT:    vmulhu.vv v8, v8, v9
699; RV32-V-NEXT:    li a0, 61
700; RV32-V-NEXT:    vsrl.vx v8, v8, a0
701; RV32-V-NEXT:    addi sp, sp, 16
702; RV32-V-NEXT:    .cfi_def_cfa_offset 0
703; RV32-V-NEXT:    ret
704;
705; ZVE64X-LABEL: vdivu_vi_nxv1i64_0:
706; ZVE64X:       # %bb.0:
707; ZVE64X-NEXT:    li a0, -7
708; ZVE64X-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
709; ZVE64X-NEXT:    vdivu.vx v8, v8, a0
710; ZVE64X-NEXT:    ret
711;
712; RV64-V-LABEL: vdivu_vi_nxv1i64_0:
713; RV64-V:       # %bb.0:
714; RV64-V-NEXT:    li a0, 1
715; RV64-V-NEXT:    slli a0, a0, 61
716; RV64-V-NEXT:    addi a0, a0, 1
717; RV64-V-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
718; RV64-V-NEXT:    vmulhu.vx v8, v8, a0
719; RV64-V-NEXT:    li a0, 61
720; RV64-V-NEXT:    vsrl.vx v8, v8, a0
721; RV64-V-NEXT:    ret
722  %vc = udiv <vscale x 1 x i64> %va, splat (i64 -7)
723  ret <vscale x 1 x i64> %vc
724}
725
726define <vscale x 1 x i64> @vdivu_vi_nxv1i64_1(<vscale x 1 x i64> %va) {
727; CHECK-LABEL: vdivu_vi_nxv1i64_1:
728; CHECK:       # %bb.0:
729; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
730; CHECK-NEXT:    vsrl.vi v8, v8, 1
731; CHECK-NEXT:    ret
732  %vc = udiv <vscale x 1 x i64> %va, splat (i64 2)
733  ret <vscale x 1 x i64> %vc
734}
735
736; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2
737define <vscale x 1 x i64> @vdivu_vi_nxv1i64_2(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
738; CHECK-LABEL: vdivu_vi_nxv1i64_2:
739; CHECK:       # %bb.0:
740; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
741; CHECK-NEXT:    vadd.vi v9, v9, 4
742; CHECK-NEXT:    vsrl.vv v8, v8, v9
743; CHECK-NEXT:    ret
744  %vc = shl <vscale x 1 x i64> splat (i64 16), %vb
745  %vd = udiv <vscale x 1 x i64> %va, %vc
746  ret <vscale x 1 x i64> %vd
747}
748
749define <vscale x 2 x i64> @vdivu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
750; CHECK-LABEL: vdivu_vv_nxv2i64:
751; CHECK:       # %bb.0:
752; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
753; CHECK-NEXT:    vdivu.vv v8, v8, v10
754; CHECK-NEXT:    ret
755  %vc = udiv <vscale x 2 x i64> %va, %vb
756  ret <vscale x 2 x i64> %vc
757}
758
759define <vscale x 2 x i64> @vdivu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
760; RV32-LABEL: vdivu_vx_nxv2i64:
761; RV32:       # %bb.0:
762; RV32-NEXT:    addi sp, sp, -16
763; RV32-NEXT:    .cfi_def_cfa_offset 16
764; RV32-NEXT:    sw a0, 8(sp)
765; RV32-NEXT:    sw a1, 12(sp)
766; RV32-NEXT:    addi a0, sp, 8
767; RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
768; RV32-NEXT:    vlse64.v v10, (a0), zero
769; RV32-NEXT:    vdivu.vv v8, v8, v10
770; RV32-NEXT:    addi sp, sp, 16
771; RV32-NEXT:    .cfi_def_cfa_offset 0
772; RV32-NEXT:    ret
773;
774; RV64-LABEL: vdivu_vx_nxv2i64:
775; RV64:       # %bb.0:
776; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
777; RV64-NEXT:    vdivu.vx v8, v8, a0
778; RV64-NEXT:    ret
779  %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
780  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
781  %vc = udiv <vscale x 2 x i64> %va, %splat
782  ret <vscale x 2 x i64> %vc
783}
784
785define <vscale x 2 x i64> @vdivu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
786; RV32-V-LABEL: vdivu_vi_nxv2i64_0:
787; RV32-V:       # %bb.0:
788; RV32-V-NEXT:    addi sp, sp, -16
789; RV32-V-NEXT:    .cfi_def_cfa_offset 16
790; RV32-V-NEXT:    lui a0, 131072
791; RV32-V-NEXT:    li a1, 1
792; RV32-V-NEXT:    sw a1, 8(sp)
793; RV32-V-NEXT:    sw a0, 12(sp)
794; RV32-V-NEXT:    addi a0, sp, 8
795; RV32-V-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
796; RV32-V-NEXT:    vlse64.v v10, (a0), zero
797; RV32-V-NEXT:    vmulhu.vv v8, v8, v10
798; RV32-V-NEXT:    li a0, 61
799; RV32-V-NEXT:    vsrl.vx v8, v8, a0
800; RV32-V-NEXT:    addi sp, sp, 16
801; RV32-V-NEXT:    .cfi_def_cfa_offset 0
802; RV32-V-NEXT:    ret
803;
804; ZVE64X-LABEL: vdivu_vi_nxv2i64_0:
805; ZVE64X:       # %bb.0:
806; ZVE64X-NEXT:    li a0, -7
807; ZVE64X-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
808; ZVE64X-NEXT:    vdivu.vx v8, v8, a0
809; ZVE64X-NEXT:    ret
810;
811; RV64-V-LABEL: vdivu_vi_nxv2i64_0:
812; RV64-V:       # %bb.0:
813; RV64-V-NEXT:    li a0, 1
814; RV64-V-NEXT:    slli a0, a0, 61
815; RV64-V-NEXT:    addi a0, a0, 1
816; RV64-V-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
817; RV64-V-NEXT:    vmulhu.vx v8, v8, a0
818; RV64-V-NEXT:    li a0, 61
819; RV64-V-NEXT:    vsrl.vx v8, v8, a0
820; RV64-V-NEXT:    ret
821  %vc = udiv <vscale x 2 x i64> %va, splat (i64 -7)
822  ret <vscale x 2 x i64> %vc
823}
824
825define <vscale x 2 x i64> @vdivu_vi_nxv2i64_1(<vscale x 2 x i64> %va) {
826; CHECK-LABEL: vdivu_vi_nxv2i64_1:
827; CHECK:       # %bb.0:
828; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
829; CHECK-NEXT:    vsrl.vi v8, v8, 1
830; CHECK-NEXT:    ret
831  %vc = udiv <vscale x 2 x i64> %va, splat (i64 2)
832  ret <vscale x 2 x i64> %vc
833}
834
835; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2
836define <vscale x 2 x i64> @vdivu_vi_nxv2i64_2(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
837; CHECK-LABEL: vdivu_vi_nxv2i64_2:
838; CHECK:       # %bb.0:
839; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
840; CHECK-NEXT:    vadd.vi v10, v10, 4
841; CHECK-NEXT:    vsrl.vv v8, v8, v10
842; CHECK-NEXT:    ret
843  %vc = shl <vscale x 2 x i64> splat (i64 16), %vb
844  %vd = udiv <vscale x 2 x i64> %va, %vc
845  ret <vscale x 2 x i64> %vd
846}
847
848define <vscale x 4 x i64> @vdivu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
849; CHECK-LABEL: vdivu_vv_nxv4i64:
850; CHECK:       # %bb.0:
851; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
852; CHECK-NEXT:    vdivu.vv v8, v8, v12
853; CHECK-NEXT:    ret
854  %vc = udiv <vscale x 4 x i64> %va, %vb
855  ret <vscale x 4 x i64> %vc
856}
857
858define <vscale x 4 x i64> @vdivu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
859; RV32-LABEL: vdivu_vx_nxv4i64:
860; RV32:       # %bb.0:
861; RV32-NEXT:    addi sp, sp, -16
862; RV32-NEXT:    .cfi_def_cfa_offset 16
863; RV32-NEXT:    sw a0, 8(sp)
864; RV32-NEXT:    sw a1, 12(sp)
865; RV32-NEXT:    addi a0, sp, 8
866; RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
867; RV32-NEXT:    vlse64.v v12, (a0), zero
868; RV32-NEXT:    vdivu.vv v8, v8, v12
869; RV32-NEXT:    addi sp, sp, 16
870; RV32-NEXT:    .cfi_def_cfa_offset 0
871; RV32-NEXT:    ret
872;
873; RV64-LABEL: vdivu_vx_nxv4i64:
874; RV64:       # %bb.0:
875; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
876; RV64-NEXT:    vdivu.vx v8, v8, a0
877; RV64-NEXT:    ret
878  %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
879  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
880  %vc = udiv <vscale x 4 x i64> %va, %splat
881  ret <vscale x 4 x i64> %vc
882}
883
884define <vscale x 4 x i64> @vdivu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
885; RV32-V-LABEL: vdivu_vi_nxv4i64_0:
886; RV32-V:       # %bb.0:
887; RV32-V-NEXT:    addi sp, sp, -16
888; RV32-V-NEXT:    .cfi_def_cfa_offset 16
889; RV32-V-NEXT:    lui a0, 131072
890; RV32-V-NEXT:    li a1, 1
891; RV32-V-NEXT:    sw a1, 8(sp)
892; RV32-V-NEXT:    sw a0, 12(sp)
893; RV32-V-NEXT:    addi a0, sp, 8
894; RV32-V-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
895; RV32-V-NEXT:    vlse64.v v12, (a0), zero
896; RV32-V-NEXT:    vmulhu.vv v8, v8, v12
897; RV32-V-NEXT:    li a0, 61
898; RV32-V-NEXT:    vsrl.vx v8, v8, a0
899; RV32-V-NEXT:    addi sp, sp, 16
900; RV32-V-NEXT:    .cfi_def_cfa_offset 0
901; RV32-V-NEXT:    ret
902;
903; ZVE64X-LABEL: vdivu_vi_nxv4i64_0:
904; ZVE64X:       # %bb.0:
905; ZVE64X-NEXT:    li a0, -7
906; ZVE64X-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
907; ZVE64X-NEXT:    vdivu.vx v8, v8, a0
908; ZVE64X-NEXT:    ret
909;
910; RV64-V-LABEL: vdivu_vi_nxv4i64_0:
911; RV64-V:       # %bb.0:
912; RV64-V-NEXT:    li a0, 1
913; RV64-V-NEXT:    slli a0, a0, 61
914; RV64-V-NEXT:    addi a0, a0, 1
915; RV64-V-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
916; RV64-V-NEXT:    vmulhu.vx v8, v8, a0
917; RV64-V-NEXT:    li a0, 61
918; RV64-V-NEXT:    vsrl.vx v8, v8, a0
919; RV64-V-NEXT:    ret
920  %vc = udiv <vscale x 4 x i64> %va, splat (i64 -7)
921  ret <vscale x 4 x i64> %vc
922}
923
924define <vscale x 4 x i64> @vdivu_vi_nxv4i64_1(<vscale x 4 x i64> %va) {
925; CHECK-LABEL: vdivu_vi_nxv4i64_1:
926; CHECK:       # %bb.0:
927; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
928; CHECK-NEXT:    vsrl.vi v8, v8, 1
929; CHECK-NEXT:    ret
930  %vc = udiv <vscale x 4 x i64> %va, splat (i64 2)
931  ret <vscale x 4 x i64> %vc
932}
933
934; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2
935define <vscale x 4 x i64> @vdivu_vi_nxv4i64_2(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
936; CHECK-LABEL: vdivu_vi_nxv4i64_2:
937; CHECK:       # %bb.0:
938; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
939; CHECK-NEXT:    vadd.vi v12, v12, 4
940; CHECK-NEXT:    vsrl.vv v8, v8, v12
941; CHECK-NEXT:    ret
942  %vc = shl <vscale x 4 x i64> splat (i64 16), %vb
943  %vd = udiv <vscale x 4 x i64> %va, %vc
944  ret <vscale x 4 x i64> %vd
945}
946
947define <vscale x 8 x i64> @vdivu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
948; CHECK-LABEL: vdivu_vv_nxv8i64:
949; CHECK:       # %bb.0:
950; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
951; CHECK-NEXT:    vdivu.vv v8, v8, v16
952; CHECK-NEXT:    ret
953  %vc = udiv <vscale x 8 x i64> %va, %vb
954  ret <vscale x 8 x i64> %vc
955}
956
957define <vscale x 8 x i64> @vdivu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
958; RV32-LABEL: vdivu_vx_nxv8i64:
959; RV32:       # %bb.0:
960; RV32-NEXT:    addi sp, sp, -16
961; RV32-NEXT:    .cfi_def_cfa_offset 16
962; RV32-NEXT:    sw a0, 8(sp)
963; RV32-NEXT:    sw a1, 12(sp)
964; RV32-NEXT:    addi a0, sp, 8
965; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
966; RV32-NEXT:    vlse64.v v16, (a0), zero
967; RV32-NEXT:    vdivu.vv v8, v8, v16
968; RV32-NEXT:    addi sp, sp, 16
969; RV32-NEXT:    .cfi_def_cfa_offset 0
970; RV32-NEXT:    ret
971;
972; RV64-LABEL: vdivu_vx_nxv8i64:
973; RV64:       # %bb.0:
974; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
975; RV64-NEXT:    vdivu.vx v8, v8, a0
976; RV64-NEXT:    ret
977  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
978  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
979  %vc = udiv <vscale x 8 x i64> %va, %splat
980  ret <vscale x 8 x i64> %vc
981}
982
983define <vscale x 8 x i64> @vdivu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
984; RV32-V-LABEL: vdivu_vi_nxv8i64_0:
985; RV32-V:       # %bb.0:
986; RV32-V-NEXT:    addi sp, sp, -16
987; RV32-V-NEXT:    .cfi_def_cfa_offset 16
988; RV32-V-NEXT:    lui a0, 131072
989; RV32-V-NEXT:    li a1, 1
990; RV32-V-NEXT:    sw a1, 8(sp)
991; RV32-V-NEXT:    sw a0, 12(sp)
992; RV32-V-NEXT:    addi a0, sp, 8
993; RV32-V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
994; RV32-V-NEXT:    vlse64.v v16, (a0), zero
995; RV32-V-NEXT:    vmulhu.vv v8, v8, v16
996; RV32-V-NEXT:    li a0, 61
997; RV32-V-NEXT:    vsrl.vx v8, v8, a0
998; RV32-V-NEXT:    addi sp, sp, 16
999; RV32-V-NEXT:    .cfi_def_cfa_offset 0
1000; RV32-V-NEXT:    ret
1001;
1002; ZVE64X-LABEL: vdivu_vi_nxv8i64_0:
1003; ZVE64X:       # %bb.0:
1004; ZVE64X-NEXT:    li a0, -7
1005; ZVE64X-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1006; ZVE64X-NEXT:    vdivu.vx v8, v8, a0
1007; ZVE64X-NEXT:    ret
1008;
1009; RV64-V-LABEL: vdivu_vi_nxv8i64_0:
1010; RV64-V:       # %bb.0:
1011; RV64-V-NEXT:    li a0, 1
1012; RV64-V-NEXT:    slli a0, a0, 61
1013; RV64-V-NEXT:    addi a0, a0, 1
1014; RV64-V-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1015; RV64-V-NEXT:    vmulhu.vx v8, v8, a0
1016; RV64-V-NEXT:    li a0, 61
1017; RV64-V-NEXT:    vsrl.vx v8, v8, a0
1018; RV64-V-NEXT:    ret
1019  %vc = udiv <vscale x 8 x i64> %va, splat (i64 -7)
1020  ret <vscale x 8 x i64> %vc
1021}
1022
1023define <vscale x 8 x i64> @vdivu_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
1024; CHECK-LABEL: vdivu_vi_nxv8i64_1:
1025; CHECK:       # %bb.0:
1026; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
1027; CHECK-NEXT:    vsrl.vi v8, v8, 1
1028; CHECK-NEXT:    ret
1029  %vc = udiv <vscale x 8 x i64> %va, splat (i64 2)
1030  ret <vscale x 8 x i64> %vc
1031}
1032
1033; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2
1034define <vscale x 8 x i64> @vdivu_vi_nxv8i64_2(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
1035; CHECK-LABEL: vdivu_vi_nxv8i64_2:
1036; CHECK:       # %bb.0:
1037; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
1038; CHECK-NEXT:    vadd.vi v16, v16, 4
1039; CHECK-NEXT:    vsrl.vv v8, v8, v16
1040; CHECK-NEXT:    ret
1041  %vc = shl <vscale x 8 x i64> splat (i64 16), %vb
1042  %vd = udiv <vscale x 8 x i64> %va, %vc
1043  ret <vscale x 8 x i64> %vd
1044}
1045
1046define <vscale x 8 x i32> @vdivu_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
1047; CHECK-LABEL: vdivu_vv_mask_nxv8i32:
1048; CHECK:       # %bb.0:
1049; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
1050; CHECK-NEXT:    vmv.v.i v16, 1
1051; CHECK-NEXT:    vmerge.vvm v12, v16, v12, v0
1052; CHECK-NEXT:    vdivu.vv v8, v8, v12
1053; CHECK-NEXT:    ret
1054  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> splat (i32 1)
1055  %vc = udiv <vscale x 8 x i32> %va, %vs
1056  ret <vscale x 8 x i32> %vc
1057}
1058
1059define <vscale x 8 x i32> @vdivu_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
1060; CHECK-LABEL: vdivu_vx_mask_nxv8i32:
1061; CHECK:       # %bb.0:
1062; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
1063; CHECK-NEXT:    vmv.v.i v12, 1
1064; CHECK-NEXT:    vmerge.vxm v12, v12, a0, v0
1065; CHECK-NEXT:    vdivu.vv v8, v8, v12
1066; CHECK-NEXT:    ret
1067  %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1068  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1069  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> splat (i32 1)
1070  %vc = udiv <vscale x 8 x i32> %va, %vs
1071  ret <vscale x 8 x i32> %vc
1072}
1073
1074define <vscale x 8 x i32> @vdivu_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
1075; CHECK-LABEL: vdivu_vi_mask_nxv8i32:
1076; CHECK:       # %bb.0:
1077; CHECK-NEXT:    lui a0, 149797
1078; CHECK-NEXT:    addi a0, a0, -1755
1079; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1080; CHECK-NEXT:    vmulhu.vx v12, v8, a0
1081; CHECK-NEXT:    vsub.vv v16, v8, v12
1082; CHECK-NEXT:    vsrl.vi v16, v16, 1
1083; CHECK-NEXT:    vadd.vv v12, v16, v12
1084; CHECK-NEXT:    vsrl.vi v8, v12, 2, v0.t
1085; CHECK-NEXT:    ret
1086  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> splat (i32 7), <vscale x 8 x i32> splat (i32 1)
1087  %vc = udiv <vscale x 8 x i32> %va, %vs
1088  ret <vscale x 8 x i32> %vc
1089}
1090