xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll (revision 97982a8c605fac7c86d02e641a6cd7898b3ca343) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
4
5define <vscale x 1 x i8> @vand_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
6; CHECK-LABEL: vand_vv_nxv1i8:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
9; CHECK-NEXT:    vand.vv v8, v8, v9
10; CHECK-NEXT:    ret
11  %vc = and <vscale x 1 x i8> %va, %vb
12  ret <vscale x 1 x i8> %vc
13}
14
15define <vscale x 1 x i8> @vand_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
16; CHECK-LABEL: vand_vx_nxv1i8:
17; CHECK:       # %bb.0:
18; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
19; CHECK-NEXT:    vand.vx v8, v8, a0
20; CHECK-NEXT:    ret
21  %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
22  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
23  %vc = and <vscale x 1 x i8> %va, %splat
24  ret <vscale x 1 x i8> %vc
25}
26
27define <vscale x 1 x i8> @vand_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
28; CHECK-LABEL: vand_vi_nxv1i8_0:
29; CHECK:       # %bb.0:
30; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
31; CHECK-NEXT:    vand.vi v8, v8, -10
32; CHECK-NEXT:    ret
33  %vc = and <vscale x 1 x i8> %va, splat (i8 -10)
34  ret <vscale x 1 x i8> %vc
35}
36
37define <vscale x 1 x i8> @vand_vi_nxv1i8_1(<vscale x 1 x i8> %va) {
38; CHECK-LABEL: vand_vi_nxv1i8_1:
39; CHECK:       # %bb.0:
40; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
41; CHECK-NEXT:    vand.vi v8, v8, 8
42; CHECK-NEXT:    ret
43  %vc = and <vscale x 1 x i8> %va, splat (i8 8)
44  ret <vscale x 1 x i8> %vc
45}
46
47define <vscale x 1 x i8> @vand_vi_nxv1i8_2(<vscale x 1 x i8> %va) {
48; CHECK-LABEL: vand_vi_nxv1i8_2:
49; CHECK:       # %bb.0:
50; CHECK-NEXT:    li a0, 16
51; CHECK-NEXT:    vsetvli a1, zero, e8, mf8, ta, ma
52; CHECK-NEXT:    vand.vx v8, v8, a0
53; CHECK-NEXT:    ret
54  %vc = and <vscale x 1 x i8> %va, splat (i8 16)
55  ret <vscale x 1 x i8> %vc
56}
57
58define <vscale x 2 x i8> @vand_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
59; CHECK-LABEL: vand_vv_nxv2i8:
60; CHECK:       # %bb.0:
61; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
62; CHECK-NEXT:    vand.vv v8, v8, v9
63; CHECK-NEXT:    ret
64  %vc = and <vscale x 2 x i8> %va, %vb
65  ret <vscale x 2 x i8> %vc
66}
67
68define <vscale x 2 x i8> @vand_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
69; CHECK-LABEL: vand_vx_nxv2i8:
70; CHECK:       # %bb.0:
71; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
72; CHECK-NEXT:    vand.vx v8, v8, a0
73; CHECK-NEXT:    ret
74  %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
75  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
76  %vc = and <vscale x 2 x i8> %va, %splat
77  ret <vscale x 2 x i8> %vc
78}
79
80define <vscale x 2 x i8> @vand_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
81; CHECK-LABEL: vand_vi_nxv2i8_0:
82; CHECK:       # %bb.0:
83; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
84; CHECK-NEXT:    vand.vi v8, v8, -10
85; CHECK-NEXT:    ret
86  %vc = and <vscale x 2 x i8> %va, splat (i8 -10)
87  ret <vscale x 2 x i8> %vc
88}
89
90define <vscale x 2 x i8> @vand_vi_nxv2i8_1(<vscale x 2 x i8> %va) {
91; CHECK-LABEL: vand_vi_nxv2i8_1:
92; CHECK:       # %bb.0:
93; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
94; CHECK-NEXT:    vand.vi v8, v8, 8
95; CHECK-NEXT:    ret
96  %vc = and <vscale x 2 x i8> %va, splat (i8 8)
97  ret <vscale x 2 x i8> %vc
98}
99
100define <vscale x 2 x i8> @vand_vi_nxv2i8_2(<vscale x 2 x i8> %va) {
101; CHECK-LABEL: vand_vi_nxv2i8_2:
102; CHECK:       # %bb.0:
103; CHECK-NEXT:    li a0, 16
104; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
105; CHECK-NEXT:    vand.vx v8, v8, a0
106; CHECK-NEXT:    ret
107  %vc = and <vscale x 2 x i8> %va, splat (i8 16)
108  ret <vscale x 2 x i8> %vc
109}
110
111define <vscale x 4 x i8> @vand_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
112; CHECK-LABEL: vand_vv_nxv4i8:
113; CHECK:       # %bb.0:
114; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
115; CHECK-NEXT:    vand.vv v8, v8, v9
116; CHECK-NEXT:    ret
117  %vc = and <vscale x 4 x i8> %va, %vb
118  ret <vscale x 4 x i8> %vc
119}
120
121define <vscale x 4 x i8> @vand_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
122; CHECK-LABEL: vand_vx_nxv4i8:
123; CHECK:       # %bb.0:
124; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
125; CHECK-NEXT:    vand.vx v8, v8, a0
126; CHECK-NEXT:    ret
127  %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
128  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
129  %vc = and <vscale x 4 x i8> %va, %splat
130  ret <vscale x 4 x i8> %vc
131}
132
133define <vscale x 4 x i8> @vand_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
134; CHECK-LABEL: vand_vi_nxv4i8_0:
135; CHECK:       # %bb.0:
136; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
137; CHECK-NEXT:    vand.vi v8, v8, -10
138; CHECK-NEXT:    ret
139  %vc = and <vscale x 4 x i8> %va, splat (i8 -10)
140  ret <vscale x 4 x i8> %vc
141}
142
143define <vscale x 4 x i8> @vand_vi_nxv4i8_1(<vscale x 4 x i8> %va) {
144; CHECK-LABEL: vand_vi_nxv4i8_1:
145; CHECK:       # %bb.0:
146; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
147; CHECK-NEXT:    vand.vi v8, v8, 8
148; CHECK-NEXT:    ret
149  %vc = and <vscale x 4 x i8> %va, splat (i8 8)
150  ret <vscale x 4 x i8> %vc
151}
152
153define <vscale x 4 x i8> @vand_vi_nxv4i8_2(<vscale x 4 x i8> %va) {
154; CHECK-LABEL: vand_vi_nxv4i8_2:
155; CHECK:       # %bb.0:
156; CHECK-NEXT:    li a0, 16
157; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma
158; CHECK-NEXT:    vand.vx v8, v8, a0
159; CHECK-NEXT:    ret
160  %vc = and <vscale x 4 x i8> %va, splat (i8 16)
161  ret <vscale x 4 x i8> %vc
162}
163
164define <vscale x 8 x i8> @vand_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
165; CHECK-LABEL: vand_vv_nxv8i8:
166; CHECK:       # %bb.0:
167; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
168; CHECK-NEXT:    vand.vv v8, v8, v9
169; CHECK-NEXT:    ret
170  %vc = and <vscale x 8 x i8> %va, %vb
171  ret <vscale x 8 x i8> %vc
172}
173
174define <vscale x 8 x i8> @vand_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
175; CHECK-LABEL: vand_vx_nxv8i8:
176; CHECK:       # %bb.0:
177; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
178; CHECK-NEXT:    vand.vx v8, v8, a0
179; CHECK-NEXT:    ret
180  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
181  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
182  %vc = and <vscale x 8 x i8> %va, %splat
183  ret <vscale x 8 x i8> %vc
184}
185
186define <vscale x 8 x i8> @vand_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
187; CHECK-LABEL: vand_vi_nxv8i8_0:
188; CHECK:       # %bb.0:
189; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
190; CHECK-NEXT:    vand.vi v8, v8, -10
191; CHECK-NEXT:    ret
192  %vc = and <vscale x 8 x i8> %va, splat (i8 -10)
193  ret <vscale x 8 x i8> %vc
194}
195
196define <vscale x 8 x i8> @vand_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
197; CHECK-LABEL: vand_vi_nxv8i8_1:
198; CHECK:       # %bb.0:
199; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
200; CHECK-NEXT:    vand.vi v8, v8, 8
201; CHECK-NEXT:    ret
202  %vc = and <vscale x 8 x i8> %va, splat (i8 8)
203  ret <vscale x 8 x i8> %vc
204}
205
206define <vscale x 8 x i8> @vand_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
207; CHECK-LABEL: vand_vi_nxv8i8_2:
208; CHECK:       # %bb.0:
209; CHECK-NEXT:    li a0, 16
210; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
211; CHECK-NEXT:    vand.vx v8, v8, a0
212; CHECK-NEXT:    ret
213  %vc = and <vscale x 8 x i8> %va, splat (i8 16)
214  ret <vscale x 8 x i8> %vc
215}
216
217define <vscale x 16 x i8> @vand_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
218; CHECK-LABEL: vand_vv_nxv16i8:
219; CHECK:       # %bb.0:
220; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
221; CHECK-NEXT:    vand.vv v8, v8, v10
222; CHECK-NEXT:    ret
223  %vc = and <vscale x 16 x i8> %va, %vb
224  ret <vscale x 16 x i8> %vc
225}
226
227define <vscale x 16 x i8> @vand_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
228; CHECK-LABEL: vand_vx_nxv16i8:
229; CHECK:       # %bb.0:
230; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
231; CHECK-NEXT:    vand.vx v8, v8, a0
232; CHECK-NEXT:    ret
233  %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
234  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
235  %vc = and <vscale x 16 x i8> %va, %splat
236  ret <vscale x 16 x i8> %vc
237}
238
239define <vscale x 16 x i8> @vand_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
240; CHECK-LABEL: vand_vi_nxv16i8_0:
241; CHECK:       # %bb.0:
242; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
243; CHECK-NEXT:    vand.vi v8, v8, -10
244; CHECK-NEXT:    ret
245  %vc = and <vscale x 16 x i8> %va, splat (i8 -10)
246  ret <vscale x 16 x i8> %vc
247}
248
249define <vscale x 16 x i8> @vand_vi_nxv16i8_1(<vscale x 16 x i8> %va) {
250; CHECK-LABEL: vand_vi_nxv16i8_1:
251; CHECK:       # %bb.0:
252; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
253; CHECK-NEXT:    vand.vi v8, v8, 8
254; CHECK-NEXT:    ret
255  %vc = and <vscale x 16 x i8> %va, splat (i8 8)
256  ret <vscale x 16 x i8> %vc
257}
258
259define <vscale x 16 x i8> @vand_vi_nxv16i8_2(<vscale x 16 x i8> %va) {
260; CHECK-LABEL: vand_vi_nxv16i8_2:
261; CHECK:       # %bb.0:
262; CHECK-NEXT:    li a0, 16
263; CHECK-NEXT:    vsetvli a1, zero, e8, m2, ta, ma
264; CHECK-NEXT:    vand.vx v8, v8, a0
265; CHECK-NEXT:    ret
266  %vc = and <vscale x 16 x i8> %va, splat (i8 16)
267  ret <vscale x 16 x i8> %vc
268}
269
270define <vscale x 32 x i8> @vand_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
271; CHECK-LABEL: vand_vv_nxv32i8:
272; CHECK:       # %bb.0:
273; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
274; CHECK-NEXT:    vand.vv v8, v8, v12
275; CHECK-NEXT:    ret
276  %vc = and <vscale x 32 x i8> %va, %vb
277  ret <vscale x 32 x i8> %vc
278}
279
280define <vscale x 32 x i8> @vand_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
281; CHECK-LABEL: vand_vx_nxv32i8:
282; CHECK:       # %bb.0:
283; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
284; CHECK-NEXT:    vand.vx v8, v8, a0
285; CHECK-NEXT:    ret
286  %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
287  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
288  %vc = and <vscale x 32 x i8> %va, %splat
289  ret <vscale x 32 x i8> %vc
290}
291
292define <vscale x 32 x i8> @vand_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
293; CHECK-LABEL: vand_vi_nxv32i8_0:
294; CHECK:       # %bb.0:
295; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
296; CHECK-NEXT:    vand.vi v8, v8, -10
297; CHECK-NEXT:    ret
298  %vc = and <vscale x 32 x i8> %va, splat (i8 -10)
299  ret <vscale x 32 x i8> %vc
300}
301
302define <vscale x 32 x i8> @vand_vi_nxv32i8_1(<vscale x 32 x i8> %va) {
303; CHECK-LABEL: vand_vi_nxv32i8_1:
304; CHECK:       # %bb.0:
305; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
306; CHECK-NEXT:    vand.vi v8, v8, 8
307; CHECK-NEXT:    ret
308  %vc = and <vscale x 32 x i8> %va, splat (i8 8)
309  ret <vscale x 32 x i8> %vc
310}
311
312define <vscale x 32 x i8> @vand_vi_nxv32i8_2(<vscale x 32 x i8> %va) {
313; CHECK-LABEL: vand_vi_nxv32i8_2:
314; CHECK:       # %bb.0:
315; CHECK-NEXT:    li a0, 16
316; CHECK-NEXT:    vsetvli a1, zero, e8, m4, ta, ma
317; CHECK-NEXT:    vand.vx v8, v8, a0
318; CHECK-NEXT:    ret
319  %vc = and <vscale x 32 x i8> %va, splat (i8 16)
320  ret <vscale x 32 x i8> %vc
321}
322
323define <vscale x 64 x i8> @vand_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {
324; CHECK-LABEL: vand_vv_nxv64i8:
325; CHECK:       # %bb.0:
326; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
327; CHECK-NEXT:    vand.vv v8, v8, v16
328; CHECK-NEXT:    ret
329  %vc = and <vscale x 64 x i8> %va, %vb
330  ret <vscale x 64 x i8> %vc
331}
332
333define <vscale x 64 x i8> @vand_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
334; CHECK-LABEL: vand_vx_nxv64i8:
335; CHECK:       # %bb.0:
336; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
337; CHECK-NEXT:    vand.vx v8, v8, a0
338; CHECK-NEXT:    ret
339  %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
340  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
341  %vc = and <vscale x 64 x i8> %va, %splat
342  ret <vscale x 64 x i8> %vc
343}
344
345define <vscale x 64 x i8> @vand_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
346; CHECK-LABEL: vand_vi_nxv64i8_0:
347; CHECK:       # %bb.0:
348; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
349; CHECK-NEXT:    vand.vi v8, v8, -10
350; CHECK-NEXT:    ret
351  %vc = and <vscale x 64 x i8> %va, splat (i8 -10)
352  ret <vscale x 64 x i8> %vc
353}
354
355define <vscale x 64 x i8> @vand_vi_nxv64i8_1(<vscale x 64 x i8> %va) {
356; CHECK-LABEL: vand_vi_nxv64i8_1:
357; CHECK:       # %bb.0:
358; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
359; CHECK-NEXT:    vand.vi v8, v8, 8
360; CHECK-NEXT:    ret
361  %vc = and <vscale x 64 x i8> %va, splat (i8 8)
362  ret <vscale x 64 x i8> %vc
363}
364
365define <vscale x 64 x i8> @vand_vi_nxv64i8_2(<vscale x 64 x i8> %va) {
366; CHECK-LABEL: vand_vi_nxv64i8_2:
367; CHECK:       # %bb.0:
368; CHECK-NEXT:    li a0, 16
369; CHECK-NEXT:    vsetvli a1, zero, e8, m8, ta, ma
370; CHECK-NEXT:    vand.vx v8, v8, a0
371; CHECK-NEXT:    ret
372  %vc = and <vscale x 64 x i8> %va, splat (i8 16)
373  ret <vscale x 64 x i8> %vc
374}
375
376define <vscale x 1 x i16> @vand_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
377; CHECK-LABEL: vand_vv_nxv1i16:
378; CHECK:       # %bb.0:
379; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
380; CHECK-NEXT:    vand.vv v8, v8, v9
381; CHECK-NEXT:    ret
382  %vc = and <vscale x 1 x i16> %va, %vb
383  ret <vscale x 1 x i16> %vc
384}
385
386define <vscale x 1 x i16> @vand_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
387; CHECK-LABEL: vand_vx_nxv1i16:
388; CHECK:       # %bb.0:
389; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
390; CHECK-NEXT:    vand.vx v8, v8, a0
391; CHECK-NEXT:    ret
392  %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
393  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
394  %vc = and <vscale x 1 x i16> %va, %splat
395  ret <vscale x 1 x i16> %vc
396}
397
398define <vscale x 1 x i16> @vand_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
399; CHECK-LABEL: vand_vi_nxv1i16_0:
400; CHECK:       # %bb.0:
401; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
402; CHECK-NEXT:    vand.vi v8, v8, -10
403; CHECK-NEXT:    ret
404  %vc = and <vscale x 1 x i16> %va, splat (i16 -10)
405  ret <vscale x 1 x i16> %vc
406}
407
408define <vscale x 1 x i16> @vand_vi_nxv1i16_1(<vscale x 1 x i16> %va) {
409; CHECK-LABEL: vand_vi_nxv1i16_1:
410; CHECK:       # %bb.0:
411; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
412; CHECK-NEXT:    vand.vi v8, v8, 8
413; CHECK-NEXT:    ret
414  %vc = and <vscale x 1 x i16> %va, splat (i16 8)
415  ret <vscale x 1 x i16> %vc
416}
417
418define <vscale x 1 x i16> @vand_vi_nxv1i16_2(<vscale x 1 x i16> %va) {
419; CHECK-LABEL: vand_vi_nxv1i16_2:
420; CHECK:       # %bb.0:
421; CHECK-NEXT:    li a0, 16
422; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
423; CHECK-NEXT:    vand.vx v8, v8, a0
424; CHECK-NEXT:    ret
425  %vc = and <vscale x 1 x i16> %va, splat (i16 16)
426  ret <vscale x 1 x i16> %vc
427}
428
429define <vscale x 2 x i16> @vand_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
430; CHECK-LABEL: vand_vv_nxv2i16:
431; CHECK:       # %bb.0:
432; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
433; CHECK-NEXT:    vand.vv v8, v8, v9
434; CHECK-NEXT:    ret
435  %vc = and <vscale x 2 x i16> %va, %vb
436  ret <vscale x 2 x i16> %vc
437}
438
439define <vscale x 2 x i16> @vand_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
440; CHECK-LABEL: vand_vx_nxv2i16:
441; CHECK:       # %bb.0:
442; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
443; CHECK-NEXT:    vand.vx v8, v8, a0
444; CHECK-NEXT:    ret
445  %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
446  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
447  %vc = and <vscale x 2 x i16> %va, %splat
448  ret <vscale x 2 x i16> %vc
449}
450
451define <vscale x 2 x i16> @vand_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
452; CHECK-LABEL: vand_vi_nxv2i16_0:
453; CHECK:       # %bb.0:
454; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
455; CHECK-NEXT:    vand.vi v8, v8, -10
456; CHECK-NEXT:    ret
457  %vc = and <vscale x 2 x i16> %va, splat (i16 -10)
458  ret <vscale x 2 x i16> %vc
459}
460
461define <vscale x 2 x i16> @vand_vi_nxv2i16_1(<vscale x 2 x i16> %va) {
462; CHECK-LABEL: vand_vi_nxv2i16_1:
463; CHECK:       # %bb.0:
464; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
465; CHECK-NEXT:    vand.vi v8, v8, 8
466; CHECK-NEXT:    ret
467  %vc = and <vscale x 2 x i16> %va, splat (i16 8)
468  ret <vscale x 2 x i16> %vc
469}
470
471define <vscale x 2 x i16> @vand_vi_nxv2i16_2(<vscale x 2 x i16> %va) {
472; CHECK-LABEL: vand_vi_nxv2i16_2:
473; CHECK:       # %bb.0:
474; CHECK-NEXT:    li a0, 16
475; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
476; CHECK-NEXT:    vand.vx v8, v8, a0
477; CHECK-NEXT:    ret
478  %vc = and <vscale x 2 x i16> %va, splat (i16 16)
479  ret <vscale x 2 x i16> %vc
480}
481
482define <vscale x 4 x i16> @vand_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
483; CHECK-LABEL: vand_vv_nxv4i16:
484; CHECK:       # %bb.0:
485; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
486; CHECK-NEXT:    vand.vv v8, v8, v9
487; CHECK-NEXT:    ret
488  %vc = and <vscale x 4 x i16> %va, %vb
489  ret <vscale x 4 x i16> %vc
490}
491
492define <vscale x 4 x i16> @vand_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
493; CHECK-LABEL: vand_vx_nxv4i16:
494; CHECK:       # %bb.0:
495; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
496; CHECK-NEXT:    vand.vx v8, v8, a0
497; CHECK-NEXT:    ret
498  %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
499  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
500  %vc = and <vscale x 4 x i16> %va, %splat
501  ret <vscale x 4 x i16> %vc
502}
503
504define <vscale x 4 x i16> @vand_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
505; CHECK-LABEL: vand_vi_nxv4i16_0:
506; CHECK:       # %bb.0:
507; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
508; CHECK-NEXT:    vand.vi v8, v8, -10
509; CHECK-NEXT:    ret
510  %vc = and <vscale x 4 x i16> %va, splat (i16 -10)
511  ret <vscale x 4 x i16> %vc
512}
513
514define <vscale x 4 x i16> @vand_vi_nxv4i16_1(<vscale x 4 x i16> %va) {
515; CHECK-LABEL: vand_vi_nxv4i16_1:
516; CHECK:       # %bb.0:
517; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
518; CHECK-NEXT:    vand.vi v8, v8, 8
519; CHECK-NEXT:    ret
520  %vc = and <vscale x 4 x i16> %va, splat (i16 8)
521  ret <vscale x 4 x i16> %vc
522}
523
524define <vscale x 4 x i16> @vand_vi_nxv4i16_2(<vscale x 4 x i16> %va) {
525; CHECK-LABEL: vand_vi_nxv4i16_2:
526; CHECK:       # %bb.0:
527; CHECK-NEXT:    li a0, 16
528; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
529; CHECK-NEXT:    vand.vx v8, v8, a0
530; CHECK-NEXT:    ret
531  %vc = and <vscale x 4 x i16> %va, splat (i16 16)
532  ret <vscale x 4 x i16> %vc
533}
534
535define <vscale x 8 x i16> @vand_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
536; CHECK-LABEL: vand_vv_nxv8i16:
537; CHECK:       # %bb.0:
538; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
539; CHECK-NEXT:    vand.vv v8, v8, v10
540; CHECK-NEXT:    ret
541  %vc = and <vscale x 8 x i16> %va, %vb
542  ret <vscale x 8 x i16> %vc
543}
544
545define <vscale x 8 x i16> @vand_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
546; CHECK-LABEL: vand_vx_nxv8i16:
547; CHECK:       # %bb.0:
548; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
549; CHECK-NEXT:    vand.vx v8, v8, a0
550; CHECK-NEXT:    ret
551  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
552  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
553  %vc = and <vscale x 8 x i16> %va, %splat
554  ret <vscale x 8 x i16> %vc
555}
556
557define <vscale x 8 x i16> @vand_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
558; CHECK-LABEL: vand_vi_nxv8i16_0:
559; CHECK:       # %bb.0:
560; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
561; CHECK-NEXT:    vand.vi v8, v8, -10
562; CHECK-NEXT:    ret
563  %vc = and <vscale x 8 x i16> %va, splat (i16 -10)
564  ret <vscale x 8 x i16> %vc
565}
566
567define <vscale x 8 x i16> @vand_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
568; CHECK-LABEL: vand_vi_nxv8i16_1:
569; CHECK:       # %bb.0:
570; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
571; CHECK-NEXT:    vand.vi v8, v8, 8
572; CHECK-NEXT:    ret
573  %vc = and <vscale x 8 x i16> %va, splat (i16 8)
574  ret <vscale x 8 x i16> %vc
575}
576
577define <vscale x 8 x i16> @vand_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
578; CHECK-LABEL: vand_vi_nxv8i16_2:
579; CHECK:       # %bb.0:
580; CHECK-NEXT:    li a0, 16
581; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
582; CHECK-NEXT:    vand.vx v8, v8, a0
583; CHECK-NEXT:    ret
584  %vc = and <vscale x 8 x i16> %va, splat (i16 16)
585  ret <vscale x 8 x i16> %vc
586}
587
588define <vscale x 16 x i16> @vand_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
589; CHECK-LABEL: vand_vv_nxv16i16:
590; CHECK:       # %bb.0:
591; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
592; CHECK-NEXT:    vand.vv v8, v8, v12
593; CHECK-NEXT:    ret
594  %vc = and <vscale x 16 x i16> %va, %vb
595  ret <vscale x 16 x i16> %vc
596}
597
598define <vscale x 16 x i16> @vand_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
599; CHECK-LABEL: vand_vx_nxv16i16:
600; CHECK:       # %bb.0:
601; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
602; CHECK-NEXT:    vand.vx v8, v8, a0
603; CHECK-NEXT:    ret
604  %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
605  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
606  %vc = and <vscale x 16 x i16> %va, %splat
607  ret <vscale x 16 x i16> %vc
608}
609
610define <vscale x 16 x i16> @vand_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
611; CHECK-LABEL: vand_vi_nxv16i16_0:
612; CHECK:       # %bb.0:
613; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
614; CHECK-NEXT:    vand.vi v8, v8, -10
615; CHECK-NEXT:    ret
616  %vc = and <vscale x 16 x i16> %va, splat (i16 -10)
617  ret <vscale x 16 x i16> %vc
618}
619
620define <vscale x 16 x i16> @vand_vi_nxv16i16_1(<vscale x 16 x i16> %va) {
621; CHECK-LABEL: vand_vi_nxv16i16_1:
622; CHECK:       # %bb.0:
623; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
624; CHECK-NEXT:    vand.vi v8, v8, 8
625; CHECK-NEXT:    ret
626  %vc = and <vscale x 16 x i16> %va, splat (i16 8)
627  ret <vscale x 16 x i16> %vc
628}
629
630define <vscale x 16 x i16> @vand_vi_nxv16i16_2(<vscale x 16 x i16> %va) {
631; CHECK-LABEL: vand_vi_nxv16i16_2:
632; CHECK:       # %bb.0:
633; CHECK-NEXT:    li a0, 16
634; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
635; CHECK-NEXT:    vand.vx v8, v8, a0
636; CHECK-NEXT:    ret
637  %vc = and <vscale x 16 x i16> %va, splat (i16 16)
638  ret <vscale x 16 x i16> %vc
639}
640
641define <vscale x 32 x i16> @vand_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {
642; CHECK-LABEL: vand_vv_nxv32i16:
643; CHECK:       # %bb.0:
644; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
645; CHECK-NEXT:    vand.vv v8, v8, v16
646; CHECK-NEXT:    ret
647  %vc = and <vscale x 32 x i16> %va, %vb
648  ret <vscale x 32 x i16> %vc
649}
650
651define <vscale x 32 x i16> @vand_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
652; CHECK-LABEL: vand_vx_nxv32i16:
653; CHECK:       # %bb.0:
654; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
655; CHECK-NEXT:    vand.vx v8, v8, a0
656; CHECK-NEXT:    ret
657  %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
658  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
659  %vc = and <vscale x 32 x i16> %va, %splat
660  ret <vscale x 32 x i16> %vc
661}
662
663define <vscale x 32 x i16> @vand_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
664; CHECK-LABEL: vand_vi_nxv32i16_0:
665; CHECK:       # %bb.0:
666; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
667; CHECK-NEXT:    vand.vi v8, v8, -10
668; CHECK-NEXT:    ret
669  %vc = and <vscale x 32 x i16> %va, splat (i16 -10)
670  ret <vscale x 32 x i16> %vc
671}
672
673define <vscale x 32 x i16> @vand_vi_nxv32i16_1(<vscale x 32 x i16> %va) {
674; CHECK-LABEL: vand_vi_nxv32i16_1:
675; CHECK:       # %bb.0:
676; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
677; CHECK-NEXT:    vand.vi v8, v8, 8
678; CHECK-NEXT:    ret
679  %vc = and <vscale x 32 x i16> %va, splat (i16 8)
680  ret <vscale x 32 x i16> %vc
681}
682
683define <vscale x 32 x i16> @vand_vi_nxv32i16_2(<vscale x 32 x i16> %va) {
684; CHECK-LABEL: vand_vi_nxv32i16_2:
685; CHECK:       # %bb.0:
686; CHECK-NEXT:    li a0, 16
687; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
688; CHECK-NEXT:    vand.vx v8, v8, a0
689; CHECK-NEXT:    ret
690  %vc = and <vscale x 32 x i16> %va, splat (i16 16)
691  ret <vscale x 32 x i16> %vc
692}
693
694define <vscale x 1 x i32> @vand_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
695; CHECK-LABEL: vand_vv_nxv1i32:
696; CHECK:       # %bb.0:
697; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
698; CHECK-NEXT:    vand.vv v8, v8, v9
699; CHECK-NEXT:    ret
700  %vc = and <vscale x 1 x i32> %va, %vb
701  ret <vscale x 1 x i32> %vc
702}
703
704define <vscale x 1 x i32> @vand_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
705; CHECK-LABEL: vand_vx_nxv1i32:
706; CHECK:       # %bb.0:
707; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
708; CHECK-NEXT:    vand.vx v8, v8, a0
709; CHECK-NEXT:    ret
710  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
711  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
712  %vc = and <vscale x 1 x i32> %va, %splat
713  ret <vscale x 1 x i32> %vc
714}
715
716define <vscale x 1 x i32> @vand_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
717; CHECK-LABEL: vand_vi_nxv1i32_0:
718; CHECK:       # %bb.0:
719; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
720; CHECK-NEXT:    vand.vi v8, v8, -10
721; CHECK-NEXT:    ret
722  %vc = and <vscale x 1 x i32> %va, splat (i32 -10)
723  ret <vscale x 1 x i32> %vc
724}
725
726define <vscale x 1 x i32> @vand_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
727; CHECK-LABEL: vand_vi_nxv1i32_1:
728; CHECK:       # %bb.0:
729; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
730; CHECK-NEXT:    vand.vi v8, v8, 8
731; CHECK-NEXT:    ret
732  %vc = and <vscale x 1 x i32> %va, splat (i32 8)
733  ret <vscale x 1 x i32> %vc
734}
735
736define <vscale x 1 x i32> @vand_vi_nxv1i32_2(<vscale x 1 x i32> %va) {
737; CHECK-LABEL: vand_vi_nxv1i32_2:
738; CHECK:       # %bb.0:
739; CHECK-NEXT:    li a0, 16
740; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
741; CHECK-NEXT:    vand.vx v8, v8, a0
742; CHECK-NEXT:    ret
743  %vc = and <vscale x 1 x i32> %va, splat (i32 16)
744  ret <vscale x 1 x i32> %vc
745}
746
747define <vscale x 2 x i32> @vand_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
748; CHECK-LABEL: vand_vv_nxv2i32:
749; CHECK:       # %bb.0:
750; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
751; CHECK-NEXT:    vand.vv v8, v8, v9
752; CHECK-NEXT:    ret
753  %vc = and <vscale x 2 x i32> %va, %vb
754  ret <vscale x 2 x i32> %vc
755}
756
757define <vscale x 2 x i32> @vand_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
758; CHECK-LABEL: vand_vx_nxv2i32:
759; CHECK:       # %bb.0:
760; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
761; CHECK-NEXT:    vand.vx v8, v8, a0
762; CHECK-NEXT:    ret
763  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
764  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
765  %vc = and <vscale x 2 x i32> %va, %splat
766  ret <vscale x 2 x i32> %vc
767}
768
769define <vscale x 2 x i32> @vand_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
770; CHECK-LABEL: vand_vi_nxv2i32_0:
771; CHECK:       # %bb.0:
772; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
773; CHECK-NEXT:    vand.vi v8, v8, -10
774; CHECK-NEXT:    ret
775  %vc = and <vscale x 2 x i32> %va, splat (i32 -10)
776  ret <vscale x 2 x i32> %vc
777}
778
779define <vscale x 2 x i32> @vand_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
780; CHECK-LABEL: vand_vi_nxv2i32_1:
781; CHECK:       # %bb.0:
782; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
783; CHECK-NEXT:    vand.vi v8, v8, 8
784; CHECK-NEXT:    ret
785  %vc = and <vscale x 2 x i32> %va, splat (i32 8)
786  ret <vscale x 2 x i32> %vc
787}
788
789define <vscale x 2 x i32> @vand_vi_nxv2i32_2(<vscale x 2 x i32> %va) {
790; CHECK-LABEL: vand_vi_nxv2i32_2:
791; CHECK:       # %bb.0:
792; CHECK-NEXT:    li a0, 16
793; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
794; CHECK-NEXT:    vand.vx v8, v8, a0
795; CHECK-NEXT:    ret
796  %vc = and <vscale x 2 x i32> %va, splat (i32 16)
797  ret <vscale x 2 x i32> %vc
798}
799
800define <vscale x 4 x i32> @vand_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
801; CHECK-LABEL: vand_vv_nxv4i32:
802; CHECK:       # %bb.0:
803; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
804; CHECK-NEXT:    vand.vv v8, v8, v10
805; CHECK-NEXT:    ret
806  %vc = and <vscale x 4 x i32> %va, %vb
807  ret <vscale x 4 x i32> %vc
808}
809
810define <vscale x 4 x i32> @vand_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
811; CHECK-LABEL: vand_vx_nxv4i32:
812; CHECK:       # %bb.0:
813; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
814; CHECK-NEXT:    vand.vx v8, v8, a0
815; CHECK-NEXT:    ret
816  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
817  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
818  %vc = and <vscale x 4 x i32> %va, %splat
819  ret <vscale x 4 x i32> %vc
820}
821
822define <vscale x 4 x i32> @vand_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
823; CHECK-LABEL: vand_vi_nxv4i32_0:
824; CHECK:       # %bb.0:
825; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
826; CHECK-NEXT:    vand.vi v8, v8, -10
827; CHECK-NEXT:    ret
828  %vc = and <vscale x 4 x i32> %va, splat (i32 -10)
829  ret <vscale x 4 x i32> %vc
830}
831
832define <vscale x 4 x i32> @vand_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
833; CHECK-LABEL: vand_vi_nxv4i32_1:
834; CHECK:       # %bb.0:
835; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
836; CHECK-NEXT:    vand.vi v8, v8, 8
837; CHECK-NEXT:    ret
838  %vc = and <vscale x 4 x i32> %va, splat (i32 8)
839  ret <vscale x 4 x i32> %vc
840}
841
842define <vscale x 4 x i32> @vand_vi_nxv4i32_2(<vscale x 4 x i32> %va) {
843; CHECK-LABEL: vand_vi_nxv4i32_2:
844; CHECK:       # %bb.0:
845; CHECK-NEXT:    li a0, 16
846; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
847; CHECK-NEXT:    vand.vx v8, v8, a0
848; CHECK-NEXT:    ret
849  %vc = and <vscale x 4 x i32> %va, splat (i32 16)
850  ret <vscale x 4 x i32> %vc
851}
852
853define <vscale x 8 x i32> @vand_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
854; CHECK-LABEL: vand_vv_nxv8i32:
855; CHECK:       # %bb.0:
856; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
857; CHECK-NEXT:    vand.vv v8, v8, v12
858; CHECK-NEXT:    ret
859  %vc = and <vscale x 8 x i32> %va, %vb
860  ret <vscale x 8 x i32> %vc
861}
862
863define <vscale x 8 x i32> @vand_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
864; CHECK-LABEL: vand_vx_nxv8i32:
865; CHECK:       # %bb.0:
866; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
867; CHECK-NEXT:    vand.vx v8, v8, a0
868; CHECK-NEXT:    ret
869  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
870  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
871  %vc = and <vscale x 8 x i32> %va, %splat
872  ret <vscale x 8 x i32> %vc
873}
874
875define <vscale x 8 x i32> @vand_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
876; CHECK-LABEL: vand_vi_nxv8i32_0:
877; CHECK:       # %bb.0:
878; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
879; CHECK-NEXT:    vand.vi v8, v8, -10
880; CHECK-NEXT:    ret
881  %vc = and <vscale x 8 x i32> %va, splat (i32 -10)
882  ret <vscale x 8 x i32> %vc
883}
884
885define <vscale x 8 x i32> @vand_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
886; CHECK-LABEL: vand_vi_nxv8i32_1:
887; CHECK:       # %bb.0:
888; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
889; CHECK-NEXT:    vand.vi v8, v8, 8
890; CHECK-NEXT:    ret
891  %vc = and <vscale x 8 x i32> %va, splat (i32 8)
892  ret <vscale x 8 x i32> %vc
893}
894
895define <vscale x 8 x i32> @vand_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
896; CHECK-LABEL: vand_vi_nxv8i32_2:
897; CHECK:       # %bb.0:
898; CHECK-NEXT:    li a0, 16
899; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
900; CHECK-NEXT:    vand.vx v8, v8, a0
901; CHECK-NEXT:    ret
902  %vc = and <vscale x 8 x i32> %va, splat (i32 16)
903  ret <vscale x 8 x i32> %vc
904}
905
906define <vscale x 16 x i32> @vand_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {
907; CHECK-LABEL: vand_vv_nxv16i32:
908; CHECK:       # %bb.0:
909; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
910; CHECK-NEXT:    vand.vv v8, v8, v16
911; CHECK-NEXT:    ret
912  %vc = and <vscale x 16 x i32> %va, %vb
913  ret <vscale x 16 x i32> %vc
914}
915
916define <vscale x 16 x i32> @vand_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
917; CHECK-LABEL: vand_vx_nxv16i32:
918; CHECK:       # %bb.0:
919; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
920; CHECK-NEXT:    vand.vx v8, v8, a0
921; CHECK-NEXT:    ret
922  %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
923  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
924  %vc = and <vscale x 16 x i32> %va, %splat
925  ret <vscale x 16 x i32> %vc
926}
927
928define <vscale x 16 x i32> @vand_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
929; CHECK-LABEL: vand_vi_nxv16i32_0:
930; CHECK:       # %bb.0:
931; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
932; CHECK-NEXT:    vand.vi v8, v8, -10
933; CHECK-NEXT:    ret
934  %vc = and <vscale x 16 x i32> %va, splat (i32 -10)
935  ret <vscale x 16 x i32> %vc
936}
937
938define <vscale x 16 x i32> @vand_vi_nxv16i32_1(<vscale x 16 x i32> %va) {
939; CHECK-LABEL: vand_vi_nxv16i32_1:
940; CHECK:       # %bb.0:
941; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
942; CHECK-NEXT:    vand.vi v8, v8, 8
943; CHECK-NEXT:    ret
944  %vc = and <vscale x 16 x i32> %va, splat (i32 8)
945  ret <vscale x 16 x i32> %vc
946}
947
948define <vscale x 16 x i32> @vand_vi_nxv16i32_2(<vscale x 16 x i32> %va) {
949; CHECK-LABEL: vand_vi_nxv16i32_2:
950; CHECK:       # %bb.0:
951; CHECK-NEXT:    li a0, 16
952; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, ma
953; CHECK-NEXT:    vand.vx v8, v8, a0
954; CHECK-NEXT:    ret
955  %vc = and <vscale x 16 x i32> %va, splat (i32 16)
956  ret <vscale x 16 x i32> %vc
957}
958
959define <vscale x 1 x i64> @vand_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
960; CHECK-LABEL: vand_vv_nxv1i64:
961; CHECK:       # %bb.0:
962; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
963; CHECK-NEXT:    vand.vv v8, v8, v9
964; CHECK-NEXT:    ret
965  %vc = and <vscale x 1 x i64> %va, %vb
966  ret <vscale x 1 x i64> %vc
967}
968
969define <vscale x 1 x i64> @vand_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
970; RV32-LABEL: vand_vx_nxv1i64:
971; RV32:       # %bb.0:
972; RV32-NEXT:    addi sp, sp, -16
973; RV32-NEXT:    .cfi_def_cfa_offset 16
974; RV32-NEXT:    sw a0, 8(sp)
975; RV32-NEXT:    sw a1, 12(sp)
976; RV32-NEXT:    addi a0, sp, 8
977; RV32-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
978; RV32-NEXT:    vlse64.v v9, (a0), zero
979; RV32-NEXT:    vand.vv v8, v8, v9
980; RV32-NEXT:    addi sp, sp, 16
981; RV32-NEXT:    .cfi_def_cfa_offset 0
982; RV32-NEXT:    ret
983;
984; RV64-LABEL: vand_vx_nxv1i64:
985; RV64:       # %bb.0:
986; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
987; RV64-NEXT:    vand.vx v8, v8, a0
988; RV64-NEXT:    ret
989  %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
990  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
991  %vc = and <vscale x 1 x i64> %va, %splat
992  ret <vscale x 1 x i64> %vc
993}
994
995define <vscale x 1 x i64> @vand_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
996; CHECK-LABEL: vand_vi_nxv1i64_0:
997; CHECK:       # %bb.0:
998; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
999; CHECK-NEXT:    vand.vi v8, v8, -10
1000; CHECK-NEXT:    ret
1001  %vc = and <vscale x 1 x i64> %va, splat (i64 -10)
1002  ret <vscale x 1 x i64> %vc
1003}
1004
1005define <vscale x 1 x i64> @vand_vi_nxv1i64_1(<vscale x 1 x i64> %va) {
1006; CHECK-LABEL: vand_vi_nxv1i64_1:
1007; CHECK:       # %bb.0:
1008; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
1009; CHECK-NEXT:    vand.vi v8, v8, 8
1010; CHECK-NEXT:    ret
1011  %vc = and <vscale x 1 x i64> %va, splat (i64 8)
1012  ret <vscale x 1 x i64> %vc
1013}
1014
1015define <vscale x 1 x i64> @vand_vi_nxv1i64_2(<vscale x 1 x i64> %va) {
1016; CHECK-LABEL: vand_vi_nxv1i64_2:
1017; CHECK:       # %bb.0:
1018; CHECK-NEXT:    li a0, 16
1019; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, ma
1020; CHECK-NEXT:    vand.vx v8, v8, a0
1021; CHECK-NEXT:    ret
1022  %vc = and <vscale x 1 x i64> %va, splat (i64 16)
1023  ret <vscale x 1 x i64> %vc
1024}
1025
1026define <vscale x 2 x i64> @vand_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
1027; CHECK-LABEL: vand_vv_nxv2i64:
1028; CHECK:       # %bb.0:
1029; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
1030; CHECK-NEXT:    vand.vv v8, v8, v10
1031; CHECK-NEXT:    ret
1032  %vc = and <vscale x 2 x i64> %va, %vb
1033  ret <vscale x 2 x i64> %vc
1034}
1035
1036define <vscale x 2 x i64> @vand_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
1037; RV32-LABEL: vand_vx_nxv2i64:
1038; RV32:       # %bb.0:
1039; RV32-NEXT:    addi sp, sp, -16
1040; RV32-NEXT:    .cfi_def_cfa_offset 16
1041; RV32-NEXT:    sw a0, 8(sp)
1042; RV32-NEXT:    sw a1, 12(sp)
1043; RV32-NEXT:    addi a0, sp, 8
1044; RV32-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
1045; RV32-NEXT:    vlse64.v v10, (a0), zero
1046; RV32-NEXT:    vand.vv v8, v8, v10
1047; RV32-NEXT:    addi sp, sp, 16
1048; RV32-NEXT:    .cfi_def_cfa_offset 0
1049; RV32-NEXT:    ret
1050;
1051; RV64-LABEL: vand_vx_nxv2i64:
1052; RV64:       # %bb.0:
1053; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
1054; RV64-NEXT:    vand.vx v8, v8, a0
1055; RV64-NEXT:    ret
1056  %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
1057  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
1058  %vc = and <vscale x 2 x i64> %va, %splat
1059  ret <vscale x 2 x i64> %vc
1060}
1061
1062define <vscale x 2 x i64> @vand_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
1063; CHECK-LABEL: vand_vi_nxv2i64_0:
1064; CHECK:       # %bb.0:
1065; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
1066; CHECK-NEXT:    vand.vi v8, v8, -10
1067; CHECK-NEXT:    ret
1068  %vc = and <vscale x 2 x i64> %va, splat (i64 -10)
1069  ret <vscale x 2 x i64> %vc
1070}
1071
1072define <vscale x 2 x i64> @vand_vi_nxv2i64_1(<vscale x 2 x i64> %va) {
1073; CHECK-LABEL: vand_vi_nxv2i64_1:
1074; CHECK:       # %bb.0:
1075; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
1076; CHECK-NEXT:    vand.vi v8, v8, 8
1077; CHECK-NEXT:    ret
1078  %vc = and <vscale x 2 x i64> %va, splat (i64 8)
1079  ret <vscale x 2 x i64> %vc
1080}
1081
1082define <vscale x 2 x i64> @vand_vi_nxv2i64_2(<vscale x 2 x i64> %va) {
1083; CHECK-LABEL: vand_vi_nxv2i64_2:
1084; CHECK:       # %bb.0:
1085; CHECK-NEXT:    li a0, 16
1086; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, ma
1087; CHECK-NEXT:    vand.vx v8, v8, a0
1088; CHECK-NEXT:    ret
1089  %vc = and <vscale x 2 x i64> %va, splat (i64 16)
1090  ret <vscale x 2 x i64> %vc
1091}
1092
1093define <vscale x 4 x i64> @vand_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
1094; CHECK-LABEL: vand_vv_nxv4i64:
1095; CHECK:       # %bb.0:
1096; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
1097; CHECK-NEXT:    vand.vv v8, v8, v12
1098; CHECK-NEXT:    ret
1099  %vc = and <vscale x 4 x i64> %va, %vb
1100  ret <vscale x 4 x i64> %vc
1101}
1102
1103define <vscale x 4 x i64> @vand_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
1104; RV32-LABEL: vand_vx_nxv4i64:
1105; RV32:       # %bb.0:
1106; RV32-NEXT:    addi sp, sp, -16
1107; RV32-NEXT:    .cfi_def_cfa_offset 16
1108; RV32-NEXT:    sw a0, 8(sp)
1109; RV32-NEXT:    sw a1, 12(sp)
1110; RV32-NEXT:    addi a0, sp, 8
1111; RV32-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
1112; RV32-NEXT:    vlse64.v v12, (a0), zero
1113; RV32-NEXT:    vand.vv v8, v8, v12
1114; RV32-NEXT:    addi sp, sp, 16
1115; RV32-NEXT:    .cfi_def_cfa_offset 0
1116; RV32-NEXT:    ret
1117;
1118; RV64-LABEL: vand_vx_nxv4i64:
1119; RV64:       # %bb.0:
1120; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
1121; RV64-NEXT:    vand.vx v8, v8, a0
1122; RV64-NEXT:    ret
1123  %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
1124  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
1125  %vc = and <vscale x 4 x i64> %va, %splat
1126  ret <vscale x 4 x i64> %vc
1127}
1128
1129define <vscale x 4 x i64> @vand_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
1130; CHECK-LABEL: vand_vi_nxv4i64_0:
1131; CHECK:       # %bb.0:
1132; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
1133; CHECK-NEXT:    vand.vi v8, v8, -10
1134; CHECK-NEXT:    ret
1135  %vc = and <vscale x 4 x i64> %va, splat (i64 -10)
1136  ret <vscale x 4 x i64> %vc
1137}
1138
1139define <vscale x 4 x i64> @vand_vi_nxv4i64_1(<vscale x 4 x i64> %va) {
1140; CHECK-LABEL: vand_vi_nxv4i64_1:
1141; CHECK:       # %bb.0:
1142; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
1143; CHECK-NEXT:    vand.vi v8, v8, 8
1144; CHECK-NEXT:    ret
1145  %vc = and <vscale x 4 x i64> %va, splat (i64 8)
1146  ret <vscale x 4 x i64> %vc
1147}
1148
1149define <vscale x 4 x i64> @vand_vi_nxv4i64_2(<vscale x 4 x i64> %va) {
1150; CHECK-LABEL: vand_vi_nxv4i64_2:
1151; CHECK:       # %bb.0:
1152; CHECK-NEXT:    li a0, 16
1153; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, ma
1154; CHECK-NEXT:    vand.vx v8, v8, a0
1155; CHECK-NEXT:    ret
1156  %vc = and <vscale x 4 x i64> %va, splat (i64 16)
1157  ret <vscale x 4 x i64> %vc
1158}
1159
1160define <vscale x 8 x i64> @vand_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
1161; CHECK-LABEL: vand_vv_nxv8i64:
1162; CHECK:       # %bb.0:
1163; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
1164; CHECK-NEXT:    vand.vv v8, v8, v16
1165; CHECK-NEXT:    ret
1166  %vc = and <vscale x 8 x i64> %va, %vb
1167  ret <vscale x 8 x i64> %vc
1168}
1169
1170define <vscale x 8 x i64> @vand_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
1171; RV32-LABEL: vand_vx_nxv8i64:
1172; RV32:       # %bb.0:
1173; RV32-NEXT:    addi sp, sp, -16
1174; RV32-NEXT:    .cfi_def_cfa_offset 16
1175; RV32-NEXT:    sw a0, 8(sp)
1176; RV32-NEXT:    sw a1, 12(sp)
1177; RV32-NEXT:    addi a0, sp, 8
1178; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1179; RV32-NEXT:    vlse64.v v16, (a0), zero
1180; RV32-NEXT:    vand.vv v8, v8, v16
1181; RV32-NEXT:    addi sp, sp, 16
1182; RV32-NEXT:    .cfi_def_cfa_offset 0
1183; RV32-NEXT:    ret
1184;
1185; RV64-LABEL: vand_vx_nxv8i64:
1186; RV64:       # %bb.0:
1187; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1188; RV64-NEXT:    vand.vx v8, v8, a0
1189; RV64-NEXT:    ret
1190  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
1191  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
1192  %vc = and <vscale x 8 x i64> %va, %splat
1193  ret <vscale x 8 x i64> %vc
1194}
1195
1196define <vscale x 8 x i64> @vand_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
1197; CHECK-LABEL: vand_vi_nxv8i64_0:
1198; CHECK:       # %bb.0:
1199; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
1200; CHECK-NEXT:    vand.vi v8, v8, -10
1201; CHECK-NEXT:    ret
1202  %vc = and <vscale x 8 x i64> %va, splat (i64 -10)
1203  ret <vscale x 8 x i64> %vc
1204}
1205
1206define <vscale x 8 x i64> @vand_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
1207; CHECK-LABEL: vand_vi_nxv8i64_1:
1208; CHECK:       # %bb.0:
1209; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
1210; CHECK-NEXT:    vand.vi v8, v8, 8
1211; CHECK-NEXT:    ret
1212  %vc = and <vscale x 8 x i64> %va, splat (i64 8)
1213  ret <vscale x 8 x i64> %vc
1214}
1215
1216define <vscale x 8 x i64> @vand_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
1217; CHECK-LABEL: vand_vi_nxv8i64_2:
1218; CHECK:       # %bb.0:
1219; CHECK-NEXT:    li a0, 16
1220; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1221; CHECK-NEXT:    vand.vx v8, v8, a0
1222; CHECK-NEXT:    ret
1223  %vc = and <vscale x 8 x i64> %va, splat (i64 16)
1224  ret <vscale x 8 x i64> %vc
1225}
1226
1227define <vscale x 8 x i64> @vand_xx_nxv8i64(i64 %a, i64 %b) nounwind {
1228; RV32-LABEL: vand_xx_nxv8i64:
1229; RV32:       # %bb.0:
1230; RV32-NEXT:    addi sp, sp, -16
1231; RV32-NEXT:    and a1, a1, a3
1232; RV32-NEXT:    and a0, a0, a2
1233; RV32-NEXT:    sw a0, 8(sp)
1234; RV32-NEXT:    sw a1, 12(sp)
1235; RV32-NEXT:    addi a0, sp, 8
1236; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1237; RV32-NEXT:    vlse64.v v8, (a0), zero
1238; RV32-NEXT:    addi sp, sp, 16
1239; RV32-NEXT:    ret
1240;
1241; RV64-LABEL: vand_xx_nxv8i64:
1242; RV64:       # %bb.0:
1243; RV64-NEXT:    and a0, a0, a1
1244; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
1245; RV64-NEXT:    vmv.v.x v8, a0
1246; RV64-NEXT:    ret
1247  %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
1248  %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
1249  %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
1250  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
1251  %v = and <vscale x 8 x i64> %splat1, %splat2
1252  ret <vscale x 8 x i64> %v
1253}
1254
1255define <vscale x 8 x i32> @vand_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
1256; CHECK-LABEL: vand_vv_mask_nxv8i32:
1257; CHECK:       # %bb.0:
1258; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1259; CHECK-NEXT:    vand.vv v8, v8, v12, v0.t
1260; CHECK-NEXT:    ret
1261  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> splat (i32 -1)
1262  %vc = and <vscale x 8 x i32> %va, %vs
1263  ret <vscale x 8 x i32> %vc
1264}
1265
1266define <vscale x 8 x i32> @vand_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
1267; CHECK-LABEL: vand_vx_mask_nxv8i32:
1268; CHECK:       # %bb.0:
1269; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1270; CHECK-NEXT:    vand.vx v8, v8, a0, v0.t
1271; CHECK-NEXT:    ret
1272  %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1273  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1274  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> splat (i32 -1)
1275  %vc = and <vscale x 8 x i32> %va, %vs
1276  ret <vscale x 8 x i32> %vc
1277}
1278
1279define <vscale x 8 x i32> @vand_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
1280; CHECK-LABEL: vand_vi_mask_nxv8i32:
1281; CHECK:       # %bb.0:
1282; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1283; CHECK-NEXT:    vand.vi v8, v8, 7, v0.t
1284; CHECK-NEXT:    ret
1285  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> splat (i32 7), <vscale x 8 x i32> splat (i32 -1)
1286  %vc = and <vscale x 8 x i32> %va, %vs
1287  ret <vscale x 8 x i32> %vc
1288}
1289