xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vaeskf1.ll (revision 09058654f68dd4cc5435f49502de33bac2b7f8fa) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvkned \
3; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvkned \
5; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
6
7declare <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i32(
8  <vscale x 4 x i32>,
9  <vscale x 4 x i32>,
10  iXLen,
11  iXLen)
12
13define <vscale x 4 x i32> @intrinsic_vaeskf1_vi_nxv4i32_i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {
14; CHECK-LABEL: intrinsic_vaeskf1_vi_nxv4i32_i32:
15; CHECK:       # %bb.0: # %entry
16; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
17; CHECK-NEXT:    vaeskf1.vi v8, v8, 2
18; CHECK-NEXT:    ret
19entry:
20  %a = call <vscale x 4 x i32> @llvm.riscv.vaeskf1.nxv4i32.i32(
21    <vscale x 4 x i32> undef,
22    <vscale x 4 x i32> %0,
23    iXLen 2,
24    iXLen %1)
25
26  ret <vscale x 4 x i32> %a
27}
28
29declare <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i32(
30  <vscale x 8 x i32>,
31  <vscale x 8 x i32>,
32  iXLen,
33  iXLen)
34
35define <vscale x 8 x i32> @intrinsic_vaeskf1_vi_nxv8i32_i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {
36; CHECK-LABEL: intrinsic_vaeskf1_vi_nxv8i32_i32:
37; CHECK:       # %bb.0: # %entry
38; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
39; CHECK-NEXT:    vaeskf1.vi v8, v8, 2
40; CHECK-NEXT:    ret
41entry:
42  %a = call <vscale x 8 x i32> @llvm.riscv.vaeskf1.nxv8i32.i32(
43    <vscale x 8 x i32> undef,
44    <vscale x 8 x i32> %0,
45    iXLen 2,
46    iXLen %1)
47
48  ret <vscale x 8 x i32> %a
49}
50
51declare <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i32(
52  <vscale x 16 x i32>,
53  <vscale x 16 x i32>,
54  iXLen,
55  iXLen)
56
57define <vscale x 16 x i32> @intrinsic_vaeskf1_vi_nxv16i32_i32(<vscale x 16 x i32> %0, iXLen %1) nounwind {
58; CHECK-LABEL: intrinsic_vaeskf1_vi_nxv16i32_i32:
59; CHECK:       # %bb.0: # %entry
60; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
61; CHECK-NEXT:    vaeskf1.vi v8, v8, 2
62; CHECK-NEXT:    ret
63entry:
64  %a = call <vscale x 16 x i32> @llvm.riscv.vaeskf1.nxv16i32.i32(
65    <vscale x 16 x i32> undef,
66    <vscale x 16 x i32> %0,
67    iXLen 2,
68    iXLen %1)
69
70  ret <vscale x 16 x i32> %a
71}
72