1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \ 3; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \ 5; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 6 7declare <vscale x 8 x i7> @llvm.vp.add.nxv8i7(<vscale x 8 x i7>, <vscale x 8 x i7>, <vscale x 8 x i1>, i32) 8 9define <vscale x 8 x i7> @vadd_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <vscale x 8 x i1> %mask, i32 zeroext %evl) { 10; CHECK-LABEL: vadd_vx_nxv8i7: 11; CHECK: # %bb.0: 12; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma 13; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 14; CHECK-NEXT: ret 15 %elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0 16 %vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer 17 %v = call <vscale x 8 x i7> @llvm.vp.add.nxv8i7(<vscale x 8 x i7> %a, <vscale x 8 x i7> %vb, <vscale x 8 x i1> %mask, i32 %evl) 18 ret <vscale x 8 x i7> %v 19} 20 21declare <vscale x 1 x i8> @llvm.vp.add.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i32) 22 23define <vscale x 1 x i8> @vadd_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { 24; CHECK-LABEL: vadd_vv_nxv1i8: 25; CHECK: # %bb.0: 26; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma 27; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t 28; CHECK-NEXT: ret 29 %v = call <vscale x 1 x i8> @llvm.vp.add.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 %evl) 30 ret <vscale x 1 x i8> %v 31} 32 33define <vscale x 1 x i8> @vadd_vv_nxv1i8_unmasked(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, i32 zeroext %evl) { 34; CHECK-LABEL: vadd_vv_nxv1i8_unmasked: 35; CHECK: # %bb.0: 36; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma 37; CHECK-NEXT: vadd.vv v8, v8, v9 38; CHECK-NEXT: ret 39 %v = call <vscale x 1 x i8> @llvm.vp.add.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl) 40 ret <vscale x 1 x i8> %v 41} 42 43define <vscale x 1 x i8> @vadd_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { 44; CHECK-LABEL: vadd_vx_nxv1i8: 45; CHECK: # %bb.0: 46; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma 47; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 48; CHECK-NEXT: ret 49 %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0 50 %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer 51 %v = call <vscale x 1 x i8> @llvm.vp.add.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> %m, i32 %evl) 52 ret <vscale x 1 x i8> %v 53} 54 55define <vscale x 1 x i8> @vadd_vx_nxv1i8_commute(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { 56; CHECK-LABEL: vadd_vx_nxv1i8_commute: 57; CHECK: # %bb.0: 58; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma 59; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 60; CHECK-NEXT: ret 61 %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0 62 %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer 63 %v = call <vscale x 1 x i8> @llvm.vp.add.nxv1i8(<vscale x 1 x i8> %vb, <vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl) 64 ret <vscale x 1 x i8> %v 65} 66 67define <vscale x 1 x i8> @vadd_vx_nxv1i8_unmasked(<vscale x 1 x i8> %va, i8 %b, i32 zeroext %evl) { 68; CHECK-LABEL: vadd_vx_nxv1i8_unmasked: 69; CHECK: # %bb.0: 70; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma 71; CHECK-NEXT: vadd.vx v8, v8, a0 72; CHECK-NEXT: ret 73 %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0 74 %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer 75 %v = call <vscale x 1 x i8> @llvm.vp.add.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl) 76 ret <vscale x 1 x i8> %v 77} 78 79define <vscale x 1 x i8> @vadd_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { 80; CHECK-LABEL: vadd_vi_nxv1i8: 81; CHECK: # %bb.0: 82; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma 83; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 84; CHECK-NEXT: ret 85 %v = call <vscale x 1 x i8> @llvm.vp.add.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> %m, i32 %evl) 86 ret <vscale x 1 x i8> %v 87} 88 89define <vscale x 1 x i8> @vadd_vi_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) { 90; CHECK-LABEL: vadd_vi_nxv1i8_unmasked: 91; CHECK: # %bb.0: 92; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma 93; CHECK-NEXT: vadd.vi v8, v8, -1 94; CHECK-NEXT: ret 95 %v = call <vscale x 1 x i8> @llvm.vp.add.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl) 96 ret <vscale x 1 x i8> %v 97} 98 99declare <vscale x 2 x i8> @llvm.vp.add.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i32) 100 101define <vscale x 2 x i8> @vadd_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { 102; CHECK-LABEL: vadd_vv_nxv2i8: 103; CHECK: # %bb.0: 104; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma 105; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t 106; CHECK-NEXT: ret 107 %v = call <vscale x 2 x i8> @llvm.vp.add.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 %evl) 108 ret <vscale x 2 x i8> %v 109} 110 111define <vscale x 2 x i8> @vadd_vv_nxv2i8_unmasked(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, i32 zeroext %evl) { 112; CHECK-LABEL: vadd_vv_nxv2i8_unmasked: 113; CHECK: # %bb.0: 114; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma 115; CHECK-NEXT: vadd.vv v8, v8, v9 116; CHECK-NEXT: ret 117 %v = call <vscale x 2 x i8> @llvm.vp.add.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl) 118 ret <vscale x 2 x i8> %v 119} 120 121define <vscale x 2 x i8> @vadd_vx_nxv2i8(<vscale x 2 x i8> %va, i8 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { 122; CHECK-LABEL: vadd_vx_nxv2i8: 123; CHECK: # %bb.0: 124; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma 125; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 126; CHECK-NEXT: ret 127 %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0 128 %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer 129 %v = call <vscale x 2 x i8> @llvm.vp.add.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> %m, i32 %evl) 130 ret <vscale x 2 x i8> %v 131} 132 133define <vscale x 2 x i8> @vadd_vx_nxv2i8_unmasked(<vscale x 2 x i8> %va, i8 %b, i32 zeroext %evl) { 134; CHECK-LABEL: vadd_vx_nxv2i8_unmasked: 135; CHECK: # %bb.0: 136; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma 137; CHECK-NEXT: vadd.vx v8, v8, a0 138; CHECK-NEXT: ret 139 %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0 140 %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer 141 %v = call <vscale x 2 x i8> @llvm.vp.add.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl) 142 ret <vscale x 2 x i8> %v 143} 144 145define <vscale x 2 x i8> @vadd_vi_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { 146; CHECK-LABEL: vadd_vi_nxv2i8: 147; CHECK: # %bb.0: 148; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma 149; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 150; CHECK-NEXT: ret 151 %v = call <vscale x 2 x i8> @llvm.vp.add.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> %m, i32 %evl) 152 ret <vscale x 2 x i8> %v 153} 154 155define <vscale x 2 x i8> @vadd_vi_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) { 156; CHECK-LABEL: vadd_vi_nxv2i8_unmasked: 157; CHECK: # %bb.0: 158; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma 159; CHECK-NEXT: vadd.vi v8, v8, -1 160; CHECK-NEXT: ret 161 %v = call <vscale x 2 x i8> @llvm.vp.add.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl) 162 ret <vscale x 2 x i8> %v 163} 164 165declare <vscale x 3 x i8> @llvm.vp.add.nxv3i8(<vscale x 3 x i8>, <vscale x 3 x i8>, <vscale x 3 x i1>, i32) 166 167define <vscale x 3 x i8> @vadd_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 zeroext %evl) { 168; CHECK-LABEL: vadd_vv_nxv3i8: 169; CHECK: # %bb.0: 170; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 171; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t 172; CHECK-NEXT: ret 173 %v = call <vscale x 3 x i8> @llvm.vp.add.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 %evl) 174 ret <vscale x 3 x i8> %v 175} 176 177define <vscale x 3 x i8> @vadd_vv_nxv3i8_unmasked(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, i32 zeroext %evl) { 178; CHECK-LABEL: vadd_vv_nxv3i8_unmasked: 179; CHECK: # %bb.0: 180; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 181; CHECK-NEXT: vadd.vv v8, v8, v9 182; CHECK-NEXT: ret 183 %v = call <vscale x 3 x i8> @llvm.vp.add.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> splat (i1 true), i32 %evl) 184 ret <vscale x 3 x i8> %v 185} 186 187define <vscale x 3 x i8> @vadd_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b, <vscale x 3 x i1> %m, i32 zeroext %evl) { 188; CHECK-LABEL: vadd_vx_nxv3i8: 189; CHECK: # %bb.0: 190; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma 191; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 192; CHECK-NEXT: ret 193 %elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0 194 %vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer 195 %v = call <vscale x 3 x i8> @llvm.vp.add.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> %m, i32 %evl) 196 ret <vscale x 3 x i8> %v 197} 198 199define <vscale x 3 x i8> @vadd_vx_nxv3i8_unmasked(<vscale x 3 x i8> %va, i8 %b, i32 zeroext %evl) { 200; CHECK-LABEL: vadd_vx_nxv3i8_unmasked: 201; CHECK: # %bb.0: 202; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma 203; CHECK-NEXT: vadd.vx v8, v8, a0 204; CHECK-NEXT: ret 205 %elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0 206 %vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer 207 %v = call <vscale x 3 x i8> @llvm.vp.add.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> splat (i1 true), i32 %evl) 208 ret <vscale x 3 x i8> %v 209} 210 211define <vscale x 3 x i8> @vadd_vi_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i1> %m, i32 zeroext %evl) { 212; CHECK-LABEL: vadd_vi_nxv3i8: 213; CHECK: # %bb.0: 214; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 215; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 216; CHECK-NEXT: ret 217 %v = call <vscale x 3 x i8> @llvm.vp.add.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> %m, i32 %evl) 218 ret <vscale x 3 x i8> %v 219} 220 221define <vscale x 3 x i8> @vadd_vi_nxv3i8_unmasked(<vscale x 3 x i8> %va, i32 zeroext %evl) { 222; CHECK-LABEL: vadd_vi_nxv3i8_unmasked: 223; CHECK: # %bb.0: 224; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 225; CHECK-NEXT: vadd.vi v8, v8, -1 226; CHECK-NEXT: ret 227 %v = call <vscale x 3 x i8> @llvm.vp.add.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> splat (i1 true), i32 %evl) 228 ret <vscale x 3 x i8> %v 229} 230 231declare <vscale x 4 x i8> @llvm.vp.add.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i32) 232 233define <vscale x 4 x i8> @vadd_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { 234; CHECK-LABEL: vadd_vv_nxv4i8: 235; CHECK: # %bb.0: 236; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 237; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t 238; CHECK-NEXT: ret 239 %v = call <vscale x 4 x i8> @llvm.vp.add.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 %evl) 240 ret <vscale x 4 x i8> %v 241} 242 243define <vscale x 4 x i8> @vadd_vv_nxv4i8_unmasked(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, i32 zeroext %evl) { 244; CHECK-LABEL: vadd_vv_nxv4i8_unmasked: 245; CHECK: # %bb.0: 246; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 247; CHECK-NEXT: vadd.vv v8, v8, v9 248; CHECK-NEXT: ret 249 %v = call <vscale x 4 x i8> @llvm.vp.add.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl) 250 ret <vscale x 4 x i8> %v 251} 252 253define <vscale x 4 x i8> @vadd_vx_nxv4i8(<vscale x 4 x i8> %va, i8 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { 254; CHECK-LABEL: vadd_vx_nxv4i8: 255; CHECK: # %bb.0: 256; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma 257; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 258; CHECK-NEXT: ret 259 %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0 260 %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer 261 %v = call <vscale x 4 x i8> @llvm.vp.add.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> %m, i32 %evl) 262 ret <vscale x 4 x i8> %v 263} 264 265define <vscale x 4 x i8> @vadd_vx_nxv4i8_unmasked(<vscale x 4 x i8> %va, i8 %b, i32 zeroext %evl) { 266; CHECK-LABEL: vadd_vx_nxv4i8_unmasked: 267; CHECK: # %bb.0: 268; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma 269; CHECK-NEXT: vadd.vx v8, v8, a0 270; CHECK-NEXT: ret 271 %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0 272 %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer 273 %v = call <vscale x 4 x i8> @llvm.vp.add.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl) 274 ret <vscale x 4 x i8> %v 275} 276 277define <vscale x 4 x i8> @vadd_vi_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { 278; CHECK-LABEL: vadd_vi_nxv4i8: 279; CHECK: # %bb.0: 280; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 281; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 282; CHECK-NEXT: ret 283 %v = call <vscale x 4 x i8> @llvm.vp.add.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> %m, i32 %evl) 284 ret <vscale x 4 x i8> %v 285} 286 287define <vscale x 4 x i8> @vadd_vi_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) { 288; CHECK-LABEL: vadd_vi_nxv4i8_unmasked: 289; CHECK: # %bb.0: 290; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 291; CHECK-NEXT: vadd.vi v8, v8, -1 292; CHECK-NEXT: ret 293 %v = call <vscale x 4 x i8> @llvm.vp.add.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl) 294 ret <vscale x 4 x i8> %v 295} 296 297declare <vscale x 8 x i8> @llvm.vp.add.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i32) 298 299define <vscale x 8 x i8> @vadd_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { 300; CHECK-LABEL: vadd_vv_nxv8i8: 301; CHECK: # %bb.0: 302; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma 303; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t 304; CHECK-NEXT: ret 305 %v = call <vscale x 8 x i8> @llvm.vp.add.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 %evl) 306 ret <vscale x 8 x i8> %v 307} 308 309define <vscale x 8 x i8> @vadd_vv_nxv8i8_unmasked(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, i32 zeroext %evl) { 310; CHECK-LABEL: vadd_vv_nxv8i8_unmasked: 311; CHECK: # %bb.0: 312; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma 313; CHECK-NEXT: vadd.vv v8, v8, v9 314; CHECK-NEXT: ret 315 %v = call <vscale x 8 x i8> @llvm.vp.add.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl) 316 ret <vscale x 8 x i8> %v 317} 318 319define <vscale x 8 x i8> @vadd_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { 320; CHECK-LABEL: vadd_vx_nxv8i8: 321; CHECK: # %bb.0: 322; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma 323; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 324; CHECK-NEXT: ret 325 %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 326 %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 327 %v = call <vscale x 8 x i8> @llvm.vp.add.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> %m, i32 %evl) 328 ret <vscale x 8 x i8> %v 329} 330 331define <vscale x 8 x i8> @vadd_vx_nxv8i8_unmasked(<vscale x 8 x i8> %va, i8 %b, i32 zeroext %evl) { 332; CHECK-LABEL: vadd_vx_nxv8i8_unmasked: 333; CHECK: # %bb.0: 334; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma 335; CHECK-NEXT: vadd.vx v8, v8, a0 336; CHECK-NEXT: ret 337 %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 338 %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 339 %v = call <vscale x 8 x i8> @llvm.vp.add.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl) 340 ret <vscale x 8 x i8> %v 341} 342 343define <vscale x 8 x i8> @vadd_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { 344; CHECK-LABEL: vadd_vi_nxv8i8: 345; CHECK: # %bb.0: 346; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma 347; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 348; CHECK-NEXT: ret 349 %v = call <vscale x 8 x i8> @llvm.vp.add.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> %m, i32 %evl) 350 ret <vscale x 8 x i8> %v 351} 352 353define <vscale x 8 x i8> @vadd_vi_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) { 354; CHECK-LABEL: vadd_vi_nxv8i8_unmasked: 355; CHECK: # %bb.0: 356; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma 357; CHECK-NEXT: vadd.vi v8, v8, -1 358; CHECK-NEXT: ret 359 %v = call <vscale x 8 x i8> @llvm.vp.add.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl) 360 ret <vscale x 8 x i8> %v 361} 362 363declare <vscale x 16 x i8> @llvm.vp.add.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, i32) 364 365define <vscale x 16 x i8> @vadd_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) { 366; CHECK-LABEL: vadd_vv_nxv16i8: 367; CHECK: # %bb.0: 368; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma 369; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t 370; CHECK-NEXT: ret 371 %v = call <vscale x 16 x i8> @llvm.vp.add.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 %evl) 372 ret <vscale x 16 x i8> %v 373} 374 375define <vscale x 16 x i8> @vadd_vv_nxv16i8_unmasked(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, i32 zeroext %evl) { 376; CHECK-LABEL: vadd_vv_nxv16i8_unmasked: 377; CHECK: # %bb.0: 378; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma 379; CHECK-NEXT: vadd.vv v8, v8, v10 380; CHECK-NEXT: ret 381 %v = call <vscale x 16 x i8> @llvm.vp.add.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl) 382 ret <vscale x 16 x i8> %v 383} 384 385define <vscale x 16 x i8> @vadd_vx_nxv16i8(<vscale x 16 x i8> %va, i8 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) { 386; CHECK-LABEL: vadd_vx_nxv16i8: 387; CHECK: # %bb.0: 388; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma 389; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 390; CHECK-NEXT: ret 391 %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0 392 %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer 393 %v = call <vscale x 16 x i8> @llvm.vp.add.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> %m, i32 %evl) 394 ret <vscale x 16 x i8> %v 395} 396 397define <vscale x 16 x i8> @vadd_vx_nxv16i8_unmasked(<vscale x 16 x i8> %va, i8 %b, i32 zeroext %evl) { 398; CHECK-LABEL: vadd_vx_nxv16i8_unmasked: 399; CHECK: # %bb.0: 400; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma 401; CHECK-NEXT: vadd.vx v8, v8, a0 402; CHECK-NEXT: ret 403 %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0 404 %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer 405 %v = call <vscale x 16 x i8> @llvm.vp.add.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl) 406 ret <vscale x 16 x i8> %v 407} 408 409define <vscale x 16 x i8> @vadd_vi_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { 410; CHECK-LABEL: vadd_vi_nxv16i8: 411; CHECK: # %bb.0: 412; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma 413; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 414; CHECK-NEXT: ret 415 %v = call <vscale x 16 x i8> @llvm.vp.add.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> %m, i32 %evl) 416 ret <vscale x 16 x i8> %v 417} 418 419define <vscale x 16 x i8> @vadd_vi_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) { 420; CHECK-LABEL: vadd_vi_nxv16i8_unmasked: 421; CHECK: # %bb.0: 422; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma 423; CHECK-NEXT: vadd.vi v8, v8, -1 424; CHECK-NEXT: ret 425 %v = call <vscale x 16 x i8> @llvm.vp.add.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl) 426 ret <vscale x 16 x i8> %v 427} 428 429declare <vscale x 32 x i8> @llvm.vp.add.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i1>, i32) 430 431define <vscale x 32 x i8> @vadd_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) { 432; CHECK-LABEL: vadd_vv_nxv32i8: 433; CHECK: # %bb.0: 434; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma 435; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t 436; CHECK-NEXT: ret 437 %v = call <vscale x 32 x i8> @llvm.vp.add.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 %evl) 438 ret <vscale x 32 x i8> %v 439} 440 441define <vscale x 32 x i8> @vadd_vv_nxv32i8_unmasked(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, i32 zeroext %evl) { 442; CHECK-LABEL: vadd_vv_nxv32i8_unmasked: 443; CHECK: # %bb.0: 444; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma 445; CHECK-NEXT: vadd.vv v8, v8, v12 446; CHECK-NEXT: ret 447 %v = call <vscale x 32 x i8> @llvm.vp.add.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl) 448 ret <vscale x 32 x i8> %v 449} 450 451define <vscale x 32 x i8> @vadd_vx_nxv32i8(<vscale x 32 x i8> %va, i8 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) { 452; CHECK-LABEL: vadd_vx_nxv32i8: 453; CHECK: # %bb.0: 454; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma 455; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 456; CHECK-NEXT: ret 457 %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0 458 %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer 459 %v = call <vscale x 32 x i8> @llvm.vp.add.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> %m, i32 %evl) 460 ret <vscale x 32 x i8> %v 461} 462 463define <vscale x 32 x i8> @vadd_vx_nxv32i8_unmasked(<vscale x 32 x i8> %va, i8 %b, i32 zeroext %evl) { 464; CHECK-LABEL: vadd_vx_nxv32i8_unmasked: 465; CHECK: # %bb.0: 466; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma 467; CHECK-NEXT: vadd.vx v8, v8, a0 468; CHECK-NEXT: ret 469 %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0 470 %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer 471 %v = call <vscale x 32 x i8> @llvm.vp.add.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl) 472 ret <vscale x 32 x i8> %v 473} 474 475define <vscale x 32 x i8> @vadd_vi_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { 476; CHECK-LABEL: vadd_vi_nxv32i8: 477; CHECK: # %bb.0: 478; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma 479; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 480; CHECK-NEXT: ret 481 %v = call <vscale x 32 x i8> @llvm.vp.add.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> %m, i32 %evl) 482 ret <vscale x 32 x i8> %v 483} 484 485define <vscale x 32 x i8> @vadd_vi_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) { 486; CHECK-LABEL: vadd_vi_nxv32i8_unmasked: 487; CHECK: # %bb.0: 488; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma 489; CHECK-NEXT: vadd.vi v8, v8, -1 490; CHECK-NEXT: ret 491 %v = call <vscale x 32 x i8> @llvm.vp.add.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl) 492 ret <vscale x 32 x i8> %v 493} 494 495declare <vscale x 64 x i8> @llvm.vp.add.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i1>, i32) 496 497define <vscale x 64 x i8> @vadd_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 zeroext %evl) { 498; CHECK-LABEL: vadd_vv_nxv64i8: 499; CHECK: # %bb.0: 500; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma 501; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t 502; CHECK-NEXT: ret 503 %v = call <vscale x 64 x i8> @llvm.vp.add.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 %evl) 504 ret <vscale x 64 x i8> %v 505} 506 507define <vscale x 64 x i8> @vadd_vv_nxv64i8_unmasked(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, i32 zeroext %evl) { 508; CHECK-LABEL: vadd_vv_nxv64i8_unmasked: 509; CHECK: # %bb.0: 510; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma 511; CHECK-NEXT: vadd.vv v8, v8, v16 512; CHECK-NEXT: ret 513 %v = call <vscale x 64 x i8> @llvm.vp.add.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> splat (i1 true), i32 %evl) 514 ret <vscale x 64 x i8> %v 515} 516 517define <vscale x 64 x i8> @vadd_vx_nxv64i8(<vscale x 64 x i8> %va, i8 %b, <vscale x 64 x i1> %m, i32 zeroext %evl) { 518; CHECK-LABEL: vadd_vx_nxv64i8: 519; CHECK: # %bb.0: 520; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma 521; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 522; CHECK-NEXT: ret 523 %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0 524 %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer 525 %v = call <vscale x 64 x i8> @llvm.vp.add.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> %m, i32 %evl) 526 ret <vscale x 64 x i8> %v 527} 528 529define <vscale x 64 x i8> @vadd_vx_nxv64i8_unmasked(<vscale x 64 x i8> %va, i8 %b, i32 zeroext %evl) { 530; CHECK-LABEL: vadd_vx_nxv64i8_unmasked: 531; CHECK: # %bb.0: 532; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma 533; CHECK-NEXT: vadd.vx v8, v8, a0 534; CHECK-NEXT: ret 535 %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0 536 %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer 537 %v = call <vscale x 64 x i8> @llvm.vp.add.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> splat (i1 true), i32 %evl) 538 ret <vscale x 64 x i8> %v 539} 540 541define <vscale x 64 x i8> @vadd_vi_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) { 542; CHECK-LABEL: vadd_vi_nxv64i8: 543; CHECK: # %bb.0: 544; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma 545; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 546; CHECK-NEXT: ret 547 %v = call <vscale x 64 x i8> @llvm.vp.add.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> %m, i32 %evl) 548 ret <vscale x 64 x i8> %v 549} 550 551define <vscale x 64 x i8> @vadd_vi_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) { 552; CHECK-LABEL: vadd_vi_nxv64i8_unmasked: 553; CHECK: # %bb.0: 554; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma 555; CHECK-NEXT: vadd.vi v8, v8, -1 556; CHECK-NEXT: ret 557 %v = call <vscale x 64 x i8> @llvm.vp.add.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> splat (i1 true), i32 %evl) 558 ret <vscale x 64 x i8> %v 559} 560 561; Test that split-legalization works when the mask itself needs splitting. 562 563declare <vscale x 128 x i8> @llvm.vp.add.nxv128i8(<vscale x 128 x i8>, <vscale x 128 x i8>, <vscale x 128 x i1>, i32) 564 565define <vscale x 128 x i8> @vadd_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i1> %m, i32 zeroext %evl) { 566; CHECK-LABEL: vadd_vi_nxv128i8: 567; CHECK: # %bb.0: 568; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma 569; CHECK-NEXT: vmv1r.v v24, v0 570; CHECK-NEXT: vlm.v v0, (a0) 571; CHECK-NEXT: csrr a0, vlenb 572; CHECK-NEXT: slli a0, a0, 3 573; CHECK-NEXT: sub a2, a1, a0 574; CHECK-NEXT: sltu a3, a1, a2 575; CHECK-NEXT: addi a3, a3, -1 576; CHECK-NEXT: and a2, a3, a2 577; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma 578; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t 579; CHECK-NEXT: bltu a1, a0, .LBB50_2 580; CHECK-NEXT: # %bb.1: 581; CHECK-NEXT: mv a1, a0 582; CHECK-NEXT: .LBB50_2: 583; CHECK-NEXT: vmv1r.v v0, v24 584; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma 585; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 586; CHECK-NEXT: ret 587 %v = call <vscale x 128 x i8> @llvm.vp.add.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> %m, i32 %evl) 588 ret <vscale x 128 x i8> %v 589} 590 591define <vscale x 128 x i8> @vadd_vi_nxv128i8_unmasked(<vscale x 128 x i8> %va, i32 zeroext %evl) { 592; CHECK-LABEL: vadd_vi_nxv128i8_unmasked: 593; CHECK: # %bb.0: 594; CHECK-NEXT: csrr a1, vlenb 595; CHECK-NEXT: slli a1, a1, 3 596; CHECK-NEXT: sub a2, a0, a1 597; CHECK-NEXT: sltu a3, a0, a2 598; CHECK-NEXT: addi a3, a3, -1 599; CHECK-NEXT: and a2, a3, a2 600; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma 601; CHECK-NEXT: vadd.vi v16, v16, -1 602; CHECK-NEXT: bltu a0, a1, .LBB51_2 603; CHECK-NEXT: # %bb.1: 604; CHECK-NEXT: mv a0, a1 605; CHECK-NEXT: .LBB51_2: 606; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma 607; CHECK-NEXT: vadd.vi v8, v8, -1 608; CHECK-NEXT: ret 609 %v = call <vscale x 128 x i8> @llvm.vp.add.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> splat (i1 true), i32 %evl) 610 ret <vscale x 128 x i8> %v 611} 612 613declare <vscale x 1 x i16> @llvm.vp.add.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i1>, i32) 614 615define <vscale x 1 x i16> @vadd_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { 616; CHECK-LABEL: vadd_vv_nxv1i16: 617; CHECK: # %bb.0: 618; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma 619; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t 620; CHECK-NEXT: ret 621 %v = call <vscale x 1 x i16> @llvm.vp.add.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 %evl) 622 ret <vscale x 1 x i16> %v 623} 624 625define <vscale x 1 x i16> @vadd_vv_nxv1i16_unmasked(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, i32 zeroext %evl) { 626; CHECK-LABEL: vadd_vv_nxv1i16_unmasked: 627; CHECK: # %bb.0: 628; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma 629; CHECK-NEXT: vadd.vv v8, v8, v9 630; CHECK-NEXT: ret 631 %v = call <vscale x 1 x i16> @llvm.vp.add.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl) 632 ret <vscale x 1 x i16> %v 633} 634 635define <vscale x 1 x i16> @vadd_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { 636; CHECK-LABEL: vadd_vx_nxv1i16: 637; CHECK: # %bb.0: 638; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma 639; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 640; CHECK-NEXT: ret 641 %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0 642 %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer 643 %v = call <vscale x 1 x i16> @llvm.vp.add.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> %m, i32 %evl) 644 ret <vscale x 1 x i16> %v 645} 646 647define <vscale x 1 x i16> @vadd_vx_nxv1i16_unmasked(<vscale x 1 x i16> %va, i16 %b, i32 zeroext %evl) { 648; CHECK-LABEL: vadd_vx_nxv1i16_unmasked: 649; CHECK: # %bb.0: 650; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma 651; CHECK-NEXT: vadd.vx v8, v8, a0 652; CHECK-NEXT: ret 653 %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0 654 %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer 655 %v = call <vscale x 1 x i16> @llvm.vp.add.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl) 656 ret <vscale x 1 x i16> %v 657} 658 659define <vscale x 1 x i16> @vadd_vi_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { 660; CHECK-LABEL: vadd_vi_nxv1i16: 661; CHECK: # %bb.0: 662; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma 663; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 664; CHECK-NEXT: ret 665 %v = call <vscale x 1 x i16> @llvm.vp.add.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> %m, i32 %evl) 666 ret <vscale x 1 x i16> %v 667} 668 669define <vscale x 1 x i16> @vadd_vi_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) { 670; CHECK-LABEL: vadd_vi_nxv1i16_unmasked: 671; CHECK: # %bb.0: 672; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma 673; CHECK-NEXT: vadd.vi v8, v8, -1 674; CHECK-NEXT: ret 675 %v = call <vscale x 1 x i16> @llvm.vp.add.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl) 676 ret <vscale x 1 x i16> %v 677} 678 679declare <vscale x 2 x i16> @llvm.vp.add.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i1>, i32) 680 681define <vscale x 2 x i16> @vadd_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { 682; CHECK-LABEL: vadd_vv_nxv2i16: 683; CHECK: # %bb.0: 684; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 685; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t 686; CHECK-NEXT: ret 687 %v = call <vscale x 2 x i16> @llvm.vp.add.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 %evl) 688 ret <vscale x 2 x i16> %v 689} 690 691define <vscale x 2 x i16> @vadd_vv_nxv2i16_unmasked(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, i32 zeroext %evl) { 692; CHECK-LABEL: vadd_vv_nxv2i16_unmasked: 693; CHECK: # %bb.0: 694; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 695; CHECK-NEXT: vadd.vv v8, v8, v9 696; CHECK-NEXT: ret 697 %v = call <vscale x 2 x i16> @llvm.vp.add.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl) 698 ret <vscale x 2 x i16> %v 699} 700 701define <vscale x 2 x i16> @vadd_vx_nxv2i16(<vscale x 2 x i16> %va, i16 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { 702; CHECK-LABEL: vadd_vx_nxv2i16: 703; CHECK: # %bb.0: 704; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma 705; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 706; CHECK-NEXT: ret 707 %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0 708 %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer 709 %v = call <vscale x 2 x i16> @llvm.vp.add.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> %m, i32 %evl) 710 ret <vscale x 2 x i16> %v 711} 712 713define <vscale x 2 x i16> @vadd_vx_nxv2i16_unmasked(<vscale x 2 x i16> %va, i16 %b, i32 zeroext %evl) { 714; CHECK-LABEL: vadd_vx_nxv2i16_unmasked: 715; CHECK: # %bb.0: 716; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma 717; CHECK-NEXT: vadd.vx v8, v8, a0 718; CHECK-NEXT: ret 719 %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0 720 %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer 721 %v = call <vscale x 2 x i16> @llvm.vp.add.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl) 722 ret <vscale x 2 x i16> %v 723} 724 725define <vscale x 2 x i16> @vadd_vi_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { 726; CHECK-LABEL: vadd_vi_nxv2i16: 727; CHECK: # %bb.0: 728; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 729; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 730; CHECK-NEXT: ret 731 %v = call <vscale x 2 x i16> @llvm.vp.add.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> %m, i32 %evl) 732 ret <vscale x 2 x i16> %v 733} 734 735define <vscale x 2 x i16> @vadd_vi_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) { 736; CHECK-LABEL: vadd_vi_nxv2i16_unmasked: 737; CHECK: # %bb.0: 738; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 739; CHECK-NEXT: vadd.vi v8, v8, -1 740; CHECK-NEXT: ret 741 %v = call <vscale x 2 x i16> @llvm.vp.add.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl) 742 ret <vscale x 2 x i16> %v 743} 744 745declare <vscale x 4 x i16> @llvm.vp.add.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i1>, i32) 746 747define <vscale x 4 x i16> @vadd_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { 748; CHECK-LABEL: vadd_vv_nxv4i16: 749; CHECK: # %bb.0: 750; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma 751; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t 752; CHECK-NEXT: ret 753 %v = call <vscale x 4 x i16> @llvm.vp.add.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 %evl) 754 ret <vscale x 4 x i16> %v 755} 756 757define <vscale x 4 x i16> @vadd_vv_nxv4i16_unmasked(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, i32 zeroext %evl) { 758; CHECK-LABEL: vadd_vv_nxv4i16_unmasked: 759; CHECK: # %bb.0: 760; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma 761; CHECK-NEXT: vadd.vv v8, v8, v9 762; CHECK-NEXT: ret 763 %v = call <vscale x 4 x i16> @llvm.vp.add.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl) 764 ret <vscale x 4 x i16> %v 765} 766 767define <vscale x 4 x i16> @vadd_vx_nxv4i16(<vscale x 4 x i16> %va, i16 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { 768; CHECK-LABEL: vadd_vx_nxv4i16: 769; CHECK: # %bb.0: 770; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma 771; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 772; CHECK-NEXT: ret 773 %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0 774 %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer 775 %v = call <vscale x 4 x i16> @llvm.vp.add.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> %m, i32 %evl) 776 ret <vscale x 4 x i16> %v 777} 778 779define <vscale x 4 x i16> @vadd_vx_nxv4i16_unmasked(<vscale x 4 x i16> %va, i16 %b, i32 zeroext %evl) { 780; CHECK-LABEL: vadd_vx_nxv4i16_unmasked: 781; CHECK: # %bb.0: 782; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma 783; CHECK-NEXT: vadd.vx v8, v8, a0 784; CHECK-NEXT: ret 785 %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0 786 %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer 787 %v = call <vscale x 4 x i16> @llvm.vp.add.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl) 788 ret <vscale x 4 x i16> %v 789} 790 791define <vscale x 4 x i16> @vadd_vi_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { 792; CHECK-LABEL: vadd_vi_nxv4i16: 793; CHECK: # %bb.0: 794; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma 795; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 796; CHECK-NEXT: ret 797 %v = call <vscale x 4 x i16> @llvm.vp.add.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> %m, i32 %evl) 798 ret <vscale x 4 x i16> %v 799} 800 801define <vscale x 4 x i16> @vadd_vi_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) { 802; CHECK-LABEL: vadd_vi_nxv4i16_unmasked: 803; CHECK: # %bb.0: 804; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma 805; CHECK-NEXT: vadd.vi v8, v8, -1 806; CHECK-NEXT: ret 807 %v = call <vscale x 4 x i16> @llvm.vp.add.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl) 808 ret <vscale x 4 x i16> %v 809} 810 811declare <vscale x 8 x i16> @llvm.vp.add.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, i32) 812 813define <vscale x 8 x i16> @vadd_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { 814; CHECK-LABEL: vadd_vv_nxv8i16: 815; CHECK: # %bb.0: 816; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma 817; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t 818; CHECK-NEXT: ret 819 %v = call <vscale x 8 x i16> @llvm.vp.add.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 %evl) 820 ret <vscale x 8 x i16> %v 821} 822 823define <vscale x 8 x i16> @vadd_vv_nxv8i16_unmasked(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, i32 zeroext %evl) { 824; CHECK-LABEL: vadd_vv_nxv8i16_unmasked: 825; CHECK: # %bb.0: 826; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma 827; CHECK-NEXT: vadd.vv v8, v8, v10 828; CHECK-NEXT: ret 829 %v = call <vscale x 8 x i16> @llvm.vp.add.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl) 830 ret <vscale x 8 x i16> %v 831} 832 833define <vscale x 8 x i16> @vadd_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { 834; CHECK-LABEL: vadd_vx_nxv8i16: 835; CHECK: # %bb.0: 836; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma 837; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 838; CHECK-NEXT: ret 839 %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 840 %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 841 %v = call <vscale x 8 x i16> @llvm.vp.add.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> %m, i32 %evl) 842 ret <vscale x 8 x i16> %v 843} 844 845define <vscale x 8 x i16> @vadd_vx_nxv8i16_unmasked(<vscale x 8 x i16> %va, i16 %b, i32 zeroext %evl) { 846; CHECK-LABEL: vadd_vx_nxv8i16_unmasked: 847; CHECK: # %bb.0: 848; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma 849; CHECK-NEXT: vadd.vx v8, v8, a0 850; CHECK-NEXT: ret 851 %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 852 %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 853 %v = call <vscale x 8 x i16> @llvm.vp.add.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl) 854 ret <vscale x 8 x i16> %v 855} 856 857define <vscale x 8 x i16> @vadd_vi_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { 858; CHECK-LABEL: vadd_vi_nxv8i16: 859; CHECK: # %bb.0: 860; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma 861; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 862; CHECK-NEXT: ret 863 %v = call <vscale x 8 x i16> @llvm.vp.add.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> %m, i32 %evl) 864 ret <vscale x 8 x i16> %v 865} 866 867define <vscale x 8 x i16> @vadd_vi_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) { 868; CHECK-LABEL: vadd_vi_nxv8i16_unmasked: 869; CHECK: # %bb.0: 870; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma 871; CHECK-NEXT: vadd.vi v8, v8, -1 872; CHECK-NEXT: ret 873 %v = call <vscale x 8 x i16> @llvm.vp.add.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl) 874 ret <vscale x 8 x i16> %v 875} 876 877declare <vscale x 16 x i16> @llvm.vp.add.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i1>, i32) 878 879define <vscale x 16 x i16> @vadd_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) { 880; CHECK-LABEL: vadd_vv_nxv16i16: 881; CHECK: # %bb.0: 882; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma 883; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t 884; CHECK-NEXT: ret 885 %v = call <vscale x 16 x i16> @llvm.vp.add.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 %evl) 886 ret <vscale x 16 x i16> %v 887} 888 889define <vscale x 16 x i16> @vadd_vv_nxv16i16_unmasked(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, i32 zeroext %evl) { 890; CHECK-LABEL: vadd_vv_nxv16i16_unmasked: 891; CHECK: # %bb.0: 892; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma 893; CHECK-NEXT: vadd.vv v8, v8, v12 894; CHECK-NEXT: ret 895 %v = call <vscale x 16 x i16> @llvm.vp.add.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl) 896 ret <vscale x 16 x i16> %v 897} 898 899define <vscale x 16 x i16> @vadd_vx_nxv16i16(<vscale x 16 x i16> %va, i16 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) { 900; CHECK-LABEL: vadd_vx_nxv16i16: 901; CHECK: # %bb.0: 902; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma 903; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 904; CHECK-NEXT: ret 905 %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0 906 %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer 907 %v = call <vscale x 16 x i16> @llvm.vp.add.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> %m, i32 %evl) 908 ret <vscale x 16 x i16> %v 909} 910 911define <vscale x 16 x i16> @vadd_vx_nxv16i16_unmasked(<vscale x 16 x i16> %va, i16 %b, i32 zeroext %evl) { 912; CHECK-LABEL: vadd_vx_nxv16i16_unmasked: 913; CHECK: # %bb.0: 914; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma 915; CHECK-NEXT: vadd.vx v8, v8, a0 916; CHECK-NEXT: ret 917 %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0 918 %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer 919 %v = call <vscale x 16 x i16> @llvm.vp.add.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl) 920 ret <vscale x 16 x i16> %v 921} 922 923define <vscale x 16 x i16> @vadd_vi_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { 924; CHECK-LABEL: vadd_vi_nxv16i16: 925; CHECK: # %bb.0: 926; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma 927; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 928; CHECK-NEXT: ret 929 %v = call <vscale x 16 x i16> @llvm.vp.add.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> %m, i32 %evl) 930 ret <vscale x 16 x i16> %v 931} 932 933define <vscale x 16 x i16> @vadd_vi_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) { 934; CHECK-LABEL: vadd_vi_nxv16i16_unmasked: 935; CHECK: # %bb.0: 936; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma 937; CHECK-NEXT: vadd.vi v8, v8, -1 938; CHECK-NEXT: ret 939 %v = call <vscale x 16 x i16> @llvm.vp.add.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl) 940 ret <vscale x 16 x i16> %v 941} 942 943declare <vscale x 32 x i16> @llvm.vp.add.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>, <vscale x 32 x i1>, i32) 944 945define <vscale x 32 x i16> @vadd_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) { 946; CHECK-LABEL: vadd_vv_nxv32i16: 947; CHECK: # %bb.0: 948; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma 949; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t 950; CHECK-NEXT: ret 951 %v = call <vscale x 32 x i16> @llvm.vp.add.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 %evl) 952 ret <vscale x 32 x i16> %v 953} 954 955define <vscale x 32 x i16> @vadd_vv_nxv32i16_unmasked(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, i32 zeroext %evl) { 956; CHECK-LABEL: vadd_vv_nxv32i16_unmasked: 957; CHECK: # %bb.0: 958; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma 959; CHECK-NEXT: vadd.vv v8, v8, v16 960; CHECK-NEXT: ret 961 %v = call <vscale x 32 x i16> @llvm.vp.add.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl) 962 ret <vscale x 32 x i16> %v 963} 964 965define <vscale x 32 x i16> @vadd_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) { 966; CHECK-LABEL: vadd_vx_nxv32i16: 967; CHECK: # %bb.0: 968; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma 969; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 970; CHECK-NEXT: ret 971 %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0 972 %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer 973 %v = call <vscale x 32 x i16> @llvm.vp.add.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> %m, i32 %evl) 974 ret <vscale x 32 x i16> %v 975} 976 977define <vscale x 32 x i16> @vadd_vx_nxv32i16_unmasked(<vscale x 32 x i16> %va, i16 %b, i32 zeroext %evl) { 978; CHECK-LABEL: vadd_vx_nxv32i16_unmasked: 979; CHECK: # %bb.0: 980; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma 981; CHECK-NEXT: vadd.vx v8, v8, a0 982; CHECK-NEXT: ret 983 %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0 984 %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer 985 %v = call <vscale x 32 x i16> @llvm.vp.add.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl) 986 ret <vscale x 32 x i16> %v 987} 988 989define <vscale x 32 x i16> @vadd_vi_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { 990; CHECK-LABEL: vadd_vi_nxv32i16: 991; CHECK: # %bb.0: 992; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma 993; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 994; CHECK-NEXT: ret 995 %v = call <vscale x 32 x i16> @llvm.vp.add.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> %m, i32 %evl) 996 ret <vscale x 32 x i16> %v 997} 998 999define <vscale x 32 x i16> @vadd_vi_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) { 1000; CHECK-LABEL: vadd_vi_nxv32i16_unmasked: 1001; CHECK: # %bb.0: 1002; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma 1003; CHECK-NEXT: vadd.vi v8, v8, -1 1004; CHECK-NEXT: ret 1005 %v = call <vscale x 32 x i16> @llvm.vp.add.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl) 1006 ret <vscale x 32 x i16> %v 1007} 1008 1009declare <vscale x 1 x i32> @llvm.vp.add.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i32) 1010 1011define <vscale x 1 x i32> @vadd_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { 1012; CHECK-LABEL: vadd_vv_nxv1i32: 1013; CHECK: # %bb.0: 1014; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma 1015; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t 1016; CHECK-NEXT: ret 1017 %v = call <vscale x 1 x i32> @llvm.vp.add.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 %evl) 1018 ret <vscale x 1 x i32> %v 1019} 1020 1021define <vscale x 1 x i32> @vadd_vv_nxv1i32_unmasked(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, i32 zeroext %evl) { 1022; CHECK-LABEL: vadd_vv_nxv1i32_unmasked: 1023; CHECK: # %bb.0: 1024; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma 1025; CHECK-NEXT: vadd.vv v8, v8, v9 1026; CHECK-NEXT: ret 1027 %v = call <vscale x 1 x i32> @llvm.vp.add.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl) 1028 ret <vscale x 1 x i32> %v 1029} 1030 1031define <vscale x 1 x i32> @vadd_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { 1032; CHECK-LABEL: vadd_vx_nxv1i32: 1033; CHECK: # %bb.0: 1034; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma 1035; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 1036; CHECK-NEXT: ret 1037 %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0 1038 %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer 1039 %v = call <vscale x 1 x i32> @llvm.vp.add.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> %m, i32 %evl) 1040 ret <vscale x 1 x i32> %v 1041} 1042 1043define <vscale x 1 x i32> @vadd_vx_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 %b, i32 zeroext %evl) { 1044; CHECK-LABEL: vadd_vx_nxv1i32_unmasked: 1045; CHECK: # %bb.0: 1046; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma 1047; CHECK-NEXT: vadd.vx v8, v8, a0 1048; CHECK-NEXT: ret 1049 %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0 1050 %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer 1051 %v = call <vscale x 1 x i32> @llvm.vp.add.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl) 1052 ret <vscale x 1 x i32> %v 1053} 1054 1055define <vscale x 1 x i32> @vadd_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { 1056; CHECK-LABEL: vadd_vi_nxv1i32: 1057; CHECK: # %bb.0: 1058; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma 1059; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 1060; CHECK-NEXT: ret 1061 %v = call <vscale x 1 x i32> @llvm.vp.add.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> %m, i32 %evl) 1062 ret <vscale x 1 x i32> %v 1063} 1064 1065define <vscale x 1 x i32> @vadd_vi_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) { 1066; CHECK-LABEL: vadd_vi_nxv1i32_unmasked: 1067; CHECK: # %bb.0: 1068; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma 1069; CHECK-NEXT: vadd.vi v8, v8, -1 1070; CHECK-NEXT: ret 1071 %v = call <vscale x 1 x i32> @llvm.vp.add.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl) 1072 ret <vscale x 1 x i32> %v 1073} 1074 1075declare <vscale x 2 x i32> @llvm.vp.add.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i32) 1076 1077define <vscale x 2 x i32> @vadd_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { 1078; CHECK-LABEL: vadd_vv_nxv2i32: 1079; CHECK: # %bb.0: 1080; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 1081; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t 1082; CHECK-NEXT: ret 1083 %v = call <vscale x 2 x i32> @llvm.vp.add.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 %evl) 1084 ret <vscale x 2 x i32> %v 1085} 1086 1087define <vscale x 2 x i32> @vadd_vv_nxv2i32_unmasked(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, i32 zeroext %evl) { 1088; CHECK-LABEL: vadd_vv_nxv2i32_unmasked: 1089; CHECK: # %bb.0: 1090; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 1091; CHECK-NEXT: vadd.vv v8, v8, v9 1092; CHECK-NEXT: ret 1093 %v = call <vscale x 2 x i32> @llvm.vp.add.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl) 1094 ret <vscale x 2 x i32> %v 1095} 1096 1097define <vscale x 2 x i32> @vadd_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { 1098; CHECK-LABEL: vadd_vx_nxv2i32: 1099; CHECK: # %bb.0: 1100; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma 1101; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 1102; CHECK-NEXT: ret 1103 %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0 1104 %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer 1105 %v = call <vscale x 2 x i32> @llvm.vp.add.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %m, i32 %evl) 1106 ret <vscale x 2 x i32> %v 1107} 1108 1109define <vscale x 2 x i32> @vadd_vx_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 %b, i32 zeroext %evl) { 1110; CHECK-LABEL: vadd_vx_nxv2i32_unmasked: 1111; CHECK: # %bb.0: 1112; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma 1113; CHECK-NEXT: vadd.vx v8, v8, a0 1114; CHECK-NEXT: ret 1115 %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0 1116 %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer 1117 %v = call <vscale x 2 x i32> @llvm.vp.add.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl) 1118 ret <vscale x 2 x i32> %v 1119} 1120 1121define <vscale x 2 x i32> @vadd_vi_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { 1122; CHECK-LABEL: vadd_vi_nxv2i32: 1123; CHECK: # %bb.0: 1124; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 1125; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 1126; CHECK-NEXT: ret 1127 %v = call <vscale x 2 x i32> @llvm.vp.add.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> %m, i32 %evl) 1128 ret <vscale x 2 x i32> %v 1129} 1130 1131define <vscale x 2 x i32> @vadd_vi_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) { 1132; CHECK-LABEL: vadd_vi_nxv2i32_unmasked: 1133; CHECK: # %bb.0: 1134; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 1135; CHECK-NEXT: vadd.vi v8, v8, -1 1136; CHECK-NEXT: ret 1137 %v = call <vscale x 2 x i32> @llvm.vp.add.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl) 1138 ret <vscale x 2 x i32> %v 1139} 1140 1141declare <vscale x 4 x i32> @llvm.vp.add.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32) 1142 1143define <vscale x 4 x i32> @vadd_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { 1144; CHECK-LABEL: vadd_vv_nxv4i32: 1145; CHECK: # %bb.0: 1146; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma 1147; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t 1148; CHECK-NEXT: ret 1149 %v = call <vscale x 4 x i32> @llvm.vp.add.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 %evl) 1150 ret <vscale x 4 x i32> %v 1151} 1152 1153define <vscale x 4 x i32> @vadd_vv_nxv4i32_unmasked(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, i32 zeroext %evl) { 1154; CHECK-LABEL: vadd_vv_nxv4i32_unmasked: 1155; CHECK: # %bb.0: 1156; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma 1157; CHECK-NEXT: vadd.vv v8, v8, v10 1158; CHECK-NEXT: ret 1159 %v = call <vscale x 4 x i32> @llvm.vp.add.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl) 1160 ret <vscale x 4 x i32> %v 1161} 1162 1163define <vscale x 4 x i32> @vadd_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { 1164; CHECK-LABEL: vadd_vx_nxv4i32: 1165; CHECK: # %bb.0: 1166; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma 1167; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 1168; CHECK-NEXT: ret 1169 %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0 1170 %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer 1171 %v = call <vscale x 4 x i32> @llvm.vp.add.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> %m, i32 %evl) 1172 ret <vscale x 4 x i32> %v 1173} 1174 1175define <vscale x 4 x i32> @vadd_vx_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 %b, i32 zeroext %evl) { 1176; CHECK-LABEL: vadd_vx_nxv4i32_unmasked: 1177; CHECK: # %bb.0: 1178; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma 1179; CHECK-NEXT: vadd.vx v8, v8, a0 1180; CHECK-NEXT: ret 1181 %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0 1182 %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer 1183 %v = call <vscale x 4 x i32> @llvm.vp.add.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl) 1184 ret <vscale x 4 x i32> %v 1185} 1186 1187define <vscale x 4 x i32> @vadd_vi_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { 1188; CHECK-LABEL: vadd_vi_nxv4i32: 1189; CHECK: # %bb.0: 1190; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma 1191; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 1192; CHECK-NEXT: ret 1193 %v = call <vscale x 4 x i32> @llvm.vp.add.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> %m, i32 %evl) 1194 ret <vscale x 4 x i32> %v 1195} 1196 1197define <vscale x 4 x i32> @vadd_vi_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) { 1198; CHECK-LABEL: vadd_vi_nxv4i32_unmasked: 1199; CHECK: # %bb.0: 1200; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma 1201; CHECK-NEXT: vadd.vi v8, v8, -1 1202; CHECK-NEXT: ret 1203 %v = call <vscale x 4 x i32> @llvm.vp.add.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl) 1204 ret <vscale x 4 x i32> %v 1205} 1206 1207declare <vscale x 8 x i32> @llvm.vp.add.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i1>, i32) 1208 1209define <vscale x 8 x i32> @vadd_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { 1210; CHECK-LABEL: vadd_vv_nxv8i32: 1211; CHECK: # %bb.0: 1212; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma 1213; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t 1214; CHECK-NEXT: ret 1215 %v = call <vscale x 8 x i32> @llvm.vp.add.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 %evl) 1216 ret <vscale x 8 x i32> %v 1217} 1218 1219define <vscale x 8 x i32> @vadd_vv_nxv8i32_unmasked(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, i32 zeroext %evl) { 1220; CHECK-LABEL: vadd_vv_nxv8i32_unmasked: 1221; CHECK: # %bb.0: 1222; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma 1223; CHECK-NEXT: vadd.vv v8, v8, v12 1224; CHECK-NEXT: ret 1225 %v = call <vscale x 8 x i32> @llvm.vp.add.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl) 1226 ret <vscale x 8 x i32> %v 1227} 1228 1229define <vscale x 8 x i32> @vadd_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { 1230; CHECK-LABEL: vadd_vx_nxv8i32: 1231; CHECK: # %bb.0: 1232; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma 1233; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 1234; CHECK-NEXT: ret 1235 %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 1236 %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1237 %v = call <vscale x 8 x i32> @llvm.vp.add.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %m, i32 %evl) 1238 ret <vscale x 8 x i32> %v 1239} 1240 1241define <vscale x 8 x i32> @vadd_vx_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 %b, i32 zeroext %evl) { 1242; CHECK-LABEL: vadd_vx_nxv8i32_unmasked: 1243; CHECK: # %bb.0: 1244; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma 1245; CHECK-NEXT: vadd.vx v8, v8, a0 1246; CHECK-NEXT: ret 1247 %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 1248 %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1249 %v = call <vscale x 8 x i32> @llvm.vp.add.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl) 1250 ret <vscale x 8 x i32> %v 1251} 1252 1253define <vscale x 8 x i32> @vadd_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { 1254; CHECK-LABEL: vadd_vi_nxv8i32: 1255; CHECK: # %bb.0: 1256; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma 1257; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 1258; CHECK-NEXT: ret 1259 %v = call <vscale x 8 x i32> @llvm.vp.add.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> %m, i32 %evl) 1260 ret <vscale x 8 x i32> %v 1261} 1262 1263define <vscale x 8 x i32> @vadd_vi_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) { 1264; CHECK-LABEL: vadd_vi_nxv8i32_unmasked: 1265; CHECK: # %bb.0: 1266; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma 1267; CHECK-NEXT: vadd.vi v8, v8, -1 1268; CHECK-NEXT: ret 1269 %v = call <vscale x 8 x i32> @llvm.vp.add.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl) 1270 ret <vscale x 8 x i32> %v 1271} 1272 1273declare <vscale x 16 x i32> @llvm.vp.add.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i1>, i32) 1274 1275define <vscale x 16 x i32> @vadd_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) { 1276; CHECK-LABEL: vadd_vv_nxv16i32: 1277; CHECK: # %bb.0: 1278; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma 1279; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t 1280; CHECK-NEXT: ret 1281 %v = call <vscale x 16 x i32> @llvm.vp.add.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 %evl) 1282 ret <vscale x 16 x i32> %v 1283} 1284 1285define <vscale x 16 x i32> @vadd_vv_nxv16i32_unmasked(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, i32 zeroext %evl) { 1286; CHECK-LABEL: vadd_vv_nxv16i32_unmasked: 1287; CHECK: # %bb.0: 1288; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma 1289; CHECK-NEXT: vadd.vv v8, v8, v16 1290; CHECK-NEXT: ret 1291 %v = call <vscale x 16 x i32> @llvm.vp.add.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl) 1292 ret <vscale x 16 x i32> %v 1293} 1294 1295define <vscale x 16 x i32> @vadd_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) { 1296; CHECK-LABEL: vadd_vx_nxv16i32: 1297; CHECK: # %bb.0: 1298; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma 1299; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t 1300; CHECK-NEXT: ret 1301 %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0 1302 %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer 1303 %v = call <vscale x 16 x i32> @llvm.vp.add.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> %m, i32 %evl) 1304 ret <vscale x 16 x i32> %v 1305} 1306 1307define <vscale x 16 x i32> @vadd_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 %b, i32 zeroext %evl) { 1308; CHECK-LABEL: vadd_vx_nxv16i32_unmasked: 1309; CHECK: # %bb.0: 1310; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma 1311; CHECK-NEXT: vadd.vx v8, v8, a0 1312; CHECK-NEXT: ret 1313 %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0 1314 %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer 1315 %v = call <vscale x 16 x i32> @llvm.vp.add.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl) 1316 ret <vscale x 16 x i32> %v 1317} 1318 1319define <vscale x 16 x i32> @vadd_vi_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { 1320; CHECK-LABEL: vadd_vi_nxv16i32: 1321; CHECK: # %bb.0: 1322; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma 1323; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 1324; CHECK-NEXT: ret 1325 %v = call <vscale x 16 x i32> @llvm.vp.add.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> %m, i32 %evl) 1326 ret <vscale x 16 x i32> %v 1327} 1328 1329define <vscale x 16 x i32> @vadd_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) { 1330; CHECK-LABEL: vadd_vi_nxv16i32_unmasked: 1331; CHECK: # %bb.0: 1332; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma 1333; CHECK-NEXT: vadd.vi v8, v8, -1 1334; CHECK-NEXT: ret 1335 %v = call <vscale x 16 x i32> @llvm.vp.add.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl) 1336 ret <vscale x 16 x i32> %v 1337} 1338 1339; Test that split-legalization works then the mask needs manual splitting. 1340 1341declare <vscale x 32 x i32> @llvm.vp.add.nxv32i32(<vscale x 32 x i32>, <vscale x 32 x i32>, <vscale x 32 x i1>, i32) 1342 1343define <vscale x 32 x i32> @vadd_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) { 1344; CHECK-LABEL: vadd_vi_nxv32i32: 1345; CHECK: # %bb.0: 1346; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma 1347; CHECK-NEXT: vmv1r.v v24, v0 1348; CHECK-NEXT: csrr a1, vlenb 1349; CHECK-NEXT: srli a2, a1, 2 1350; CHECK-NEXT: slli a1, a1, 1 1351; CHECK-NEXT: vslidedown.vx v0, v0, a2 1352; CHECK-NEXT: sub a2, a0, a1 1353; CHECK-NEXT: sltu a3, a0, a2 1354; CHECK-NEXT: addi a3, a3, -1 1355; CHECK-NEXT: and a2, a3, a2 1356; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma 1357; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t 1358; CHECK-NEXT: bltu a0, a1, .LBB118_2 1359; CHECK-NEXT: # %bb.1: 1360; CHECK-NEXT: mv a0, a1 1361; CHECK-NEXT: .LBB118_2: 1362; CHECK-NEXT: vmv1r.v v0, v24 1363; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma 1364; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 1365; CHECK-NEXT: ret 1366 %v = call <vscale x 32 x i32> @llvm.vp.add.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> %m, i32 %evl) 1367 ret <vscale x 32 x i32> %v 1368} 1369 1370define <vscale x 32 x i32> @vadd_vi_nxv32i32_unmasked(<vscale x 32 x i32> %va, i32 zeroext %evl) { 1371; CHECK-LABEL: vadd_vi_nxv32i32_unmasked: 1372; CHECK: # %bb.0: 1373; CHECK-NEXT: csrr a1, vlenb 1374; CHECK-NEXT: slli a1, a1, 1 1375; CHECK-NEXT: sub a2, a0, a1 1376; CHECK-NEXT: sltu a3, a0, a2 1377; CHECK-NEXT: addi a3, a3, -1 1378; CHECK-NEXT: and a2, a3, a2 1379; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma 1380; CHECK-NEXT: vadd.vi v16, v16, -1 1381; CHECK-NEXT: bltu a0, a1, .LBB119_2 1382; CHECK-NEXT: # %bb.1: 1383; CHECK-NEXT: mv a0, a1 1384; CHECK-NEXT: .LBB119_2: 1385; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma 1386; CHECK-NEXT: vadd.vi v8, v8, -1 1387; CHECK-NEXT: ret 1388 %v = call <vscale x 32 x i32> @llvm.vp.add.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl) 1389 ret <vscale x 32 x i32> %v 1390} 1391 1392; Test splitting when the %evl is a constant (albeit an unknown one). 1393 1394declare i32 @llvm.vscale.i32() 1395 1396; FIXME: The upper half of the operation is doing nothing. 1397; FIXME: The branches comparing vscale vs. vscale should be constant-foldable. 1398 1399define <vscale x 32 x i32> @vadd_vi_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m) { 1400; CHECK-LABEL: vadd_vi_nxv32i32_evl_nx8: 1401; CHECK: # %bb.0: 1402; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma 1403; CHECK-NEXT: vmv1r.v v24, v0 1404; CHECK-NEXT: csrr a0, vlenb 1405; CHECK-NEXT: srli a2, a0, 2 1406; CHECK-NEXT: slli a1, a0, 1 1407; CHECK-NEXT: vslidedown.vx v0, v0, a2 1408; CHECK-NEXT: sub a2, a0, a1 1409; CHECK-NEXT: sltu a3, a0, a2 1410; CHECK-NEXT: addi a3, a3, -1 1411; CHECK-NEXT: and a2, a3, a2 1412; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma 1413; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t 1414; CHECK-NEXT: bltu a0, a1, .LBB120_2 1415; CHECK-NEXT: # %bb.1: 1416; CHECK-NEXT: mv a0, a1 1417; CHECK-NEXT: .LBB120_2: 1418; CHECK-NEXT: vmv1r.v v0, v24 1419; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma 1420; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 1421; CHECK-NEXT: ret 1422 %evl = call i32 @llvm.vscale.i32() 1423 %evl0 = mul i32 %evl, 8 1424 %v = call <vscale x 32 x i32> @llvm.vp.add.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> %m, i32 %evl0) 1425 ret <vscale x 32 x i32> %v 1426} 1427 1428; FIXME: The upper half of the operation is doing nothing but we don't catch 1429; that on RV64; we issue a usubsat(and (vscale x 16), 0xffffffff, vscale x 16) 1430; (the "original" %evl is the "and", due to known-bits issues with legalizing 1431; the i32 %evl to i64) and this isn't detected as 0. 1432; This could be resolved in the future with more detailed KnownBits analysis 1433; for ISD::VSCALE. 1434 1435define <vscale x 32 x i32> @vadd_vi_nxv32i32_evl_nx16(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m) { 1436; RV32-LABEL: vadd_vi_nxv32i32_evl_nx16: 1437; RV32: # %bb.0: 1438; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma 1439; RV32-NEXT: vadd.vi v8, v8, -1, v0.t 1440; RV32-NEXT: ret 1441; 1442; RV64-LABEL: vadd_vi_nxv32i32_evl_nx16: 1443; RV64: # %bb.0: 1444; RV64-NEXT: csrr a0, vlenb 1445; RV64-NEXT: srli a0, a0, 2 1446; RV64-NEXT: vsetvli a1, zero, e8, mf2, ta, ma 1447; RV64-NEXT: vslidedown.vx v24, v0, a0 1448; RV64-NEXT: vsetvli a0, zero, e32, m8, ta, ma 1449; RV64-NEXT: vadd.vi v8, v8, -1, v0.t 1450; RV64-NEXT: vmv1r.v v0, v24 1451; RV64-NEXT: vsetivli zero, 0, e32, m8, ta, ma 1452; RV64-NEXT: vadd.vi v16, v16, -1, v0.t 1453; RV64-NEXT: ret 1454 %evl = call i32 @llvm.vscale.i32() 1455 %evl0 = mul i32 %evl, 16 1456 %v = call <vscale x 32 x i32> @llvm.vp.add.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> %m, i32 %evl0) 1457 ret <vscale x 32 x i32> %v 1458} 1459 1460declare <vscale x 1 x i64> @llvm.vp.add.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i32) 1461 1462define <vscale x 1 x i64> @vadd_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { 1463; CHECK-LABEL: vadd_vv_nxv1i64: 1464; CHECK: # %bb.0: 1465; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma 1466; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t 1467; CHECK-NEXT: ret 1468 %v = call <vscale x 1 x i64> @llvm.vp.add.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 %evl) 1469 ret <vscale x 1 x i64> %v 1470} 1471 1472define <vscale x 1 x i64> @vadd_vv_nxv1i64_unmasked(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, i32 zeroext %evl) { 1473; CHECK-LABEL: vadd_vv_nxv1i64_unmasked: 1474; CHECK: # %bb.0: 1475; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma 1476; CHECK-NEXT: vadd.vv v8, v8, v9 1477; CHECK-NEXT: ret 1478 %v = call <vscale x 1 x i64> @llvm.vp.add.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl) 1479 ret <vscale x 1 x i64> %v 1480} 1481 1482define <vscale x 1 x i64> @vadd_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { 1483; RV32-LABEL: vadd_vx_nxv1i64: 1484; RV32: # %bb.0: 1485; RV32-NEXT: addi sp, sp, -16 1486; RV32-NEXT: .cfi_def_cfa_offset 16 1487; RV32-NEXT: sw a0, 8(sp) 1488; RV32-NEXT: sw a1, 12(sp) 1489; RV32-NEXT: addi a0, sp, 8 1490; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma 1491; RV32-NEXT: vlse64.v v9, (a0), zero 1492; RV32-NEXT: vadd.vv v8, v8, v9, v0.t 1493; RV32-NEXT: addi sp, sp, 16 1494; RV32-NEXT: .cfi_def_cfa_offset 0 1495; RV32-NEXT: ret 1496; 1497; RV64-LABEL: vadd_vx_nxv1i64: 1498; RV64: # %bb.0: 1499; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma 1500; RV64-NEXT: vadd.vx v8, v8, a0, v0.t 1501; RV64-NEXT: ret 1502 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 1503 %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer 1504 %v = call <vscale x 1 x i64> @llvm.vp.add.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl) 1505 ret <vscale x 1 x i64> %v 1506} 1507 1508define <vscale x 1 x i64> @vadd_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) { 1509; RV32-LABEL: vadd_vx_nxv1i64_unmasked: 1510; RV32: # %bb.0: 1511; RV32-NEXT: addi sp, sp, -16 1512; RV32-NEXT: .cfi_def_cfa_offset 16 1513; RV32-NEXT: sw a0, 8(sp) 1514; RV32-NEXT: sw a1, 12(sp) 1515; RV32-NEXT: addi a0, sp, 8 1516; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma 1517; RV32-NEXT: vlse64.v v9, (a0), zero 1518; RV32-NEXT: vadd.vv v8, v8, v9 1519; RV32-NEXT: addi sp, sp, 16 1520; RV32-NEXT: .cfi_def_cfa_offset 0 1521; RV32-NEXT: ret 1522; 1523; RV64-LABEL: vadd_vx_nxv1i64_unmasked: 1524; RV64: # %bb.0: 1525; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma 1526; RV64-NEXT: vadd.vx v8, v8, a0 1527; RV64-NEXT: ret 1528 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 1529 %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer 1530 %v = call <vscale x 1 x i64> @llvm.vp.add.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl) 1531 ret <vscale x 1 x i64> %v 1532} 1533 1534define <vscale x 1 x i64> @vadd_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) { 1535; CHECK-LABEL: vadd_vi_nxv1i64: 1536; CHECK: # %bb.0: 1537; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma 1538; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 1539; CHECK-NEXT: ret 1540 %v = call <vscale x 1 x i64> @llvm.vp.add.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> %m, i32 %evl) 1541 ret <vscale x 1 x i64> %v 1542} 1543 1544define <vscale x 1 x i64> @vadd_vi_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) { 1545; CHECK-LABEL: vadd_vi_nxv1i64_unmasked: 1546; CHECK: # %bb.0: 1547; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma 1548; CHECK-NEXT: vadd.vi v8, v8, -1 1549; CHECK-NEXT: ret 1550 %v = call <vscale x 1 x i64> @llvm.vp.add.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl) 1551 ret <vscale x 1 x i64> %v 1552} 1553 1554declare <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, i32) 1555 1556define <vscale x 2 x i64> @vadd_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { 1557; CHECK-LABEL: vadd_vv_nxv2i64: 1558; CHECK: # %bb.0: 1559; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma 1560; CHECK-NEXT: vadd.vv v8, v8, v10, v0.t 1561; CHECK-NEXT: ret 1562 %v = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 %evl) 1563 ret <vscale x 2 x i64> %v 1564} 1565 1566define <vscale x 2 x i64> @vadd_vv_nxv2i64_unmasked(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, i32 zeroext %evl) { 1567; CHECK-LABEL: vadd_vv_nxv2i64_unmasked: 1568; CHECK: # %bb.0: 1569; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma 1570; CHECK-NEXT: vadd.vv v8, v8, v10 1571; CHECK-NEXT: ret 1572 %v = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl) 1573 ret <vscale x 2 x i64> %v 1574} 1575 1576define <vscale x 2 x i64> @vadd_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { 1577; RV32-LABEL: vadd_vx_nxv2i64: 1578; RV32: # %bb.0: 1579; RV32-NEXT: addi sp, sp, -16 1580; RV32-NEXT: .cfi_def_cfa_offset 16 1581; RV32-NEXT: sw a0, 8(sp) 1582; RV32-NEXT: sw a1, 12(sp) 1583; RV32-NEXT: addi a0, sp, 8 1584; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma 1585; RV32-NEXT: vlse64.v v10, (a0), zero 1586; RV32-NEXT: vadd.vv v8, v8, v10, v0.t 1587; RV32-NEXT: addi sp, sp, 16 1588; RV32-NEXT: .cfi_def_cfa_offset 0 1589; RV32-NEXT: ret 1590; 1591; RV64-LABEL: vadd_vx_nxv2i64: 1592; RV64: # %bb.0: 1593; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma 1594; RV64-NEXT: vadd.vx v8, v8, a0, v0.t 1595; RV64-NEXT: ret 1596 %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 1597 %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer 1598 %v = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl) 1599 ret <vscale x 2 x i64> %v 1600} 1601 1602define <vscale x 2 x i64> @vadd_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) { 1603; RV32-LABEL: vadd_vx_nxv2i64_unmasked: 1604; RV32: # %bb.0: 1605; RV32-NEXT: addi sp, sp, -16 1606; RV32-NEXT: .cfi_def_cfa_offset 16 1607; RV32-NEXT: sw a0, 8(sp) 1608; RV32-NEXT: sw a1, 12(sp) 1609; RV32-NEXT: addi a0, sp, 8 1610; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma 1611; RV32-NEXT: vlse64.v v10, (a0), zero 1612; RV32-NEXT: vadd.vv v8, v8, v10 1613; RV32-NEXT: addi sp, sp, 16 1614; RV32-NEXT: .cfi_def_cfa_offset 0 1615; RV32-NEXT: ret 1616; 1617; RV64-LABEL: vadd_vx_nxv2i64_unmasked: 1618; RV64: # %bb.0: 1619; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma 1620; RV64-NEXT: vadd.vx v8, v8, a0 1621; RV64-NEXT: ret 1622 %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 1623 %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer 1624 %v = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl) 1625 ret <vscale x 2 x i64> %v 1626} 1627 1628define <vscale x 2 x i64> @vadd_vi_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) { 1629; CHECK-LABEL: vadd_vi_nxv2i64: 1630; CHECK: # %bb.0: 1631; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma 1632; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 1633; CHECK-NEXT: ret 1634 %v = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> %m, i32 %evl) 1635 ret <vscale x 2 x i64> %v 1636} 1637 1638define <vscale x 2 x i64> @vadd_vi_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) { 1639; CHECK-LABEL: vadd_vi_nxv2i64_unmasked: 1640; CHECK: # %bb.0: 1641; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma 1642; CHECK-NEXT: vadd.vi v8, v8, -1 1643; CHECK-NEXT: ret 1644 %v = call <vscale x 2 x i64> @llvm.vp.add.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl) 1645 ret <vscale x 2 x i64> %v 1646} 1647 1648declare <vscale x 4 x i64> @llvm.vp.add.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i1>, i32) 1649 1650define <vscale x 4 x i64> @vadd_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { 1651; CHECK-LABEL: vadd_vv_nxv4i64: 1652; CHECK: # %bb.0: 1653; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma 1654; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t 1655; CHECK-NEXT: ret 1656 %v = call <vscale x 4 x i64> @llvm.vp.add.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 %evl) 1657 ret <vscale x 4 x i64> %v 1658} 1659 1660define <vscale x 4 x i64> @vadd_vv_nxv4i64_unmasked(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, i32 zeroext %evl) { 1661; CHECK-LABEL: vadd_vv_nxv4i64_unmasked: 1662; CHECK: # %bb.0: 1663; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma 1664; CHECK-NEXT: vadd.vv v8, v8, v12 1665; CHECK-NEXT: ret 1666 %v = call <vscale x 4 x i64> @llvm.vp.add.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl) 1667 ret <vscale x 4 x i64> %v 1668} 1669 1670define <vscale x 4 x i64> @vadd_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { 1671; RV32-LABEL: vadd_vx_nxv4i64: 1672; RV32: # %bb.0: 1673; RV32-NEXT: addi sp, sp, -16 1674; RV32-NEXT: .cfi_def_cfa_offset 16 1675; RV32-NEXT: sw a0, 8(sp) 1676; RV32-NEXT: sw a1, 12(sp) 1677; RV32-NEXT: addi a0, sp, 8 1678; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma 1679; RV32-NEXT: vlse64.v v12, (a0), zero 1680; RV32-NEXT: vadd.vv v8, v8, v12, v0.t 1681; RV32-NEXT: addi sp, sp, 16 1682; RV32-NEXT: .cfi_def_cfa_offset 0 1683; RV32-NEXT: ret 1684; 1685; RV64-LABEL: vadd_vx_nxv4i64: 1686; RV64: # %bb.0: 1687; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma 1688; RV64-NEXT: vadd.vx v8, v8, a0, v0.t 1689; RV64-NEXT: ret 1690 %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 1691 %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer 1692 %v = call <vscale x 4 x i64> @llvm.vp.add.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl) 1693 ret <vscale x 4 x i64> %v 1694} 1695 1696define <vscale x 4 x i64> @vadd_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) { 1697; RV32-LABEL: vadd_vx_nxv4i64_unmasked: 1698; RV32: # %bb.0: 1699; RV32-NEXT: addi sp, sp, -16 1700; RV32-NEXT: .cfi_def_cfa_offset 16 1701; RV32-NEXT: sw a0, 8(sp) 1702; RV32-NEXT: sw a1, 12(sp) 1703; RV32-NEXT: addi a0, sp, 8 1704; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma 1705; RV32-NEXT: vlse64.v v12, (a0), zero 1706; RV32-NEXT: vadd.vv v8, v8, v12 1707; RV32-NEXT: addi sp, sp, 16 1708; RV32-NEXT: .cfi_def_cfa_offset 0 1709; RV32-NEXT: ret 1710; 1711; RV64-LABEL: vadd_vx_nxv4i64_unmasked: 1712; RV64: # %bb.0: 1713; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma 1714; RV64-NEXT: vadd.vx v8, v8, a0 1715; RV64-NEXT: ret 1716 %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 1717 %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer 1718 %v = call <vscale x 4 x i64> @llvm.vp.add.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl) 1719 ret <vscale x 4 x i64> %v 1720} 1721 1722define <vscale x 4 x i64> @vadd_vi_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) { 1723; CHECK-LABEL: vadd_vi_nxv4i64: 1724; CHECK: # %bb.0: 1725; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma 1726; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 1727; CHECK-NEXT: ret 1728 %v = call <vscale x 4 x i64> @llvm.vp.add.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> %m, i32 %evl) 1729 ret <vscale x 4 x i64> %v 1730} 1731 1732define <vscale x 4 x i64> @vadd_vi_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) { 1733; CHECK-LABEL: vadd_vi_nxv4i64_unmasked: 1734; CHECK: # %bb.0: 1735; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma 1736; CHECK-NEXT: vadd.vi v8, v8, -1 1737; CHECK-NEXT: ret 1738 %v = call <vscale x 4 x i64> @llvm.vp.add.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl) 1739 ret <vscale x 4 x i64> %v 1740} 1741 1742declare <vscale x 8 x i64> @llvm.vp.add.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i1>, i32) 1743 1744define <vscale x 8 x i64> @vadd_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { 1745; CHECK-LABEL: vadd_vv_nxv8i64: 1746; CHECK: # %bb.0: 1747; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma 1748; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t 1749; CHECK-NEXT: ret 1750 %v = call <vscale x 8 x i64> @llvm.vp.add.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 %evl) 1751 ret <vscale x 8 x i64> %v 1752} 1753 1754define <vscale x 8 x i64> @vadd_vv_nxv8i64_unmasked(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, i32 zeroext %evl) { 1755; CHECK-LABEL: vadd_vv_nxv8i64_unmasked: 1756; CHECK: # %bb.0: 1757; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma 1758; CHECK-NEXT: vadd.vv v8, v8, v16 1759; CHECK-NEXT: ret 1760 %v = call <vscale x 8 x i64> @llvm.vp.add.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl) 1761 ret <vscale x 8 x i64> %v 1762} 1763 1764define <vscale x 8 x i64> @vadd_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { 1765; RV32-LABEL: vadd_vx_nxv8i64: 1766; RV32: # %bb.0: 1767; RV32-NEXT: addi sp, sp, -16 1768; RV32-NEXT: .cfi_def_cfa_offset 16 1769; RV32-NEXT: sw a0, 8(sp) 1770; RV32-NEXT: sw a1, 12(sp) 1771; RV32-NEXT: addi a0, sp, 8 1772; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma 1773; RV32-NEXT: vlse64.v v16, (a0), zero 1774; RV32-NEXT: vadd.vv v8, v8, v16, v0.t 1775; RV32-NEXT: addi sp, sp, 16 1776; RV32-NEXT: .cfi_def_cfa_offset 0 1777; RV32-NEXT: ret 1778; 1779; RV64-LABEL: vadd_vx_nxv8i64: 1780; RV64: # %bb.0: 1781; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma 1782; RV64-NEXT: vadd.vx v8, v8, a0, v0.t 1783; RV64-NEXT: ret 1784 %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 1785 %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 1786 %v = call <vscale x 8 x i64> @llvm.vp.add.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl) 1787 ret <vscale x 8 x i64> %v 1788} 1789 1790define <vscale x 8 x i64> @vadd_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) { 1791; RV32-LABEL: vadd_vx_nxv8i64_unmasked: 1792; RV32: # %bb.0: 1793; RV32-NEXT: addi sp, sp, -16 1794; RV32-NEXT: .cfi_def_cfa_offset 16 1795; RV32-NEXT: sw a0, 8(sp) 1796; RV32-NEXT: sw a1, 12(sp) 1797; RV32-NEXT: addi a0, sp, 8 1798; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma 1799; RV32-NEXT: vlse64.v v16, (a0), zero 1800; RV32-NEXT: vadd.vv v8, v8, v16 1801; RV32-NEXT: addi sp, sp, 16 1802; RV32-NEXT: .cfi_def_cfa_offset 0 1803; RV32-NEXT: ret 1804; 1805; RV64-LABEL: vadd_vx_nxv8i64_unmasked: 1806; RV64: # %bb.0: 1807; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma 1808; RV64-NEXT: vadd.vx v8, v8, a0 1809; RV64-NEXT: ret 1810 %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 1811 %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 1812 %v = call <vscale x 8 x i64> @llvm.vp.add.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl) 1813 ret <vscale x 8 x i64> %v 1814} 1815 1816define <vscale x 8 x i64> @vadd_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) { 1817; CHECK-LABEL: vadd_vi_nxv8i64: 1818; CHECK: # %bb.0: 1819; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma 1820; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t 1821; CHECK-NEXT: ret 1822 %v = call <vscale x 8 x i64> @llvm.vp.add.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> %m, i32 %evl) 1823 ret <vscale x 8 x i64> %v 1824} 1825 1826define <vscale x 8 x i64> @vadd_vi_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) { 1827; CHECK-LABEL: vadd_vi_nxv8i64_unmasked: 1828; CHECK: # %bb.0: 1829; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma 1830; CHECK-NEXT: vadd.vi v8, v8, -1 1831; CHECK-NEXT: ret 1832 %v = call <vscale x 8 x i64> @llvm.vp.add.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl) 1833 ret <vscale x 8 x i64> %v 1834} 1835