xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/ushl_sat_vec.ll (revision 00d93def778afa7fd117e615e4f6fb7645e25f49) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
3
4declare <2 x i64> @llvm.ushl.sat.v2i64(<2 x i64>, <2 x i64>)
5declare <4 x i32> @llvm.ushl.sat.v4i32(<4 x i32>, <4 x i32>)
6declare <8 x i16> @llvm.ushl.sat.v8i16(<8 x i16>, <8 x i16>)
7declare <16 x i8> @llvm.ushl.sat.v16i8(<16 x i8>, <16 x i8>)
8
9define <2 x i64> @vec_v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
10; CHECK-LABEL: vec_v2i64:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
13; CHECK-NEXT:    vsll.vv v10, v8, v9
14; CHECK-NEXT:    vsrl.vv v9, v10, v9
15; CHECK-NEXT:    vmsne.vv v0, v8, v9
16; CHECK-NEXT:    vmerge.vim v8, v10, -1, v0
17; CHECK-NEXT:    ret
18  %tmp = call <2 x i64> @llvm.ushl.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
19  ret <2 x i64> %tmp
20}
21
22define <4 x i32> @vec_v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
23; CHECK-LABEL: vec_v4i32:
24; CHECK:       # %bb.0:
25; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
26; CHECK-NEXT:    vsll.vv v10, v8, v9
27; CHECK-NEXT:    vsrl.vv v9, v10, v9
28; CHECK-NEXT:    vmsne.vv v0, v8, v9
29; CHECK-NEXT:    vmerge.vim v8, v10, -1, v0
30; CHECK-NEXT:    ret
31  %tmp = call <4 x i32> @llvm.ushl.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
32  ret <4 x i32> %tmp
33}
34
35define <8 x i16> @vec_v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
36; CHECK-LABEL: vec_v8i16:
37; CHECK:       # %bb.0:
38; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
39; CHECK-NEXT:    vsll.vv v10, v8, v9
40; CHECK-NEXT:    vsrl.vv v9, v10, v9
41; CHECK-NEXT:    vmsne.vv v0, v8, v9
42; CHECK-NEXT:    vmerge.vim v8, v10, -1, v0
43; CHECK-NEXT:    ret
44  %tmp = call <8 x i16> @llvm.ushl.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
45  ret <8 x i16> %tmp
46}
47
48define <16 x i8> @vec_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
49; CHECK-LABEL: vec_v16i8:
50; CHECK:       # %bb.0:
51; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
52; CHECK-NEXT:    vsll.vv v10, v8, v9
53; CHECK-NEXT:    vsrl.vv v9, v10, v9
54; CHECK-NEXT:    vmsne.vv v0, v8, v9
55; CHECK-NEXT:    vmerge.vim v8, v10, -1, v0
56; CHECK-NEXT:    ret
57  %tmp = call <16 x i8> @llvm.ushl.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
58  ret <16 x i8> %tmp
59}
60
61declare <vscale x 2 x i64> @llvm.ushl.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
62declare <vscale x 4 x i32> @llvm.ushl.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
63declare <vscale x 8 x i16> @llvm.ushl.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
64declare <vscale x 16 x i8> @llvm.ushl.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
65
66define <vscale x 2 x i64> @vec_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) nounwind {
67; CHECK-LABEL: vec_nxv2i64:
68; CHECK:       # %bb.0:
69; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
70; CHECK-NEXT:    vsll.vv v12, v8, v10
71; CHECK-NEXT:    vsrl.vv v10, v12, v10
72; CHECK-NEXT:    vmsne.vv v0, v8, v10
73; CHECK-NEXT:    vmerge.vim v8, v12, -1, v0
74; CHECK-NEXT:    ret
75  %tmp = call <vscale x 2 x i64> @llvm.ushl.sat.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y)
76  ret <vscale x 2 x i64> %tmp
77}
78
79define <vscale x 4 x i32> @vec_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) nounwind {
80; CHECK-LABEL: vec_nxv4i32:
81; CHECK:       # %bb.0:
82; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
83; CHECK-NEXT:    vsll.vv v12, v8, v10
84; CHECK-NEXT:    vsrl.vv v10, v12, v10
85; CHECK-NEXT:    vmsne.vv v0, v8, v10
86; CHECK-NEXT:    vmerge.vim v8, v12, -1, v0
87; CHECK-NEXT:    ret
88  %tmp = call <vscale x 4 x i32> @llvm.ushl.sat.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)
89  ret <vscale x 4 x i32> %tmp
90}
91
92define <vscale x 8 x i16> @vec_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) nounwind {
93; CHECK-LABEL: vec_nxv8i16:
94; CHECK:       # %bb.0:
95; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
96; CHECK-NEXT:    vsll.vv v12, v8, v10
97; CHECK-NEXT:    vsrl.vv v10, v12, v10
98; CHECK-NEXT:    vmsne.vv v0, v8, v10
99; CHECK-NEXT:    vmerge.vim v8, v12, -1, v0
100; CHECK-NEXT:    ret
101  %tmp = call <vscale x 8 x i16> @llvm.ushl.sat.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)
102  ret <vscale x 8 x i16> %tmp
103}
104
105define <vscale x 16 x i8> @vec_nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) nounwind {
106; CHECK-LABEL: vec_nxv16i8:
107; CHECK:       # %bb.0:
108; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
109; CHECK-NEXT:    vsll.vv v12, v8, v10
110; CHECK-NEXT:    vsrl.vv v10, v12, v10
111; CHECK-NEXT:    vmsne.vv v0, v8, v10
112; CHECK-NEXT:    vmerge.vim v8, v12, -1, v0
113; CHECK-NEXT:    ret
114  %tmp = call <vscale x 16 x i8> @llvm.ushl.sat.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)
115  ret <vscale x 16 x i8> %tmp
116}
117