xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/trunc-select-to-max-usat.ll (revision d8c9d583930befff3e0d78a5ab785d33a8e95f0f) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
3; RUN: llc < %s -mtriple=riscv64 -mattr=+zve64x,+zvl128b | FileCheck %s
4
5define <4 x i8> @test_v4i16_v4i8(<4 x i16> %x) {
6; CHECK-LABEL: test_v4i16_v4i8:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
9; CHECK-NEXT:    vmax.vx v8, v8, zero
10; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
11; CHECK-NEXT:    vnclipu.wi v8, v8, 0
12; CHECK-NEXT:    ret
13  %a = icmp sgt <4 x i16> %x, zeroinitializer
14  %b = sext <4 x i1> %a to <4 x i16>
15  %c = icmp ult <4 x i16> %x, splat (i16 256)
16  %d = select <4 x i1> %c, <4 x i16> %x, <4 x i16> %b
17  %e = trunc <4 x i16> %d to <4 x i8>
18  ret <4 x i8> %e
19}
20
21define <4 x i8> @test_v4i32_v4i8(<4 x i32> %x) {
22; CHECK-LABEL: test_v4i32_v4i8:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
25; CHECK-NEXT:    vmax.vx v8, v8, zero
26; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
27; CHECK-NEXT:    vnclipu.wi v8, v8, 0
28; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
29; CHECK-NEXT:    vnclipu.wi v8, v8, 0
30; CHECK-NEXT:    ret
31  %a = icmp sgt <4 x i32> %x, zeroinitializer
32  %b = sext <4 x i1> %a to <4 x i32>
33  %c = icmp ult <4 x i32> %x, splat (i32 256)
34  %d = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %b
35  %e = trunc <4 x i32> %d to <4 x i8>
36  ret <4 x i8> %e
37}
38
39define <4 x i8> @test_v4i64_v4i8(<4 x i64> %x) {
40; CHECK-LABEL: test_v4i64_v4i8:
41; CHECK:       # %bb.0:
42; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
43; CHECK-NEXT:    vmax.vx v8, v8, zero
44; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
45; CHECK-NEXT:    vnclipu.wi v10, v8, 0
46; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
47; CHECK-NEXT:    vnclipu.wi v8, v10, 0
48; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
49; CHECK-NEXT:    vnclipu.wi v8, v8, 0
50; CHECK-NEXT:    ret
51  %a = icmp sgt <4 x i64> %x, zeroinitializer
52  %b = sext <4 x i1> %a to <4 x i64>
53  %c = icmp ult <4 x i64> %x, splat (i64 256)
54  %d = select <4 x i1> %c, <4 x i64> %x, <4 x i64> %b
55  %e = trunc <4 x i64> %d to <4 x i8>
56  ret <4 x i8> %e
57}
58
59define <4 x i16> @test_v4i32_v4i16(<4 x i32> %x) {
60; CHECK-LABEL: test_v4i32_v4i16:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
63; CHECK-NEXT:    vmax.vx v8, v8, zero
64; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
65; CHECK-NEXT:    vnclipu.wi v8, v8, 0
66; CHECK-NEXT:    ret
67  %a = icmp sgt <4 x i32> %x, zeroinitializer
68  %b = sext <4 x i1> %a to <4 x i32>
69  %c = icmp ult <4 x i32> %x, splat (i32 65536)
70  %d = select <4 x i1> %c, <4 x i32> %x, <4 x i32> %b
71  %e = trunc <4 x i32> %d to <4 x i16>
72  ret <4 x i16> %e
73}
74
75define <4 x i16> @test_v4i64_v4i16(<4 x i64> %x) {
76; CHECK-LABEL: test_v4i64_v4i16:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
79; CHECK-NEXT:    vmax.vx v8, v8, zero
80; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
81; CHECK-NEXT:    vnclipu.wi v10, v8, 0
82; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
83; CHECK-NEXT:    vnclipu.wi v8, v10, 0
84; CHECK-NEXT:    ret
85  %a = icmp sgt <4 x i64> %x, zeroinitializer
86  %b = sext <4 x i1> %a to <4 x i64>
87  %c = icmp ult <4 x i64> %x, splat (i64 65536)
88  %d = select <4 x i1> %c, <4 x i64> %x, <4 x i64> %b
89  %e = trunc <4 x i64> %d to <4 x i16>
90  ret <4 x i16> %e
91}
92
93define <4 x i32> @test_v4i64_v4i32(<4 x i64> %x) {
94; CHECK-LABEL: test_v4i64_v4i32:
95; CHECK:       # %bb.0:
96; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
97; CHECK-NEXT:    vmax.vx v10, v8, zero
98; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
99; CHECK-NEXT:    vnclipu.wi v8, v10, 0
100; CHECK-NEXT:    ret
101  %a = icmp sgt <4 x i64> %x, zeroinitializer
102  %b = sext <4 x i1> %a to <4 x i64>
103  %c = icmp ult <4 x i64> %x, splat (i64 4294967296)
104  %d = select <4 x i1> %c, <4 x i64> %x, <4 x i64> %b
105  %e = trunc <4 x i64> %d to <4 x i32>
106  ret <4 x i32> %e
107}
108
109define <vscale x 4 x i8> @test_nxv4i16_nxv4i8(<vscale x 4 x i16> %x) {
110; CHECK-LABEL: test_nxv4i16_nxv4i8:
111; CHECK:       # %bb.0:
112; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
113; CHECK-NEXT:    vmax.vx v8, v8, zero
114; CHECK-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
115; CHECK-NEXT:    vnclipu.wi v8, v8, 0
116; CHECK-NEXT:    ret
117  %a = icmp sgt <vscale x 4 x i16> %x, zeroinitializer
118  %b = sext <vscale x 4 x i1> %a to <vscale x 4 x i16>
119  %c = icmp ult <vscale x 4 x i16> %x, splat (i16 256)
120  %d = select <vscale x 4 x i1> %c, <vscale x 4 x i16> %x, <vscale x 4 x i16> %b
121  %e = trunc <vscale x 4 x i16> %d to <vscale x 4 x i8>
122  ret <vscale x 4 x i8> %e
123}
124
125define <vscale x 4 x i8> @test_nxv4i32_nxv4i8(<vscale x 4 x i32> %x) {
126; CHECK-LABEL: test_nxv4i32_nxv4i8:
127; CHECK:       # %bb.0:
128; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
129; CHECK-NEXT:    vmax.vx v8, v8, zero
130; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
131; CHECK-NEXT:    vnclipu.wi v10, v8, 0
132; CHECK-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
133; CHECK-NEXT:    vnclipu.wi v8, v10, 0
134; CHECK-NEXT:    ret
135  %a = icmp sgt <vscale x 4 x i32> %x, zeroinitializer
136  %b = sext <vscale x 4 x i1> %a to <vscale x 4 x i32>
137  %c = icmp ult <vscale x 4 x i32> %x, splat (i32 256)
138  %d = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %x, <vscale x 4 x i32> %b
139  %e = trunc <vscale x 4 x i32> %d to <vscale x 4 x i8>
140  ret <vscale x 4 x i8> %e
141}
142
143define <vscale x 4 x i8> @test_nxv4i64_nxv4i8(<vscale x 4 x i64> %x) {
144; CHECK-LABEL: test_nxv4i64_nxv4i8:
145; CHECK:       # %bb.0:
146; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
147; CHECK-NEXT:    vmax.vx v8, v8, zero
148; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
149; CHECK-NEXT:    vnclipu.wi v12, v8, 0
150; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
151; CHECK-NEXT:    vnclipu.wi v8, v12, 0
152; CHECK-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
153; CHECK-NEXT:    vnclipu.wi v8, v8, 0
154; CHECK-NEXT:    ret
155  %a = icmp sgt <vscale x 4 x i64> %x, zeroinitializer
156  %b = sext <vscale x 4 x i1> %a to <vscale x 4 x i64>
157  %c = icmp ult <vscale x 4 x i64> %x, splat (i64 256)
158  %d = select <vscale x 4 x i1> %c, <vscale x 4 x i64> %x, <vscale x 4 x i64> %b
159  %e = trunc <vscale x 4 x i64> %d to <vscale x 4 x i8>
160  ret <vscale x 4 x i8> %e
161}
162
163define <vscale x 4 x i16> @test_nxv4i32_nxv4i16(<vscale x 4 x i32> %x) {
164; CHECK-LABEL: test_nxv4i32_nxv4i16:
165; CHECK:       # %bb.0:
166; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
167; CHECK-NEXT:    vmax.vx v10, v8, zero
168; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
169; CHECK-NEXT:    vnclipu.wi v8, v10, 0
170; CHECK-NEXT:    ret
171  %a = icmp sgt <vscale x 4 x i32> %x, zeroinitializer
172  %b = sext <vscale x 4 x i1> %a to <vscale x 4 x i32>
173  %c = icmp ult <vscale x 4 x i32> %x, splat (i32 65536)
174  %d = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %x, <vscale x 4 x i32> %b
175  %e = trunc <vscale x 4 x i32> %d to <vscale x 4 x i16>
176  ret <vscale x 4 x i16> %e
177}
178
179define <vscale x 4 x i16> @test_nxv4i64_nxv4i16(<vscale x 4 x i64> %x) {
180; CHECK-LABEL: test_nxv4i64_nxv4i16:
181; CHECK:       # %bb.0:
182; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
183; CHECK-NEXT:    vmax.vx v8, v8, zero
184; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
185; CHECK-NEXT:    vnclipu.wi v12, v8, 0
186; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
187; CHECK-NEXT:    vnclipu.wi v8, v12, 0
188; CHECK-NEXT:    ret
189  %a = icmp sgt <vscale x 4 x i64> %x, zeroinitializer
190  %b = sext <vscale x 4 x i1> %a to <vscale x 4 x i64>
191  %c = icmp ult <vscale x 4 x i64> %x, splat (i64 65536)
192  %d = select <vscale x 4 x i1> %c, <vscale x 4 x i64> %x, <vscale x 4 x i64> %b
193  %e = trunc <vscale x 4 x i64> %d to <vscale x 4 x i16>
194  ret <vscale x 4 x i16> %e
195}
196
197define <vscale x 4 x i32> @test_nxv4i64_nxv4i32(<vscale x 4 x i64> %x) {
198; CHECK-LABEL: test_nxv4i64_nxv4i32:
199; CHECK:       # %bb.0:
200; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
201; CHECK-NEXT:    vmax.vx v12, v8, zero
202; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
203; CHECK-NEXT:    vnclipu.wi v8, v12, 0
204; CHECK-NEXT:    ret
205  %a = icmp sgt <vscale x 4 x i64> %x, zeroinitializer
206  %b = sext <vscale x 4 x i1> %a to <vscale x 4 x i64>
207  %c = icmp ult <vscale x 4 x i64> %x, splat (i64 4294967296)
208  %d = select <vscale x 4 x i1> %c, <vscale x 4 x i64> %x, <vscale x 4 x i64> %b
209  %e = trunc <vscale x 4 x i64> %d to <vscale x 4 x i32>
210  ret <vscale x 4 x i32> %e
211}
212