xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+v,+zvfh,+zvfbfmin \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s \
4; RUN:     -check-prefixes=CHECK,CHECK-RV32
5; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v,+zvfh,+zvfbfmin \
6; RUN:     -verify-machineinstrs < %s | FileCheck %s \
7; RUN:     -check-prefixes=CHECK,CHECK-RV64
8; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+v,+zvfhmin,+zvfbfmin \
9; RUN:     -verify-machineinstrs < %s | FileCheck %s \
10; RUN:     -check-prefixes=CHECK,CHECK-RV32
11; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v,+zvfhmin,+zvfbfmin \
12; RUN:     -verify-machineinstrs < %s | FileCheck %s \
13; RUN:     -check-prefixes=CHECK,CHECK-RV64
14
15declare void @llvm.experimental.vp.strided.store.nxv1i8.p0.i8(<vscale x 1 x i8>, ptr, i8, <vscale x 1 x i1>, i32)
16
17define void @strided_vpstore_nxv1i8_i8(<vscale x 1 x i8> %val, ptr %ptr, i8 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {
18; CHECK-LABEL: strided_vpstore_nxv1i8_i8:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    vsetvli zero, a2, e8, mf8, ta, ma
21; CHECK-NEXT:    vsse8.v v8, (a0), a1, v0.t
22; CHECK-NEXT:    ret
23  call void @llvm.experimental.vp.strided.store.nxv1i8.p0.i8(<vscale x 1 x i8> %val, ptr %ptr, i8 %stride, <vscale x 1 x i1> %m, i32 %evl)
24  ret void
25}
26
27declare void @llvm.experimental.vp.strided.store.nxv1i8.p0.i16(<vscale x 1 x i8>, ptr, i16, <vscale x 1 x i1>, i32)
28
29define void @strided_vpstore_nxv1i8_i16(<vscale x 1 x i8> %val, ptr %ptr, i16 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {
30; CHECK-LABEL: strided_vpstore_nxv1i8_i16:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    vsetvli zero, a2, e8, mf8, ta, ma
33; CHECK-NEXT:    vsse8.v v8, (a0), a1, v0.t
34; CHECK-NEXT:    ret
35  call void @llvm.experimental.vp.strided.store.nxv1i8.p0.i16(<vscale x 1 x i8> %val, ptr %ptr, i16 %stride, <vscale x 1 x i1> %m, i32 %evl)
36  ret void
37}
38
39declare void @llvm.experimental.vp.strided.store.nxv1i8.p0.i64(<vscale x 1 x i8>, ptr, i64, <vscale x 1 x i1>, i32)
40
41define void @strided_vpstore_nxv1i8_i64(<vscale x 1 x i8> %val, ptr %ptr, i64 signext %stride, <vscale x 1 x i1> %m, i32 zeroext %evl) {
42; CHECK-RV32-LABEL: strided_vpstore_nxv1i8_i64:
43; CHECK-RV32:       # %bb.0:
44; CHECK-RV32-NEXT:    vsetvli zero, a3, e8, mf8, ta, ma
45; CHECK-RV32-NEXT:    vsse8.v v8, (a0), a1, v0.t
46; CHECK-RV32-NEXT:    ret
47;
48; CHECK-RV64-LABEL: strided_vpstore_nxv1i8_i64:
49; CHECK-RV64:       # %bb.0:
50; CHECK-RV64-NEXT:    vsetvli zero, a2, e8, mf8, ta, ma
51; CHECK-RV64-NEXT:    vsse8.v v8, (a0), a1, v0.t
52; CHECK-RV64-NEXT:    ret
53  call void @llvm.experimental.vp.strided.store.nxv1i8.p0.i64(<vscale x 1 x i8> %val, ptr %ptr, i64 %stride, <vscale x 1 x i1> %m, i32 %evl)
54  ret void
55}
56
57declare void @llvm.experimental.vp.strided.store.nxv1i8.p0.i32(<vscale x 1 x i8>, ptr, i32, <vscale x 1 x i1>, i32)
58
59define void @strided_vpstore_nxv1i8(<vscale x 1 x i8> %val, ptr %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {
60; CHECK-LABEL: strided_vpstore_nxv1i8:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    vsetvli zero, a2, e8, mf8, ta, ma
63; CHECK-NEXT:    vsse8.v v8, (a0), a1, v0.t
64; CHECK-NEXT:    ret
65  call void @llvm.experimental.vp.strided.store.nxv1i8.p0.i32(<vscale x 1 x i8> %val, ptr %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)
66  ret void
67}
68
69declare void @llvm.experimental.vp.strided.store.nxv2i8.p0.i32(<vscale x 2 x i8>, ptr, i32, <vscale x 2 x i1>, i32)
70
71define void @strided_vpstore_nxv2i8(<vscale x 2 x i8> %val, ptr %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {
72; CHECK-LABEL: strided_vpstore_nxv2i8:
73; CHECK:       # %bb.0:
74; CHECK-NEXT:    vsetvli zero, a2, e8, mf4, ta, ma
75; CHECK-NEXT:    vsse8.v v8, (a0), a1, v0.t
76; CHECK-NEXT:    ret
77  call void @llvm.experimental.vp.strided.store.nxv2i8.p0.i32(<vscale x 2 x i8> %val, ptr %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)
78  ret void
79}
80
81declare void @llvm.experimental.vp.strided.store.nxv4i8.p0.i32(<vscale x 4 x i8>, ptr, i32, <vscale x 4 x i1>, i32)
82
83define void @strided_vpstore_nxv4i8(<vscale x 4 x i8> %val, ptr %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {
84; CHECK-LABEL: strided_vpstore_nxv4i8:
85; CHECK:       # %bb.0:
86; CHECK-NEXT:    vsetvli zero, a2, e8, mf2, ta, ma
87; CHECK-NEXT:    vsse8.v v8, (a0), a1, v0.t
88; CHECK-NEXT:    ret
89  call void @llvm.experimental.vp.strided.store.nxv4i8.p0.i32(<vscale x 4 x i8> %val, ptr %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)
90  ret void
91}
92
93declare void @llvm.experimental.vp.strided.store.nxv8i8.p0.i32(<vscale x 8 x i8>, ptr, i32, <vscale x 8 x i1>, i32)
94
95define void @strided_vpstore_nxv8i8(<vscale x 8 x i8> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {
96; CHECK-LABEL: strided_vpstore_nxv8i8:
97; CHECK:       # %bb.0:
98; CHECK-NEXT:    vsetvli zero, a2, e8, m1, ta, ma
99; CHECK-NEXT:    vsse8.v v8, (a0), a1, v0.t
100; CHECK-NEXT:    ret
101  call void @llvm.experimental.vp.strided.store.nxv8i8.p0.i32(<vscale x 8 x i8> %val, ptr %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)
102  ret void
103}
104
105define void @strided_vpstore_nxv8i8_unit_stride(<vscale x 8 x i8> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {
106; CHECK-LABEL: strided_vpstore_nxv8i8_unit_stride:
107; CHECK:       # %bb.0:
108; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
109; CHECK-NEXT:    vse8.v v8, (a0), v0.t
110; CHECK-NEXT:    ret
111  call void @llvm.experimental.vp.strided.store.nxv8i8.p0.i32(<vscale x 8 x i8> %val, ptr %ptr, i32 1, <vscale x 8 x i1> %m, i32 %evl)
112  ret void
113}
114
115declare void @llvm.experimental.vp.strided.store.nxv1i16.p0.i32(<vscale x 1 x i16>, ptr, i32, <vscale x 1 x i1>, i32)
116
117define void @strided_vpstore_nxv1i16(<vscale x 1 x i16> %val, ptr %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {
118; CHECK-LABEL: strided_vpstore_nxv1i16:
119; CHECK:       # %bb.0:
120; CHECK-NEXT:    vsetvli zero, a2, e16, mf4, ta, ma
121; CHECK-NEXT:    vsse16.v v8, (a0), a1, v0.t
122; CHECK-NEXT:    ret
123  call void @llvm.experimental.vp.strided.store.nxv1i16.p0.i32(<vscale x 1 x i16> %val, ptr %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)
124  ret void
125}
126
127declare void @llvm.experimental.vp.strided.store.nxv2i16.p0.i32(<vscale x 2 x i16>, ptr, i32, <vscale x 2 x i1>, i32)
128
129define void @strided_vpstore_nxv2i16(<vscale x 2 x i16> %val, ptr %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {
130; CHECK-LABEL: strided_vpstore_nxv2i16:
131; CHECK:       # %bb.0:
132; CHECK-NEXT:    vsetvli zero, a2, e16, mf2, ta, ma
133; CHECK-NEXT:    vsse16.v v8, (a0), a1, v0.t
134; CHECK-NEXT:    ret
135  call void @llvm.experimental.vp.strided.store.nxv2i16.p0.i32(<vscale x 2 x i16> %val, ptr %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)
136  ret void
137}
138
139declare void @llvm.experimental.vp.strided.store.nxv4i16.p0.i32(<vscale x 4 x i16>, ptr, i32, <vscale x 4 x i1>, i32)
140
141define void @strided_vpstore_nxv4i16(<vscale x 4 x i16> %val, ptr %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {
142; CHECK-LABEL: strided_vpstore_nxv4i16:
143; CHECK:       # %bb.0:
144; CHECK-NEXT:    vsetvli zero, a2, e16, m1, ta, ma
145; CHECK-NEXT:    vsse16.v v8, (a0), a1, v0.t
146; CHECK-NEXT:    ret
147  call void @llvm.experimental.vp.strided.store.nxv4i16.p0.i32(<vscale x 4 x i16> %val, ptr %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)
148  ret void
149}
150
151define void @strided_vpstore_nxv4i16_unit_stride(<vscale x 4 x i16> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
152; CHECK-LABEL: strided_vpstore_nxv4i16_unit_stride:
153; CHECK:       # %bb.0:
154; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
155; CHECK-NEXT:    vse16.v v8, (a0), v0.t
156; CHECK-NEXT:    ret
157  call void @llvm.experimental.vp.strided.store.nxv4i16.p0.i32(<vscale x 4 x i16> %val, ptr %ptr, i32 2, <vscale x 4 x i1> %m, i32 %evl)
158  ret void
159}
160
161declare void @llvm.experimental.vp.strided.store.nxv8i16.p0.i32(<vscale x 8 x i16>, ptr, i32, <vscale x 8 x i1>, i32)
162
163define void @strided_vpstore_nxv8i16(<vscale x 8 x i16> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {
164; CHECK-LABEL: strided_vpstore_nxv8i16:
165; CHECK:       # %bb.0:
166; CHECK-NEXT:    vsetvli zero, a2, e16, m2, ta, ma
167; CHECK-NEXT:    vsse16.v v8, (a0), a1, v0.t
168; CHECK-NEXT:    ret
169  call void @llvm.experimental.vp.strided.store.nxv8i16.p0.i32(<vscale x 8 x i16> %val, ptr %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)
170  ret void
171}
172
173declare void @llvm.experimental.vp.strided.store.nxv1i32.p0.i32(<vscale x 1 x i32>, ptr, i32, <vscale x 1 x i1>, i32)
174
175define void @strided_vpstore_nxv1i32(<vscale x 1 x i32> %val, ptr %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {
176; CHECK-LABEL: strided_vpstore_nxv1i32:
177; CHECK:       # %bb.0:
178; CHECK-NEXT:    vsetvli zero, a2, e32, mf2, ta, ma
179; CHECK-NEXT:    vsse32.v v8, (a0), a1, v0.t
180; CHECK-NEXT:    ret
181  call void @llvm.experimental.vp.strided.store.nxv1i32.p0.i32(<vscale x 1 x i32> %val, ptr %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)
182  ret void
183}
184
185declare void @llvm.experimental.vp.strided.store.nxv2i32.p0.i32(<vscale x 2 x i32>, ptr, i32, <vscale x 2 x i1>, i32)
186
187define void @strided_vpstore_nxv2i32(<vscale x 2 x i32> %val, ptr %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {
188; CHECK-LABEL: strided_vpstore_nxv2i32:
189; CHECK:       # %bb.0:
190; CHECK-NEXT:    vsetvli zero, a2, e32, m1, ta, ma
191; CHECK-NEXT:    vsse32.v v8, (a0), a1, v0.t
192; CHECK-NEXT:    ret
193  call void @llvm.experimental.vp.strided.store.nxv2i32.p0.i32(<vscale x 2 x i32> %val, ptr %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)
194  ret void
195}
196
197declare void @llvm.experimental.vp.strided.store.nxv4i32.p0.i32(<vscale x 4 x i32>, ptr, i32, <vscale x 4 x i1>, i32)
198
199define void @strided_vpstore_nxv4i32(<vscale x 4 x i32> %val, ptr %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {
200; CHECK-LABEL: strided_vpstore_nxv4i32:
201; CHECK:       # %bb.0:
202; CHECK-NEXT:    vsetvli zero, a2, e32, m2, ta, ma
203; CHECK-NEXT:    vsse32.v v8, (a0), a1, v0.t
204; CHECK-NEXT:    ret
205  call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i32(<vscale x 4 x i32> %val, ptr %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)
206  ret void
207}
208
209define void @strided_vpstore_nxv4i32_unit_stride(<vscale x 4 x i32> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
210; CHECK-LABEL: strided_vpstore_nxv4i32_unit_stride:
211; CHECK:       # %bb.0:
212; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
213; CHECK-NEXT:    vse32.v v8, (a0), v0.t
214; CHECK-NEXT:    ret
215  call void @llvm.experimental.vp.strided.store.nxv4i32.p0.i32(<vscale x 4 x i32> %val, ptr %ptr, i32 4, <vscale x 4 x i1> %m, i32 %evl)
216  ret void
217}
218
219declare void @llvm.experimental.vp.strided.store.nxv8i32.p0.i32(<vscale x 8 x i32>, ptr, i32, <vscale x 8 x i1>, i32)
220
221define void @strided_vpstore_nxv8i32(<vscale x 8 x i32> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {
222; CHECK-LABEL: strided_vpstore_nxv8i32:
223; CHECK:       # %bb.0:
224; CHECK-NEXT:    vsetvli zero, a2, e32, m4, ta, ma
225; CHECK-NEXT:    vsse32.v v8, (a0), a1, v0.t
226; CHECK-NEXT:    ret
227  call void @llvm.experimental.vp.strided.store.nxv8i32.p0.i32(<vscale x 8 x i32> %val, ptr %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)
228  ret void
229}
230
231declare void @llvm.experimental.vp.strided.store.nxv1i64.p0.i32(<vscale x 1 x i64>, ptr, i32, <vscale x 1 x i1>, i32)
232
233define void @strided_vpstore_nxv1i64(<vscale x 1 x i64> %val, ptr %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {
234; CHECK-LABEL: strided_vpstore_nxv1i64:
235; CHECK:       # %bb.0:
236; CHECK-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
237; CHECK-NEXT:    vsse64.v v8, (a0), a1, v0.t
238; CHECK-NEXT:    ret
239  call void @llvm.experimental.vp.strided.store.nxv1i64.p0.i32(<vscale x 1 x i64> %val, ptr %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)
240  ret void
241}
242
243define void @strided_vpstore_nxv1i64_unit_stride(<vscale x 1 x i64> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {
244; CHECK-LABEL: strided_vpstore_nxv1i64_unit_stride:
245; CHECK:       # %bb.0:
246; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
247; CHECK-NEXT:    vse64.v v8, (a0), v0.t
248; CHECK-NEXT:    ret
249  call void @llvm.experimental.vp.strided.store.nxv1i64.p0.i32(<vscale x 1 x i64> %val, ptr %ptr, i32 8, <vscale x 1 x i1> %m, i32 %evl)
250  ret void
251}
252
253declare void @llvm.experimental.vp.strided.store.nxv2i64.p0.i32(<vscale x 2 x i64>, ptr, i32, <vscale x 2 x i1>, i32)
254
255define void @strided_vpstore_nxv2i64(<vscale x 2 x i64> %val, ptr %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {
256; CHECK-LABEL: strided_vpstore_nxv2i64:
257; CHECK:       # %bb.0:
258; CHECK-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
259; CHECK-NEXT:    vsse64.v v8, (a0), a1, v0.t
260; CHECK-NEXT:    ret
261  call void @llvm.experimental.vp.strided.store.nxv2i64.p0.i32(<vscale x 2 x i64> %val, ptr %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)
262  ret void
263}
264
265declare void @llvm.experimental.vp.strided.store.nxv4i64.p0.i32(<vscale x 4 x i64>, ptr, i32, <vscale x 4 x i1>, i32)
266
267define void @strided_vpstore_nxv4i64(<vscale x 4 x i64> %val, ptr %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {
268; CHECK-LABEL: strided_vpstore_nxv4i64:
269; CHECK:       # %bb.0:
270; CHECK-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
271; CHECK-NEXT:    vsse64.v v8, (a0), a1, v0.t
272; CHECK-NEXT:    ret
273  call void @llvm.experimental.vp.strided.store.nxv4i64.p0.i32(<vscale x 4 x i64> %val, ptr %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)
274  ret void
275}
276
277declare void @llvm.experimental.vp.strided.store.nxv8i64.p0.i32(<vscale x 8 x i64>, ptr, i32, <vscale x 8 x i1>, i32)
278
279define void @strided_vpstore_nxv8i64(<vscale x 8 x i64> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {
280; CHECK-LABEL: strided_vpstore_nxv8i64:
281; CHECK:       # %bb.0:
282; CHECK-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
283; CHECK-NEXT:    vsse64.v v8, (a0), a1, v0.t
284; CHECK-NEXT:    ret
285  call void @llvm.experimental.vp.strided.store.nxv8i64.p0.i32(<vscale x 8 x i64> %val, ptr %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)
286  ret void
287}
288
289declare void @llvm.experimental.vp.strided.store.nxv1bf16.p0.i32(<vscale x 1 x bfloat>, ptr, i32, <vscale x 1 x i1>, i32)
290
291define void @strided_vpstore_nxv1bf16(<vscale x 1 x bfloat> %val, ptr %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {
292; CHECK-LABEL: strided_vpstore_nxv1bf16:
293; CHECK:       # %bb.0:
294; CHECK-NEXT:    vsetvli zero, a2, e16, mf4, ta, ma
295; CHECK-NEXT:    vsse16.v v8, (a0), a1, v0.t
296; CHECK-NEXT:    ret
297  call void @llvm.experimental.vp.strided.store.nxv1bf16.p0.i32(<vscale x 1 x bfloat> %val, ptr %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)
298  ret void
299}
300
301declare void @llvm.experimental.vp.strided.store.nxv2bf16.p0.i32(<vscale x 2 x bfloat>, ptr, i32, <vscale x 2 x i1>, i32)
302
303define void @strided_vpstore_nxv2bf16(<vscale x 2 x bfloat> %val, ptr %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {
304; CHECK-LABEL: strided_vpstore_nxv2bf16:
305; CHECK:       # %bb.0:
306; CHECK-NEXT:    vsetvli zero, a2, e16, mf2, ta, ma
307; CHECK-NEXT:    vsse16.v v8, (a0), a1, v0.t
308; CHECK-NEXT:    ret
309  call void @llvm.experimental.vp.strided.store.nxv2bf16.p0.i32(<vscale x 2 x bfloat> %val, ptr %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)
310  ret void
311}
312
313declare void @llvm.experimental.vp.strided.store.nxv4bf16.p0.i32(<vscale x 4 x bfloat>, ptr, i32, <vscale x 4 x i1>, i32)
314
315define void @strided_vpstore_nxv4bf16(<vscale x 4 x bfloat> %val, ptr %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {
316; CHECK-LABEL: strided_vpstore_nxv4bf16:
317; CHECK:       # %bb.0:
318; CHECK-NEXT:    vsetvli zero, a2, e16, m1, ta, ma
319; CHECK-NEXT:    vsse16.v v8, (a0), a1, v0.t
320; CHECK-NEXT:    ret
321  call void @llvm.experimental.vp.strided.store.nxv4bf16.p0.i32(<vscale x 4 x bfloat> %val, ptr %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)
322  ret void
323}
324
325define void @strided_vpstore_nxv4bf16_unit_stride(<vscale x 4 x bfloat> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
326; CHECK-LABEL: strided_vpstore_nxv4bf16_unit_stride:
327; CHECK:       # %bb.0:
328; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
329; CHECK-NEXT:    vse16.v v8, (a0), v0.t
330; CHECK-NEXT:    ret
331  call void @llvm.experimental.vp.strided.store.nxv4bf16.p0.i32(<vscale x 4 x bfloat> %val, ptr %ptr, i32 2, <vscale x 4 x i1> %m, i32 %evl)
332  ret void
333}
334
335declare void @llvm.experimental.vp.strided.store.nxv8bf16.p0.i32(<vscale x 8 x bfloat>, ptr, i32, <vscale x 8 x i1>, i32)
336
337define void @strided_vpstore_nxv8bf16(<vscale x 8 x bfloat> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {
338; CHECK-LABEL: strided_vpstore_nxv8bf16:
339; CHECK:       # %bb.0:
340; CHECK-NEXT:    vsetvli zero, a2, e16, m2, ta, ma
341; CHECK-NEXT:    vsse16.v v8, (a0), a1, v0.t
342; CHECK-NEXT:    ret
343  call void @llvm.experimental.vp.strided.store.nxv8bf16.p0.i32(<vscale x 8 x bfloat> %val, ptr %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)
344  ret void
345}
346
347declare void @llvm.experimental.vp.strided.store.nxv1f16.p0.i32(<vscale x 1 x half>, ptr, i32, <vscale x 1 x i1>, i32)
348
349define void @strided_vpstore_nxv1f16(<vscale x 1 x half> %val, ptr %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {
350; CHECK-LABEL: strided_vpstore_nxv1f16:
351; CHECK:       # %bb.0:
352; CHECK-NEXT:    vsetvli zero, a2, e16, mf4, ta, ma
353; CHECK-NEXT:    vsse16.v v8, (a0), a1, v0.t
354; CHECK-NEXT:    ret
355  call void @llvm.experimental.vp.strided.store.nxv1f16.p0.i32(<vscale x 1 x half> %val, ptr %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)
356  ret void
357}
358
359declare void @llvm.experimental.vp.strided.store.nxv2f16.p0.i32(<vscale x 2 x half>, ptr, i32, <vscale x 2 x i1>, i32)
360
361define void @strided_vpstore_nxv2f16(<vscale x 2 x half> %val, ptr %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {
362; CHECK-LABEL: strided_vpstore_nxv2f16:
363; CHECK:       # %bb.0:
364; CHECK-NEXT:    vsetvli zero, a2, e16, mf2, ta, ma
365; CHECK-NEXT:    vsse16.v v8, (a0), a1, v0.t
366; CHECK-NEXT:    ret
367  call void @llvm.experimental.vp.strided.store.nxv2f16.p0.i32(<vscale x 2 x half> %val, ptr %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)
368  ret void
369}
370
371declare void @llvm.experimental.vp.strided.store.nxv4f16.p0.i32(<vscale x 4 x half>, ptr, i32, <vscale x 4 x i1>, i32)
372
373define void @strided_vpstore_nxv4f16(<vscale x 4 x half> %val, ptr %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {
374; CHECK-LABEL: strided_vpstore_nxv4f16:
375; CHECK:       # %bb.0:
376; CHECK-NEXT:    vsetvli zero, a2, e16, m1, ta, ma
377; CHECK-NEXT:    vsse16.v v8, (a0), a1, v0.t
378; CHECK-NEXT:    ret
379  call void @llvm.experimental.vp.strided.store.nxv4f16.p0.i32(<vscale x 4 x half> %val, ptr %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)
380  ret void
381}
382
383define void @strided_vpstore_nxv4f16_unit_stride(<vscale x 4 x half> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
384; CHECK-LABEL: strided_vpstore_nxv4f16_unit_stride:
385; CHECK:       # %bb.0:
386; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
387; CHECK-NEXT:    vse16.v v8, (a0), v0.t
388; CHECK-NEXT:    ret
389  call void @llvm.experimental.vp.strided.store.nxv4f16.p0.i32(<vscale x 4 x half> %val, ptr %ptr, i32 2, <vscale x 4 x i1> %m, i32 %evl)
390  ret void
391}
392
393declare void @llvm.experimental.vp.strided.store.nxv8f16.p0.i32(<vscale x 8 x half>, ptr, i32, <vscale x 8 x i1>, i32)
394
395define void @strided_vpstore_nxv8f16(<vscale x 8 x half> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {
396; CHECK-LABEL: strided_vpstore_nxv8f16:
397; CHECK:       # %bb.0:
398; CHECK-NEXT:    vsetvli zero, a2, e16, m2, ta, ma
399; CHECK-NEXT:    vsse16.v v8, (a0), a1, v0.t
400; CHECK-NEXT:    ret
401  call void @llvm.experimental.vp.strided.store.nxv8f16.p0.i32(<vscale x 8 x half> %val, ptr %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)
402  ret void
403}
404
405declare void @llvm.experimental.vp.strided.store.nxv1f32.p0.i32(<vscale x 1 x float>, ptr, i32, <vscale x 1 x i1>, i32)
406
407define void @strided_vpstore_nxv1f32(<vscale x 1 x float> %val, ptr %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {
408; CHECK-LABEL: strided_vpstore_nxv1f32:
409; CHECK:       # %bb.0:
410; CHECK-NEXT:    vsetvli zero, a2, e32, mf2, ta, ma
411; CHECK-NEXT:    vsse32.v v8, (a0), a1, v0.t
412; CHECK-NEXT:    ret
413  call void @llvm.experimental.vp.strided.store.nxv1f32.p0.i32(<vscale x 1 x float> %val, ptr %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)
414  ret void
415}
416
417declare void @llvm.experimental.vp.strided.store.nxv2f32.p0.i32(<vscale x 2 x float>, ptr, i32, <vscale x 2 x i1>, i32)
418
419define void @strided_vpstore_nxv2f32(<vscale x 2 x float> %val, ptr %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {
420; CHECK-LABEL: strided_vpstore_nxv2f32:
421; CHECK:       # %bb.0:
422; CHECK-NEXT:    vsetvli zero, a2, e32, m1, ta, ma
423; CHECK-NEXT:    vsse32.v v8, (a0), a1, v0.t
424; CHECK-NEXT:    ret
425  call void @llvm.experimental.vp.strided.store.nxv2f32.p0.i32(<vscale x 2 x float> %val, ptr %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)
426  ret void
427}
428
429declare void @llvm.experimental.vp.strided.store.nxv4f32.p0.i32(<vscale x 4 x float>, ptr, i32, <vscale x 4 x i1>, i32)
430
431define void @strided_vpstore_nxv4f32(<vscale x 4 x float> %val, ptr %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {
432; CHECK-LABEL: strided_vpstore_nxv4f32:
433; CHECK:       # %bb.0:
434; CHECK-NEXT:    vsetvli zero, a2, e32, m2, ta, ma
435; CHECK-NEXT:    vsse32.v v8, (a0), a1, v0.t
436; CHECK-NEXT:    ret
437  call void @llvm.experimental.vp.strided.store.nxv4f32.p0.i32(<vscale x 4 x float> %val, ptr %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)
438  ret void
439}
440
441define void @strided_vpstore_nxv4f32_unit_stride(<vscale x 4 x float> %val, ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
442; CHECK-LABEL: strided_vpstore_nxv4f32_unit_stride:
443; CHECK:       # %bb.0:
444; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
445; CHECK-NEXT:    vse32.v v8, (a0), v0.t
446; CHECK-NEXT:    ret
447  call void @llvm.experimental.vp.strided.store.nxv4f32.p0.i32(<vscale x 4 x float> %val, ptr %ptr, i32 4, <vscale x 4 x i1> %m, i32 %evl)
448  ret void
449}
450
451declare void @llvm.experimental.vp.strided.store.nxv8f32.p0.i32(<vscale x 8 x float>, ptr, i32, <vscale x 8 x i1>, i32)
452
453define void @strided_vpstore_nxv8f32(<vscale x 8 x float> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {
454; CHECK-LABEL: strided_vpstore_nxv8f32:
455; CHECK:       # %bb.0:
456; CHECK-NEXT:    vsetvli zero, a2, e32, m4, ta, ma
457; CHECK-NEXT:    vsse32.v v8, (a0), a1, v0.t
458; CHECK-NEXT:    ret
459  call void @llvm.experimental.vp.strided.store.nxv8f32.p0.i32(<vscale x 8 x float> %val, ptr %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)
460  ret void
461}
462
463declare void @llvm.experimental.vp.strided.store.nxv1f64.p0.i32(<vscale x 1 x double>, ptr, i32, <vscale x 1 x i1>, i32)
464
465define void @strided_vpstore_nxv1f64(<vscale x 1 x double> %val, ptr %ptr, i32 signext %strided, <vscale x 1 x i1> %m, i32 zeroext %evl) {
466; CHECK-LABEL: strided_vpstore_nxv1f64:
467; CHECK:       # %bb.0:
468; CHECK-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
469; CHECK-NEXT:    vsse64.v v8, (a0), a1, v0.t
470; CHECK-NEXT:    ret
471  call void @llvm.experimental.vp.strided.store.nxv1f64.p0.i32(<vscale x 1 x double> %val, ptr %ptr, i32 %strided, <vscale x 1 x i1> %m, i32 %evl)
472  ret void
473}
474
475define void @strided_vpstore_nxv1f64_unit_stride(<vscale x 1 x double> %val, ptr %ptr, <vscale x 1 x i1> %m, i32 zeroext %evl) {
476; CHECK-LABEL: strided_vpstore_nxv1f64_unit_stride:
477; CHECK:       # %bb.0:
478; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
479; CHECK-NEXT:    vse64.v v8, (a0), v0.t
480; CHECK-NEXT:    ret
481  call void @llvm.experimental.vp.strided.store.nxv1f64.p0.i32(<vscale x 1 x double> %val, ptr %ptr, i32 8, <vscale x 1 x i1> %m, i32 %evl)
482  ret void
483}
484
485declare void @llvm.experimental.vp.strided.store.nxv2f64.p0.i32(<vscale x 2 x double>, ptr, i32, <vscale x 2 x i1>, i32)
486
487define void @strided_vpstore_nxv2f64(<vscale x 2 x double> %val, ptr %ptr, i32 signext %strided, <vscale x 2 x i1> %m, i32 zeroext %evl) {
488; CHECK-LABEL: strided_vpstore_nxv2f64:
489; CHECK:       # %bb.0:
490; CHECK-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
491; CHECK-NEXT:    vsse64.v v8, (a0), a1, v0.t
492; CHECK-NEXT:    ret
493  call void @llvm.experimental.vp.strided.store.nxv2f64.p0.i32(<vscale x 2 x double> %val, ptr %ptr, i32 %strided, <vscale x 2 x i1> %m, i32 %evl)
494  ret void
495}
496
497declare void @llvm.experimental.vp.strided.store.nxv4f64.p0.i32(<vscale x 4 x double>, ptr, i32, <vscale x 4 x i1>, i32)
498
499define void @strided_vpstore_nxv4f64(<vscale x 4 x double> %val, ptr %ptr, i32 signext %strided, <vscale x 4 x i1> %m, i32 zeroext %evl) {
500; CHECK-LABEL: strided_vpstore_nxv4f64:
501; CHECK:       # %bb.0:
502; CHECK-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
503; CHECK-NEXT:    vsse64.v v8, (a0), a1, v0.t
504; CHECK-NEXT:    ret
505  call void @llvm.experimental.vp.strided.store.nxv4f64.p0.i32(<vscale x 4 x double> %val, ptr %ptr, i32 %strided, <vscale x 4 x i1> %m, i32 %evl)
506  ret void
507}
508
509declare void @llvm.experimental.vp.strided.store.nxv8f64.p0.i32(<vscale x 8 x double>, ptr, i32, <vscale x 8 x i1>, i32)
510
511define void @strided_vpstore_nxv8f64(<vscale x 8 x double> %val, ptr %ptr, i32 signext %strided, <vscale x 8 x i1> %m, i32 zeroext %evl) {
512; CHECK-LABEL: strided_vpstore_nxv8f64:
513; CHECK:       # %bb.0:
514; CHECK-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
515; CHECK-NEXT:    vsse64.v v8, (a0), a1, v0.t
516; CHECK-NEXT:    ret
517  call void @llvm.experimental.vp.strided.store.nxv8f64.p0.i32(<vscale x 8 x double> %val, ptr %ptr, i32 %strided, <vscale x 8 x i1> %m, i32 %evl)
518  ret void
519}
520
521define void @strided_vpstore_nxv1i8_allones_mask(<vscale x 1 x i8> %val, ptr %ptr, i32 signext %strided, i32 zeroext %evl) {
522; CHECK-LABEL: strided_vpstore_nxv1i8_allones_mask:
523; CHECK:       # %bb.0:
524; CHECK-NEXT:    vsetvli zero, a2, e8, mf8, ta, ma
525; CHECK-NEXT:    vsse8.v v8, (a0), a1
526; CHECK-NEXT:    ret
527  call void @llvm.experimental.vp.strided.store.nxv1i8.p0.i32(<vscale x 1 x i8> %val, ptr %ptr, i32 %strided, <vscale x 1 x i1> splat (i1 true), i32 %evl)
528  ret void
529}
530
531; Widening
532define void @strided_vpstore_nxv3f32(<vscale x 3 x float> %v, ptr %ptr, i32 signext %stride, <vscale x 3 x i1> %mask, i32 zeroext %evl) {
533; CHECK-LABEL: strided_vpstore_nxv3f32:
534; CHECK:       # %bb.0:
535; CHECK-NEXT:    vsetvli zero, a2, e32, m2, ta, ma
536; CHECK-NEXT:    vsse32.v v8, (a0), a1, v0.t
537; CHECK-NEXT:    ret
538  call void @llvm.experimental.vp.strided.store.nxv3f32.p0.i32(<vscale x 3 x float> %v, ptr %ptr, i32 %stride, <vscale x 3 x i1> %mask, i32 %evl)
539  ret void
540}
541
542define void @strided_vpstore_nxv3f32_allones_mask(<vscale x 3 x float> %v, ptr %ptr, i32 signext %stride, i32 zeroext %evl) {
543; CHECK-LABEL: strided_vpstore_nxv3f32_allones_mask:
544; CHECK:       # %bb.0:
545; CHECK-NEXT:    vsetvli zero, a2, e32, m2, ta, ma
546; CHECK-NEXT:    vsse32.v v8, (a0), a1
547; CHECK-NEXT:    ret
548  call void @llvm.experimental.vp.strided.store.nxv3f32.p0.i32(<vscale x 3 x float> %v, ptr %ptr, i32 %stride, <vscale x 3 x i1> splat (i1 true), i32 %evl)
549  ret void
550}
551
552declare void @llvm.experimental.vp.strided.store.nxv3f32.p0.i32(<vscale x 3 x float>, ptr , i32, <vscale x 3 x i1>, i32)
553
554; Splitting
555define void @strided_store_nxv16f64(<vscale x 16 x double> %v, ptr %ptr, i32 signext %stride, <vscale x 16 x i1> %mask, i32 zeroext %evl) {
556; CHECK-LABEL: strided_store_nxv16f64:
557; CHECK:       # %bb.0:
558; CHECK-NEXT:    csrr a3, vlenb
559; CHECK-NEXT:    mv a4, a2
560; CHECK-NEXT:    bltu a2, a3, .LBB46_2
561; CHECK-NEXT:  # %bb.1:
562; CHECK-NEXT:    mv a4, a3
563; CHECK-NEXT:  .LBB46_2:
564; CHECK-NEXT:    vsetvli zero, a4, e64, m8, ta, ma
565; CHECK-NEXT:    vsse64.v v8, (a0), a1, v0.t
566; CHECK-NEXT:    sub a5, a2, a3
567; CHECK-NEXT:    mul a4, a4, a1
568; CHECK-NEXT:    srli a3, a3, 3
569; CHECK-NEXT:    sltu a2, a2, a5
570; CHECK-NEXT:    vsetvli a6, zero, e8, mf4, ta, ma
571; CHECK-NEXT:    vslidedown.vx v0, v0, a3
572; CHECK-NEXT:    addi a2, a2, -1
573; CHECK-NEXT:    and a2, a2, a5
574; CHECK-NEXT:    add a0, a0, a4
575; CHECK-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
576; CHECK-NEXT:    vsse64.v v16, (a0), a1, v0.t
577; CHECK-NEXT:    ret
578  call void @llvm.experimental.vp.strided.store.nxv16f64.p0.i32(<vscale x 16 x double> %v, ptr %ptr, i32 %stride, <vscale x 16 x i1> %mask, i32 %evl)
579  ret void
580}
581
582define void @strided_store_nxv16f64_allones_mask(<vscale x 16 x double> %v, ptr %ptr, i32 signext %stride, i32 zeroext %evl) {
583; CHECK-LABEL: strided_store_nxv16f64_allones_mask:
584; CHECK:       # %bb.0:
585; CHECK-NEXT:    csrr a4, vlenb
586; CHECK-NEXT:    mv a3, a2
587; CHECK-NEXT:    bltu a2, a4, .LBB47_2
588; CHECK-NEXT:  # %bb.1:
589; CHECK-NEXT:    mv a3, a4
590; CHECK-NEXT:  .LBB47_2:
591; CHECK-NEXT:    vsetvli zero, a3, e64, m8, ta, ma
592; CHECK-NEXT:    vsse64.v v8, (a0), a1
593; CHECK-NEXT:    sub a4, a2, a4
594; CHECK-NEXT:    mul a3, a3, a1
595; CHECK-NEXT:    sltu a2, a2, a4
596; CHECK-NEXT:    addi a2, a2, -1
597; CHECK-NEXT:    and a2, a2, a4
598; CHECK-NEXT:    add a0, a0, a3
599; CHECK-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
600; CHECK-NEXT:    vsse64.v v16, (a0), a1
601; CHECK-NEXT:    ret
602  call void @llvm.experimental.vp.strided.store.nxv16f64.p0.i32(<vscale x 16 x double> %v, ptr %ptr, i32 %stride, <vscale x 16 x i1> splat (i1 true), i32 %evl)
603  ret void
604}
605
606declare void @llvm.experimental.vp.strided.store.nxv16f64.p0.i32(<vscale x 16 x double>, ptr, i32, <vscale x 16 x i1>, i32)
607
608; Widening + splitting (with HiIsEmpty == true)
609define void @strided_store_nxv17f64(<vscale x 17 x double> %v, ptr %ptr, i32 signext %stride, <vscale x 17 x i1> %mask, i32 zeroext %evl) {
610; CHECK-LABEL: strided_store_nxv17f64:
611; CHECK:       # %bb.0:
612; CHECK-NEXT:    addi sp, sp, -16
613; CHECK-NEXT:    .cfi_def_cfa_offset 16
614; CHECK-NEXT:    csrr a4, vlenb
615; CHECK-NEXT:    slli a4, a4, 3
616; CHECK-NEXT:    sub sp, sp, a4
617; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
618; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
619; CHECK-NEXT:    vmv1r.v v24, v0
620; CHECK-NEXT:    addi a4, sp, 16
621; CHECK-NEXT:    vs8r.v v16, (a4) # Unknown-size Folded Spill
622; CHECK-NEXT:    csrr a4, vlenb
623; CHECK-NEXT:    slli a6, a4, 1
624; CHECK-NEXT:    mv a5, a3
625; CHECK-NEXT:    bltu a3, a6, .LBB48_2
626; CHECK-NEXT:  # %bb.1:
627; CHECK-NEXT:    mv a5, a6
628; CHECK-NEXT:  .LBB48_2:
629; CHECK-NEXT:    mv a7, a5
630; CHECK-NEXT:    bltu a5, a4, .LBB48_4
631; CHECK-NEXT:  # %bb.3:
632; CHECK-NEXT:    mv a7, a4
633; CHECK-NEXT:  .LBB48_4:
634; CHECK-NEXT:    vmv1r.v v0, v24
635; CHECK-NEXT:    vl8re64.v v16, (a0)
636; CHECK-NEXT:    vsetvli zero, a7, e64, m8, ta, ma
637; CHECK-NEXT:    vsse64.v v8, (a1), a2, v0.t
638; CHECK-NEXT:    sub a0, a5, a4
639; CHECK-NEXT:    mul a7, a7, a2
640; CHECK-NEXT:    srli t0, a4, 3
641; CHECK-NEXT:    sub a6, a3, a6
642; CHECK-NEXT:    vsetvli t1, zero, e8, mf4, ta, ma
643; CHECK-NEXT:    vslidedown.vx v0, v24, t0
644; CHECK-NEXT:    sltu t0, a5, a0
645; CHECK-NEXT:    add a7, a1, a7
646; CHECK-NEXT:    sltu a3, a3, a6
647; CHECK-NEXT:    addi t0, t0, -1
648; CHECK-NEXT:    addi a3, a3, -1
649; CHECK-NEXT:    and t0, t0, a0
650; CHECK-NEXT:    and a0, a3, a6
651; CHECK-NEXT:    addi a3, sp, 16
652; CHECK-NEXT:    vl8r.v v8, (a3) # Unknown-size Folded Reload
653; CHECK-NEXT:    vsetvli zero, t0, e64, m8, ta, ma
654; CHECK-NEXT:    vsse64.v v8, (a7), a2, v0.t
655; CHECK-NEXT:    bltu a0, a4, .LBB48_6
656; CHECK-NEXT:  # %bb.5:
657; CHECK-NEXT:    mv a0, a4
658; CHECK-NEXT:  .LBB48_6:
659; CHECK-NEXT:    mul a3, a5, a2
660; CHECK-NEXT:    srli a4, a4, 2
661; CHECK-NEXT:    vsetvli a5, zero, e8, mf2, ta, ma
662; CHECK-NEXT:    vslidedown.vx v0, v24, a4
663; CHECK-NEXT:    add a1, a1, a3
664; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
665; CHECK-NEXT:    vsse64.v v16, (a1), a2, v0.t
666; CHECK-NEXT:    csrr a0, vlenb
667; CHECK-NEXT:    slli a0, a0, 3
668; CHECK-NEXT:    add sp, sp, a0
669; CHECK-NEXT:    .cfi_def_cfa sp, 16
670; CHECK-NEXT:    addi sp, sp, 16
671; CHECK-NEXT:    .cfi_def_cfa_offset 0
672; CHECK-NEXT:    ret
673  call void @llvm.experimental.vp.strided.store.nxv17f64.p0.i32(<vscale x 17 x double> %v, ptr %ptr, i32 %stride, <vscale x 17 x i1> %mask, i32 %evl)
674  ret void
675}
676
677declare void @llvm.experimental.vp.strided.store.nxv17f64.p0.i32(<vscale x 17 x double>, ptr, i32, <vscale x 17 x i1>, i32)
678