xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll (revision 01a15dca09e56dce850ab6fb3ecddfb3f8c6c172) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
3
4declare <2 x i64> @llvm.sshl.sat.v2i64(<2 x i64>, <2 x i64>)
5declare <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32>, <4 x i32>)
6declare <8 x i16> @llvm.sshl.sat.v8i16(<8 x i16>, <8 x i16>)
7declare <16 x i8> @llvm.sshl.sat.v16i8(<16 x i8>, <16 x i8>)
8
9define <2 x i64> @vec_v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
10; CHECK-LABEL: vec_v2i64:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
13; CHECK-NEXT:    vmsle.vi v0, v8, -1
14; CHECK-NEXT:    li a0, -1
15; CHECK-NEXT:    srli a1, a0, 1
16; CHECK-NEXT:    slli a0, a0, 63
17; CHECK-NEXT:    vmv.v.x v10, a1
18; CHECK-NEXT:    vmerge.vxm v10, v10, a0, v0
19; CHECK-NEXT:    vsll.vv v11, v8, v9
20; CHECK-NEXT:    vsra.vv v9, v11, v9
21; CHECK-NEXT:    vmsne.vv v0, v8, v9
22; CHECK-NEXT:    vmerge.vvm v8, v11, v10, v0
23; CHECK-NEXT:    ret
24  %tmp = call <2 x i64> @llvm.sshl.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
25  ret <2 x i64> %tmp
26}
27
28define <4 x i32> @vec_v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
29; CHECK-LABEL: vec_v4i32:
30; CHECK:       # %bb.0:
31; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
32; CHECK-NEXT:    vmsle.vi v0, v8, -1
33; CHECK-NEXT:    lui a0, 524288
34; CHECK-NEXT:    addi a1, a0, -1
35; CHECK-NEXT:    vmv.v.x v10, a1
36; CHECK-NEXT:    vmerge.vxm v10, v10, a0, v0
37; CHECK-NEXT:    vsll.vv v11, v8, v9
38; CHECK-NEXT:    vsra.vv v9, v11, v9
39; CHECK-NEXT:    vmsne.vv v0, v8, v9
40; CHECK-NEXT:    vmerge.vvm v8, v11, v10, v0
41; CHECK-NEXT:    ret
42  %tmp = call <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
43  ret <4 x i32> %tmp
44}
45
46define <8 x i16> @vec_v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
47; CHECK-LABEL: vec_v8i16:
48; CHECK:       # %bb.0:
49; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
50; CHECK-NEXT:    vmsle.vi v0, v8, -1
51; CHECK-NEXT:    lui a0, 8
52; CHECK-NEXT:    addi a1, a0, -1
53; CHECK-NEXT:    vmv.v.x v10, a1
54; CHECK-NEXT:    vmerge.vxm v10, v10, a0, v0
55; CHECK-NEXT:    vsll.vv v11, v8, v9
56; CHECK-NEXT:    vsra.vv v9, v11, v9
57; CHECK-NEXT:    vmsne.vv v0, v8, v9
58; CHECK-NEXT:    vmerge.vvm v8, v11, v10, v0
59; CHECK-NEXT:    ret
60  %tmp = call <8 x i16> @llvm.sshl.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
61  ret <8 x i16> %tmp
62}
63
64define <16 x i8> @vec_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
65; CHECK-LABEL: vec_v16i8:
66; CHECK:       # %bb.0:
67; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
68; CHECK-NEXT:    vmsle.vi v0, v8, -1
69; CHECK-NEXT:    li a0, 127
70; CHECK-NEXT:    vmv.v.x v10, a0
71; CHECK-NEXT:    li a0, 128
72; CHECK-NEXT:    vmerge.vxm v10, v10, a0, v0
73; CHECK-NEXT:    vsll.vv v11, v8, v9
74; CHECK-NEXT:    vsra.vv v9, v11, v9
75; CHECK-NEXT:    vmsne.vv v0, v8, v9
76; CHECK-NEXT:    vmerge.vvm v8, v11, v10, v0
77; CHECK-NEXT:    ret
78  %tmp = call <16 x i8> @llvm.sshl.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
79  ret <16 x i8> %tmp
80}
81
82declare <vscale x 2 x i64> @llvm.sshl.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
83declare <vscale x 4 x i32> @llvm.sshl.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
84declare <vscale x 8 x i16> @llvm.sshl.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
85declare <vscale x 16 x i8> @llvm.sshl.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
86
87define <vscale x 2 x i64> @vec_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) nounwind {
88; CHECK-LABEL: vec_nxv2i64:
89; CHECK:       # %bb.0:
90; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
91; CHECK-NEXT:    vmsle.vi v0, v8, -1
92; CHECK-NEXT:    li a0, -1
93; CHECK-NEXT:    srli a1, a0, 1
94; CHECK-NEXT:    slli a0, a0, 63
95; CHECK-NEXT:    vmv.v.x v12, a1
96; CHECK-NEXT:    vmerge.vxm v12, v12, a0, v0
97; CHECK-NEXT:    vsll.vv v14, v8, v10
98; CHECK-NEXT:    vsra.vv v10, v14, v10
99; CHECK-NEXT:    vmsne.vv v0, v8, v10
100; CHECK-NEXT:    vmerge.vvm v8, v14, v12, v0
101; CHECK-NEXT:    ret
102  %tmp = call <vscale x 2 x i64> @llvm.sshl.sat.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y)
103  ret <vscale x 2 x i64> %tmp
104}
105
106define <vscale x 4 x i32> @vec_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) nounwind {
107; CHECK-LABEL: vec_nxv4i32:
108; CHECK:       # %bb.0:
109; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
110; CHECK-NEXT:    vmsle.vi v0, v8, -1
111; CHECK-NEXT:    lui a0, 524288
112; CHECK-NEXT:    addi a1, a0, -1
113; CHECK-NEXT:    vmv.v.x v12, a1
114; CHECK-NEXT:    vmerge.vxm v12, v12, a0, v0
115; CHECK-NEXT:    vsll.vv v14, v8, v10
116; CHECK-NEXT:    vsra.vv v10, v14, v10
117; CHECK-NEXT:    vmsne.vv v0, v8, v10
118; CHECK-NEXT:    vmerge.vvm v8, v14, v12, v0
119; CHECK-NEXT:    ret
120  %tmp = call <vscale x 4 x i32> @llvm.sshl.sat.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)
121  ret <vscale x 4 x i32> %tmp
122}
123
124define <vscale x 8 x i16> @vec_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) nounwind {
125; CHECK-LABEL: vec_nxv8i16:
126; CHECK:       # %bb.0:
127; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
128; CHECK-NEXT:    vmsle.vi v0, v8, -1
129; CHECK-NEXT:    lui a0, 8
130; CHECK-NEXT:    addi a1, a0, -1
131; CHECK-NEXT:    vmv.v.x v12, a1
132; CHECK-NEXT:    vmerge.vxm v12, v12, a0, v0
133; CHECK-NEXT:    vsll.vv v14, v8, v10
134; CHECK-NEXT:    vsra.vv v10, v14, v10
135; CHECK-NEXT:    vmsne.vv v0, v8, v10
136; CHECK-NEXT:    vmerge.vvm v8, v14, v12, v0
137; CHECK-NEXT:    ret
138  %tmp = call <vscale x 8 x i16> @llvm.sshl.sat.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)
139  ret <vscale x 8 x i16> %tmp
140}
141
142define <vscale x 16 x i8> @vec_nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) nounwind {
143; CHECK-LABEL: vec_nxv16i8:
144; CHECK:       # %bb.0:
145; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
146; CHECK-NEXT:    vmsle.vi v0, v8, -1
147; CHECK-NEXT:    li a0, 127
148; CHECK-NEXT:    vmv.v.x v12, a0
149; CHECK-NEXT:    li a0, 128
150; CHECK-NEXT:    vmerge.vxm v12, v12, a0, v0
151; CHECK-NEXT:    vsll.vv v14, v8, v10
152; CHECK-NEXT:    vsra.vv v10, v14, v10
153; CHECK-NEXT:    vmsne.vv v0, v8, v10
154; CHECK-NEXT:    vmerge.vvm v8, v14, v12, v0
155; CHECK-NEXT:    ret
156  %tmp = call <vscale x 16 x i8> @llvm.sshl.sat.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)
157  ret <vscale x 16 x i8> %tmp
158}
159