1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s 3 4declare { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.sadd.with.overflow.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>) 5 6define <vscale x 2 x i32> @saddo_nvx2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) { 7; CHECK-LABEL: saddo_nvx2i32: 8; CHECK: # %bb.0: 9; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma 10; CHECK-NEXT: vsadd.vv v10, v8, v9 11; CHECK-NEXT: vadd.vv v8, v8, v9 12; CHECK-NEXT: vmsne.vv v0, v8, v10 13; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 14; CHECK-NEXT: ret 15 %a = call { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.sadd.with.overflow.nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) 16 %b = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 0 17 %c = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 1 18 %d = select <vscale x 2 x i1> %c, <vscale x 2 x i32> zeroinitializer, <vscale x 2 x i32> %b 19 ret <vscale x 2 x i32> %d 20} 21