1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple riscv32 -mattr=+m,+v < %s \ 3; RUN: | FileCheck %s 4 5define i32 @vscale_zero() nounwind { 6; CHECK-LABEL: vscale_zero: 7; CHECK: # %bb.0: # %entry 8; CHECK-NEXT: li a0, 0 9; CHECK-NEXT: ret 10entry: 11 %0 = call i32 @llvm.vscale.i32() 12 %1 = mul i32 %0, 0 13 ret i32 %1 14} 15 16define i32 @vscale_one() nounwind { 17; CHECK-LABEL: vscale_one: 18; CHECK: # %bb.0: # %entry 19; CHECK-NEXT: csrr a0, vlenb 20; CHECK-NEXT: srli a0, a0, 3 21; CHECK-NEXT: ret 22entry: 23 %0 = call i32 @llvm.vscale.i32() 24 %1 = mul i32 %0, 1 25 ret i32 %1 26} 27 28define i32 @vscale_uimmpow2xlen() nounwind { 29; CHECK-LABEL: vscale_uimmpow2xlen: 30; CHECK: # %bb.0: # %entry 31; CHECK-NEXT: csrr a0, vlenb 32; CHECK-NEXT: slli a0, a0, 3 33; CHECK-NEXT: ret 34entry: 35 %0 = call i32 @llvm.vscale.i32() 36 %1 = mul i32 %0, 64 37 ret i32 %1 38} 39 40define i32 @vscale_non_pow2() nounwind { 41; CHECK-LABEL: vscale_non_pow2: 42; CHECK: # %bb.0: # %entry 43; CHECK-NEXT: csrr a0, vlenb 44; CHECK-NEXT: slli a1, a0, 1 45; CHECK-NEXT: add a0, a1, a0 46; CHECK-NEXT: ret 47entry: 48 %0 = call i32 @llvm.vscale.i32() 49 %1 = mul i32 %0, 24 50 ret i32 %1 51} 52 53declare i32 @llvm.vscale.i32() 54