1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2; RUN: llc < %s -mtriple=riscv64-unknown-linux-gnu -mattr=+v | FileCheck %s 3 4define i32 @main() vscale_range(2,2) { 5; CHECK-LABEL: main: 6; CHECK: # %bb.0: # %vector.body 7; CHECK-NEXT: lui a0, 1040368 8; CHECK-NEXT: addiw a0, a0, -144 9; CHECK-NEXT: vl2re16.v v8, (a0) 10; CHECK-NEXT: vs2r.v v8, (zero) 11; CHECK-NEXT: li a0, 0 12; CHECK-NEXT: ret 13vector.body: 14 %0 = load <16 x i16>, ptr getelementptr ([3 x [23 x [23 x i16]]], ptr null, i64 -10593, i64 1, i64 22, i64 0), align 16 15 store <16 x i16> %0, ptr null, align 2 16 %wide.load = load <vscale x 8 x i16>, ptr getelementptr ([3 x [23 x [23 x i16]]], ptr null, i64 -10593, i64 1, i64 22, i64 0), align 16 17 store <vscale x 8 x i16> %wide.load, ptr null, align 2 18 ret i32 0 19} 20