1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s 3 4define i1 @foo(<vscale x 16 x i8> %x, i64 %y) { 5; CHECK-LABEL: foo: 6; CHECK: # %bb.0: 7; CHECK-NEXT: csrr a1, vlenb 8; CHECK-NEXT: slli a2, a1, 4 9; CHECK-NEXT: addi a2, a2, -1 10; CHECK-NEXT: bltu a0, a2, .LBB0_2 11; CHECK-NEXT: # %bb.1: 12; CHECK-NEXT: mv a0, a2 13; CHECK-NEXT: .LBB0_2: 14; CHECK-NEXT: addi sp, sp, -80 15; CHECK-NEXT: .cfi_def_cfa_offset 80 16; CHECK-NEXT: sd ra, 72(sp) # 8-byte Folded Spill 17; CHECK-NEXT: sd s0, 64(sp) # 8-byte Folded Spill 18; CHECK-NEXT: .cfi_offset ra, -8 19; CHECK-NEXT: .cfi_offset s0, -16 20; CHECK-NEXT: addi s0, sp, 80 21; CHECK-NEXT: .cfi_def_cfa s0, 0 22; CHECK-NEXT: csrr a2, vlenb 23; CHECK-NEXT: slli a2, a2, 4 24; CHECK-NEXT: sub sp, sp, a2 25; CHECK-NEXT: andi sp, sp, -64 26; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma 27; CHECK-NEXT: vmv1r.v v0, v9 28; CHECK-NEXT: addi a2, sp, 64 29; CHECK-NEXT: slli a1, a1, 3 30; CHECK-NEXT: vmv.v.i v16, 0 31; CHECK-NEXT: add a0, a2, a0 32; CHECK-NEXT: add a1, a2, a1 33; CHECK-NEXT: vmerge.vim v24, v16, 1, v0 34; CHECK-NEXT: vs8r.v v24, (a1) 35; CHECK-NEXT: vmv1r.v v0, v8 36; CHECK-NEXT: vmerge.vim v8, v16, 1, v0 37; CHECK-NEXT: vs8r.v v8, (a2) 38; CHECK-NEXT: lbu a0, 0(a0) 39; CHECK-NEXT: addi sp, s0, -80 40; CHECK-NEXT: .cfi_def_cfa sp, 80 41; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload 42; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload 43; CHECK-NEXT: .cfi_restore ra 44; CHECK-NEXT: .cfi_restore s0 45; CHECK-NEXT: addi sp, sp, 80 46; CHECK-NEXT: .cfi_def_cfa_offset 0 47; CHECK-NEXT: ret 48 %a = bitcast <vscale x 16 x i8> %x to <vscale x 128 x i1> 49 %b = extractelement <vscale x 128 x i1> %a, i64 %y 50 ret i1 %b 51} 52 53define i8 @bar(<vscale x 128 x i1> %x, i64 %y) { 54; CHECK-LABEL: bar: 55; CHECK: # %bb.0: 56; CHECK-NEXT: vsetivli zero, 1, e8, m2, ta, ma 57; CHECK-NEXT: vmv1r.v v1, v8 58; CHECK-NEXT: vslidedown.vx v8, v0, a0 59; CHECK-NEXT: vmv.x.s a0, v8 60; CHECK-NEXT: ret 61 %a = bitcast <vscale x 128 x i1> %x to <vscale x 16 x i8> 62 %b = extractelement <vscale x 16 x i8> %a, i64 %y 63 ret i8 %b 64} 65