xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/pr63596.ll (revision 6da5968f5ecc2a2e8b0697e335f4dec1b3bbfd01)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc < %s -mtriple=riscv64 -mattr=+v -target-abi=lp64d | FileCheck %s
3
4define <4 x float> @foo(ptr %0) nounwind {
5; CHECK-LABEL: foo:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    addi sp, sp, -48
8; CHECK-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
9; CHECK-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
10; CHECK-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill
11; CHECK-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
12; CHECK-NEXT:    csrr a1, vlenb
13; CHECK-NEXT:    slli a1, a1, 1
14; CHECK-NEXT:    sub sp, sp, a1
15; CHECK-NEXT:    lhu s0, 0(a0)
16; CHECK-NEXT:    lhu s1, 2(a0)
17; CHECK-NEXT:    lhu s2, 4(a0)
18; CHECK-NEXT:    lhu a0, 6(a0)
19; CHECK-NEXT:    fmv.w.x fa0, a0
20; CHECK-NEXT:    call __extendhfsf2
21; CHECK-NEXT:    fmv.w.x fa5, s2
22; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
23; CHECK-NEXT:    vfmv.s.f v8, fa0
24; CHECK-NEXT:    addi a0, sp, 16
25; CHECK-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
26; CHECK-NEXT:    fmv.s fa0, fa5
27; CHECK-NEXT:    call __extendhfsf2
28; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
29; CHECK-NEXT:    vfmv.s.f v8, fa0
30; CHECK-NEXT:    addi a0, sp, 16
31; CHECK-NEXT:    vl1r.v v9, (a0) # Unknown-size Folded Reload
32; CHECK-NEXT:    vslideup.vi v8, v9, 1
33; CHECK-NEXT:    csrr a0, vlenb
34; CHECK-NEXT:    add a0, sp, a0
35; CHECK-NEXT:    addi a0, a0, 16
36; CHECK-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
37; CHECK-NEXT:    fmv.w.x fa0, s1
38; CHECK-NEXT:    call __extendhfsf2
39; CHECK-NEXT:    fmv.w.x fa5, s0
40; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
41; CHECK-NEXT:    vfmv.s.f v8, fa0
42; CHECK-NEXT:    addi a0, sp, 16
43; CHECK-NEXT:    vs1r.v v8, (a0) # Unknown-size Folded Spill
44; CHECK-NEXT:    fmv.s fa0, fa5
45; CHECK-NEXT:    call __extendhfsf2
46; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
47; CHECK-NEXT:    vfmv.s.f v8, fa0
48; CHECK-NEXT:    addi a0, sp, 16
49; CHECK-NEXT:    vl1r.v v9, (a0) # Unknown-size Folded Reload
50; CHECK-NEXT:    vslideup.vi v8, v9, 1
51; CHECK-NEXT:    csrr a0, vlenb
52; CHECK-NEXT:    add a0, sp, a0
53; CHECK-NEXT:    addi a0, a0, 16
54; CHECK-NEXT:    vl1r.v v9, (a0) # Unknown-size Folded Reload
55; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
56; CHECK-NEXT:    vslideup.vi v8, v9, 2
57; CHECK-NEXT:    csrr a0, vlenb
58; CHECK-NEXT:    slli a0, a0, 1
59; CHECK-NEXT:    add sp, sp, a0
60; CHECK-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
61; CHECK-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
62; CHECK-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
63; CHECK-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
64; CHECK-NEXT:    addi sp, sp, 48
65; CHECK-NEXT:    ret
66  %2 = load <4 x half>, ptr %0, align 2
67  %3 = fpext <4 x half> %2 to <4 x float>
68  ret <4 x float> %3
69}
70