xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/pr52475.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=4 \
3; RUN:   -pre-RA-sched=list-burr -disable-machine-cse -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-fixed-length-vector-lmul-max=4 \
5; RUN:   -pre-RA-sched=list-burr -disable-machine-cse -verify-machineinstrs < %s | FileCheck %s
6
7define <128 x i32> @ret_split_v128i32(ptr %x) {
8; CHECK-LABEL: ret_split_v128i32:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
11; CHECK-NEXT:    vle32.v v8, (a1)
12; CHECK-NEXT:    addi a2, a1, 448
13; CHECK-NEXT:    vse32.v v8, (a0)
14; CHECK-NEXT:    vle32.v v8, (a2)
15; CHECK-NEXT:    addi a2, a0, 448
16; CHECK-NEXT:    vse32.v v8, (a2)
17; CHECK-NEXT:    addi a2, a1, 384
18; CHECK-NEXT:    vle32.v v8, (a2)
19; CHECK-NEXT:    addi a2, a0, 384
20; CHECK-NEXT:    vse32.v v8, (a2)
21; CHECK-NEXT:    addi a2, a1, 320
22; CHECK-NEXT:    vle32.v v8, (a2)
23; CHECK-NEXT:    addi a2, a0, 320
24; CHECK-NEXT:    vse32.v v8, (a2)
25; CHECK-NEXT:    addi a2, a1, 256
26; CHECK-NEXT:    vle32.v v8, (a2)
27; CHECK-NEXT:    addi a2, a0, 256
28; CHECK-NEXT:    vse32.v v8, (a2)
29; CHECK-NEXT:    addi a2, a1, 192
30; CHECK-NEXT:    vle32.v v8, (a2)
31; CHECK-NEXT:    addi a2, a0, 192
32; CHECK-NEXT:    vse32.v v8, (a2)
33; CHECK-NEXT:    addi a2, a1, 128
34; CHECK-NEXT:    vle32.v v8, (a2)
35; CHECK-NEXT:    addi a2, a0, 128
36; CHECK-NEXT:    vse32.v v8, (a2)
37; CHECK-NEXT:    addi a1, a1, 64
38; CHECK-NEXT:    vle32.v v8, (a1)
39; CHECK-NEXT:    addi a0, a0, 64
40; CHECK-NEXT:    vse32.v v8, (a0)
41; CHECK-NEXT:    ret
42  %v = load <128 x i32>, ptr %x
43  ret <128 x i32> %v
44}
45