1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s 3 4define <vscale x 4 x float> @intrinsic_vfslide1down_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %false, float %1, <vscale x 4 x i1> %mask) { 5; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv4f32_nxv4f32_f32: 6; CHECK: # %bb.0: # %entry 7; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma 8; CHECK-NEXT: vfslide1down.vf v8, v8, fa0 9; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma 10; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 11; CHECK-NEXT: ret 12entry: 13 %a = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32(<vscale x 4 x float> undef, <vscale x 4 x float> %0, float %1, i64 4) 14 %b = call <vscale x 4 x float> @llvm.riscv.vmerge.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x float> %false, <vscale x 4 x float> %a, <vscale x 4 x i1> %mask, i64 1) 15 ret <vscale x 4 x float> %b 16} 17