xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/pr104480.ll (revision 9122c5235ec85ce0c0ad337e862b006e7b349d84) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v | FileCheck %s
3
4define <vscale x 4 x i16> @test_mulhs_promote(<vscale x 4 x i16> %broadcast.splatinsert, <vscale x 4 x i1> %0, <vscale x 4 x i1> %1) {
5; CHECK-LABEL: test_mulhs_promote:
6; CHECK:       # %bb.0: # %entry
7; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
8; CHECK-NEXT:    vrgather.vi v9, v8, 0
9; CHECK-NEXT:    lui a0, 5
10; CHECK-NEXT:    addi a0, a0, 1366
11; CHECK-NEXT:    vmulh.vx v8, v9, a0
12; CHECK-NEXT:    vsrl.vi v10, v8, 15
13; CHECK-NEXT:    vadd.vv v8, v8, v10
14; CHECK-NEXT:    li a0, 3
15; CHECK-NEXT:    vnmsub.vx v8, a0, v9
16; CHECK-NEXT:    ret
17entry:
18  %broadcast.splat = shufflevector <vscale x 4 x i16> %broadcast.splatinsert, <vscale x 4 x i16> zeroinitializer, <vscale x 4 x i32> zeroinitializer
19  %2 = srem <vscale x 4 x i16> %broadcast.splat, shufflevector (<vscale x 4 x i16> insertelement (<vscale x 4 x i16> poison, i16 3, i64 0), <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer)
20 ret <vscale x 4 x i16> %2
21}
22
23define <vscale x 4 x i16> @test_mulhu_promote(<vscale x 4 x i16> %broadcast.splatinsert, <vscale x 4 x i1> %0, <vscale x 4 x i1> %1) {
24; CHECK-LABEL: test_mulhu_promote:
25; CHECK:       # %bb.0: # %entry
26; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
27; CHECK-NEXT:    vrgather.vi v9, v8, 0
28; CHECK-NEXT:    lui a0, 1048571
29; CHECK-NEXT:    addi a0, a0, -1365
30; CHECK-NEXT:    vmulhu.vx v8, v9, a0
31; CHECK-NEXT:    vsrl.vi v8, v8, 1
32; CHECK-NEXT:    li a0, 3
33; CHECK-NEXT:    vnmsub.vx v8, a0, v9
34; CHECK-NEXT:    ret
35entry:
36  %broadcast.splat = shufflevector <vscale x 4 x i16> %broadcast.splatinsert, <vscale x 4 x i16> zeroinitializer, <vscale x 4 x i32> zeroinitializer
37  %2 = urem <vscale x 4 x i16> %broadcast.splat, shufflevector (<vscale x 4 x i16> insertelement (<vscale x 4 x i16> poison, i16 3, i64 0), <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer)
38 ret <vscale x 4 x i16> %2
39}
40
41define <vscale x 4 x i64> @test_mulhs_expand(<vscale x 4 x i64> %broadcast.splatinsert, <vscale x 4 x i1> %0, <vscale x 4 x i1> %1) {
42; CHECK-LABEL: test_mulhs_expand:
43; CHECK:       # %bb.0: # %entry
44; CHECK-NEXT:    addi sp, sp, -16
45; CHECK-NEXT:    .cfi_def_cfa_offset 16
46; CHECK-NEXT:    lui a0, 349525
47; CHECK-NEXT:    addi a1, sp, 8
48; CHECK-NEXT:    addi a2, a0, 1365
49; CHECK-NEXT:    addi a0, a0, 1366
50; CHECK-NEXT:    sw a0, 8(sp)
51; CHECK-NEXT:    sw a2, 12(sp)
52; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
53; CHECK-NEXT:    vlse64.v v12, (a1), zero
54; CHECK-NEXT:    vrgather.vi v16, v8, 0
55; CHECK-NEXT:    li a0, 63
56; CHECK-NEXT:    vmulh.vv v8, v16, v12
57; CHECK-NEXT:    vsrl.vx v12, v8, a0
58; CHECK-NEXT:    vadd.vv v8, v8, v12
59; CHECK-NEXT:    li a0, 3
60; CHECK-NEXT:    vnmsub.vx v8, a0, v16
61; CHECK-NEXT:    addi sp, sp, 16
62; CHECK-NEXT:    .cfi_def_cfa_offset 0
63; CHECK-NEXT:    ret
64entry:
65  %broadcast.splat = shufflevector <vscale x 4 x i64> %broadcast.splatinsert, <vscale x 4 x i64> zeroinitializer, <vscale x 4 x i32> zeroinitializer
66  %2 = srem <vscale x 4 x i64> %broadcast.splat, shufflevector (<vscale x 4 x i64> insertelement (<vscale x 4 x i64> poison, i64 3, i64 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer)
67 ret <vscale x 4 x i64> %2
68}
69
70define <vscale x 4 x i64> @test_mulhu_expand(<vscale x 4 x i64> %broadcast.splatinsert, <vscale x 4 x i1> %0, <vscale x 4 x i1> %1) {
71; CHECK-LABEL: test_mulhu_expand:
72; CHECK:       # %bb.0: # %entry
73; CHECK-NEXT:    addi sp, sp, -16
74; CHECK-NEXT:    .cfi_def_cfa_offset 16
75; CHECK-NEXT:    lui a0, 699051
76; CHECK-NEXT:    addi a1, sp, 8
77; CHECK-NEXT:    addi a2, a0, -1366
78; CHECK-NEXT:    addi a0, a0, -1365
79; CHECK-NEXT:    sw a0, 8(sp)
80; CHECK-NEXT:    sw a2, 12(sp)
81; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
82; CHECK-NEXT:    vlse64.v v12, (a1), zero
83; CHECK-NEXT:    vrgather.vi v16, v8, 0
84; CHECK-NEXT:    vmulhu.vv v8, v16, v12
85; CHECK-NEXT:    vsrl.vi v8, v8, 1
86; CHECK-NEXT:    li a0, 3
87; CHECK-NEXT:    vnmsub.vx v8, a0, v16
88; CHECK-NEXT:    addi sp, sp, 16
89; CHECK-NEXT:    .cfi_def_cfa_offset 0
90; CHECK-NEXT:    ret
91entry:
92  %broadcast.splat = shufflevector <vscale x 4 x i64> %broadcast.splatinsert, <vscale x 4 x i64> zeroinitializer, <vscale x 4 x i32> zeroinitializer
93  %2 = urem <vscale x 4 x i64> %broadcast.splat, shufflevector (<vscale x 4 x i64> insertelement (<vscale x 4 x i64> poison, i64 3, i64 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer)
94 ret <vscale x 4 x i64> %2
95}
96