1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-UNKNOWN 3; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-256 4; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-512 5; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-UNKNOWN 6; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-256 7; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-512 8; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-UNKNOWN 9; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-256 10; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-512 11; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-UNKNOWN 12; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-256 13; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-512 14 15; 16; VECTOR_REVERSE - masks 17; 18 19define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) { 20; RV32-BITS-UNKNOWN-LABEL: reverse_nxv2i1: 21; RV32-BITS-UNKNOWN: # %bb.0: 22; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf4, ta, ma 23; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0 24; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb 25; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0 26; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 2 27; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 28; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma 29; RV32-BITS-UNKNOWN-NEXT: vid.v v9 30; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0 31; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma 32; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9 33; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v10, 0 34; RV32-BITS-UNKNOWN-NEXT: ret 35; 36; RV32-BITS-256-LABEL: reverse_nxv2i1: 37; RV32-BITS-256: # %bb.0: 38; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, mf4, ta, ma 39; RV32-BITS-256-NEXT: vmv.v.i v8, 0 40; RV32-BITS-256-NEXT: csrr a0, vlenb 41; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0 42; RV32-BITS-256-NEXT: srli a0, a0, 2 43; RV32-BITS-256-NEXT: addi a0, a0, -1 44; RV32-BITS-256-NEXT: vid.v v9 45; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a0 46; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v9 47; RV32-BITS-256-NEXT: vmsne.vi v0, v10, 0 48; RV32-BITS-256-NEXT: ret 49; 50; RV32-BITS-512-LABEL: reverse_nxv2i1: 51; RV32-BITS-512: # %bb.0: 52; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, mf4, ta, ma 53; RV32-BITS-512-NEXT: vmv.v.i v8, 0 54; RV32-BITS-512-NEXT: csrr a0, vlenb 55; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0 56; RV32-BITS-512-NEXT: srli a0, a0, 2 57; RV32-BITS-512-NEXT: addi a0, a0, -1 58; RV32-BITS-512-NEXT: vid.v v9 59; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a0 60; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v9 61; RV32-BITS-512-NEXT: vmsne.vi v0, v10, 0 62; RV32-BITS-512-NEXT: ret 63; 64; RV64-BITS-UNKNOWN-LABEL: reverse_nxv2i1: 65; RV64-BITS-UNKNOWN: # %bb.0: 66; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf4, ta, ma 67; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0 68; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb 69; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0 70; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 2 71; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 72; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma 73; RV64-BITS-UNKNOWN-NEXT: vid.v v9 74; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0 75; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma 76; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9 77; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v10, 0 78; RV64-BITS-UNKNOWN-NEXT: ret 79; 80; RV64-BITS-256-LABEL: reverse_nxv2i1: 81; RV64-BITS-256: # %bb.0: 82; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, mf4, ta, ma 83; RV64-BITS-256-NEXT: vmv.v.i v8, 0 84; RV64-BITS-256-NEXT: csrr a0, vlenb 85; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0 86; RV64-BITS-256-NEXT: srli a0, a0, 2 87; RV64-BITS-256-NEXT: addi a0, a0, -1 88; RV64-BITS-256-NEXT: vid.v v9 89; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a0 90; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v9 91; RV64-BITS-256-NEXT: vmsne.vi v0, v10, 0 92; RV64-BITS-256-NEXT: ret 93; 94; RV64-BITS-512-LABEL: reverse_nxv2i1: 95; RV64-BITS-512: # %bb.0: 96; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, mf4, ta, ma 97; RV64-BITS-512-NEXT: vmv.v.i v8, 0 98; RV64-BITS-512-NEXT: csrr a0, vlenb 99; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0 100; RV64-BITS-512-NEXT: srli a0, a0, 2 101; RV64-BITS-512-NEXT: addi a0, a0, -1 102; RV64-BITS-512-NEXT: vid.v v9 103; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0 104; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9 105; RV64-BITS-512-NEXT: vmsne.vi v0, v10, 0 106; RV64-BITS-512-NEXT: ret 107 %res = call <vscale x 2 x i1> @llvm.vector.reverse.nxv2i1(<vscale x 2 x i1> %a) 108 ret <vscale x 2 x i1> %res 109} 110 111define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) { 112; RV32-BITS-UNKNOWN-LABEL: reverse_nxv4i1: 113; RV32-BITS-UNKNOWN: # %bb.0: 114; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma 115; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0 116; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb 117; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0 118; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 1 119; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 120; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m1, ta, ma 121; RV32-BITS-UNKNOWN-NEXT: vid.v v9 122; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0 123; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma 124; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9 125; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v10, 0 126; RV32-BITS-UNKNOWN-NEXT: ret 127; 128; RV32-BITS-256-LABEL: reverse_nxv4i1: 129; RV32-BITS-256: # %bb.0: 130; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, mf2, ta, ma 131; RV32-BITS-256-NEXT: vmv.v.i v8, 0 132; RV32-BITS-256-NEXT: csrr a0, vlenb 133; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0 134; RV32-BITS-256-NEXT: srli a0, a0, 1 135; RV32-BITS-256-NEXT: addi a0, a0, -1 136; RV32-BITS-256-NEXT: vid.v v9 137; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a0 138; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v9 139; RV32-BITS-256-NEXT: vmsne.vi v0, v10, 0 140; RV32-BITS-256-NEXT: ret 141; 142; RV32-BITS-512-LABEL: reverse_nxv4i1: 143; RV32-BITS-512: # %bb.0: 144; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, mf2, ta, ma 145; RV32-BITS-512-NEXT: vmv.v.i v8, 0 146; RV32-BITS-512-NEXT: csrr a0, vlenb 147; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0 148; RV32-BITS-512-NEXT: srli a0, a0, 1 149; RV32-BITS-512-NEXT: addi a0, a0, -1 150; RV32-BITS-512-NEXT: vid.v v9 151; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a0 152; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v9 153; RV32-BITS-512-NEXT: vmsne.vi v0, v10, 0 154; RV32-BITS-512-NEXT: ret 155; 156; RV64-BITS-UNKNOWN-LABEL: reverse_nxv4i1: 157; RV64-BITS-UNKNOWN: # %bb.0: 158; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma 159; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0 160; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb 161; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0 162; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 1 163; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 164; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m1, ta, ma 165; RV64-BITS-UNKNOWN-NEXT: vid.v v9 166; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0 167; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma 168; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9 169; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v10, 0 170; RV64-BITS-UNKNOWN-NEXT: ret 171; 172; RV64-BITS-256-LABEL: reverse_nxv4i1: 173; RV64-BITS-256: # %bb.0: 174; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, mf2, ta, ma 175; RV64-BITS-256-NEXT: vmv.v.i v8, 0 176; RV64-BITS-256-NEXT: csrr a0, vlenb 177; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0 178; RV64-BITS-256-NEXT: srli a0, a0, 1 179; RV64-BITS-256-NEXT: addi a0, a0, -1 180; RV64-BITS-256-NEXT: vid.v v9 181; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a0 182; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v9 183; RV64-BITS-256-NEXT: vmsne.vi v0, v10, 0 184; RV64-BITS-256-NEXT: ret 185; 186; RV64-BITS-512-LABEL: reverse_nxv4i1: 187; RV64-BITS-512: # %bb.0: 188; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, mf2, ta, ma 189; RV64-BITS-512-NEXT: vmv.v.i v8, 0 190; RV64-BITS-512-NEXT: csrr a0, vlenb 191; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0 192; RV64-BITS-512-NEXT: srli a0, a0, 1 193; RV64-BITS-512-NEXT: addi a0, a0, -1 194; RV64-BITS-512-NEXT: vid.v v9 195; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0 196; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9 197; RV64-BITS-512-NEXT: vmsne.vi v0, v10, 0 198; RV64-BITS-512-NEXT: ret 199 %res = call <vscale x 4 x i1> @llvm.vector.reverse.nxv4i1(<vscale x 4 x i1> %a) 200 ret <vscale x 4 x i1> %res 201} 202 203define <vscale x 8 x i1> @reverse_nxv8i1(<vscale x 8 x i1> %a) { 204; RV32-BITS-UNKNOWN-LABEL: reverse_nxv8i1: 205; RV32-BITS-UNKNOWN: # %bb.0: 206; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma 207; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0 208; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb 209; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0 210; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 211; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m2, ta, ma 212; RV32-BITS-UNKNOWN-NEXT: vid.v v10 213; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v10, a0 214; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma 215; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 216; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v9, 0 217; RV32-BITS-UNKNOWN-NEXT: ret 218; 219; RV32-BITS-256-LABEL: reverse_nxv8i1: 220; RV32-BITS-256: # %bb.0: 221; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma 222; RV32-BITS-256-NEXT: vmv.v.i v8, 0 223; RV32-BITS-256-NEXT: csrr a0, vlenb 224; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0 225; RV32-BITS-256-NEXT: addi a0, a0, -1 226; RV32-BITS-256-NEXT: vid.v v9 227; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a0 228; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v9 229; RV32-BITS-256-NEXT: vmsne.vi v0, v10, 0 230; RV32-BITS-256-NEXT: ret 231; 232; RV32-BITS-512-LABEL: reverse_nxv8i1: 233; RV32-BITS-512: # %bb.0: 234; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma 235; RV32-BITS-512-NEXT: vmv.v.i v8, 0 236; RV32-BITS-512-NEXT: csrr a0, vlenb 237; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0 238; RV32-BITS-512-NEXT: addi a0, a0, -1 239; RV32-BITS-512-NEXT: vid.v v9 240; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a0 241; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v9 242; RV32-BITS-512-NEXT: vmsne.vi v0, v10, 0 243; RV32-BITS-512-NEXT: ret 244; 245; RV64-BITS-UNKNOWN-LABEL: reverse_nxv8i1: 246; RV64-BITS-UNKNOWN: # %bb.0: 247; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma 248; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0 249; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb 250; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0 251; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 252; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m2, ta, ma 253; RV64-BITS-UNKNOWN-NEXT: vid.v v10 254; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v10, a0 255; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma 256; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 257; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v9, 0 258; RV64-BITS-UNKNOWN-NEXT: ret 259; 260; RV64-BITS-256-LABEL: reverse_nxv8i1: 261; RV64-BITS-256: # %bb.0: 262; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma 263; RV64-BITS-256-NEXT: vmv.v.i v8, 0 264; RV64-BITS-256-NEXT: csrr a0, vlenb 265; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0 266; RV64-BITS-256-NEXT: addi a0, a0, -1 267; RV64-BITS-256-NEXT: vid.v v9 268; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a0 269; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v9 270; RV64-BITS-256-NEXT: vmsne.vi v0, v10, 0 271; RV64-BITS-256-NEXT: ret 272; 273; RV64-BITS-512-LABEL: reverse_nxv8i1: 274; RV64-BITS-512: # %bb.0: 275; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma 276; RV64-BITS-512-NEXT: vmv.v.i v8, 0 277; RV64-BITS-512-NEXT: csrr a0, vlenb 278; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0 279; RV64-BITS-512-NEXT: addi a0, a0, -1 280; RV64-BITS-512-NEXT: vid.v v9 281; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0 282; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9 283; RV64-BITS-512-NEXT: vmsne.vi v0, v10, 0 284; RV64-BITS-512-NEXT: ret 285 %res = call <vscale x 8 x i1> @llvm.vector.reverse.nxv8i1(<vscale x 8 x i1> %a) 286 ret <vscale x 8 x i1> %res 287} 288 289define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) { 290; RV32-BITS-UNKNOWN-LABEL: reverse_nxv16i1: 291; RV32-BITS-UNKNOWN: # %bb.0: 292; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb 293; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma 294; RV32-BITS-UNKNOWN-NEXT: vid.v v8 295; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e8, m2, ta, ma 296; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v10, 0 297; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 298; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma 299; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v8, v8, a0 300; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m2, ta, ma 301; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v10, v10, 1, v0 302; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma 303; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v10, v8 304; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v11, v8 305; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m2, ta, ma 306; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v12, 0 307; RV32-BITS-UNKNOWN-NEXT: ret 308; 309; RV32-BITS-256-LABEL: reverse_nxv16i1: 310; RV32-BITS-256: # %bb.0: 311; RV32-BITS-256-NEXT: csrr a0, vlenb 312; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma 313; RV32-BITS-256-NEXT: vid.v v8 314; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m2, ta, ma 315; RV32-BITS-256-NEXT: vmv.v.i v10, 0 316; RV32-BITS-256-NEXT: addi a0, a0, -1 317; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma 318; RV32-BITS-256-NEXT: vrsub.vx v8, v8, a0 319; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma 320; RV32-BITS-256-NEXT: vmerge.vim v10, v10, 1, v0 321; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma 322; RV32-BITS-256-NEXT: vrgather.vv v13, v10, v8 323; RV32-BITS-256-NEXT: vrgather.vv v12, v11, v8 324; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma 325; RV32-BITS-256-NEXT: vmsne.vi v0, v12, 0 326; RV32-BITS-256-NEXT: ret 327; 328; RV32-BITS-512-LABEL: reverse_nxv16i1: 329; RV32-BITS-512: # %bb.0: 330; RV32-BITS-512-NEXT: csrr a0, vlenb 331; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma 332; RV32-BITS-512-NEXT: vid.v v8 333; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m2, ta, ma 334; RV32-BITS-512-NEXT: vmv.v.i v10, 0 335; RV32-BITS-512-NEXT: addi a0, a0, -1 336; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma 337; RV32-BITS-512-NEXT: vrsub.vx v8, v8, a0 338; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma 339; RV32-BITS-512-NEXT: vmerge.vim v10, v10, 1, v0 340; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma 341; RV32-BITS-512-NEXT: vrgather.vv v13, v10, v8 342; RV32-BITS-512-NEXT: vrgather.vv v12, v11, v8 343; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma 344; RV32-BITS-512-NEXT: vmsne.vi v0, v12, 0 345; RV32-BITS-512-NEXT: ret 346; 347; RV64-BITS-UNKNOWN-LABEL: reverse_nxv16i1: 348; RV64-BITS-UNKNOWN: # %bb.0: 349; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb 350; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma 351; RV64-BITS-UNKNOWN-NEXT: vid.v v8 352; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e8, m2, ta, ma 353; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v10, 0 354; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 355; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma 356; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v8, v8, a0 357; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m2, ta, ma 358; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v10, v10, 1, v0 359; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma 360; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v10, v8 361; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v11, v8 362; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m2, ta, ma 363; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v12, 0 364; RV64-BITS-UNKNOWN-NEXT: ret 365; 366; RV64-BITS-256-LABEL: reverse_nxv16i1: 367; RV64-BITS-256: # %bb.0: 368; RV64-BITS-256-NEXT: csrr a0, vlenb 369; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma 370; RV64-BITS-256-NEXT: vid.v v8 371; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m2, ta, ma 372; RV64-BITS-256-NEXT: vmv.v.i v10, 0 373; RV64-BITS-256-NEXT: addi a0, a0, -1 374; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma 375; RV64-BITS-256-NEXT: vrsub.vx v8, v8, a0 376; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma 377; RV64-BITS-256-NEXT: vmerge.vim v10, v10, 1, v0 378; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma 379; RV64-BITS-256-NEXT: vrgather.vv v13, v10, v8 380; RV64-BITS-256-NEXT: vrgather.vv v12, v11, v8 381; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma 382; RV64-BITS-256-NEXT: vmsne.vi v0, v12, 0 383; RV64-BITS-256-NEXT: ret 384; 385; RV64-BITS-512-LABEL: reverse_nxv16i1: 386; RV64-BITS-512: # %bb.0: 387; RV64-BITS-512-NEXT: csrr a0, vlenb 388; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma 389; RV64-BITS-512-NEXT: vid.v v8 390; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m2, ta, ma 391; RV64-BITS-512-NEXT: vmv.v.i v10, 0 392; RV64-BITS-512-NEXT: addi a0, a0, -1 393; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma 394; RV64-BITS-512-NEXT: vrsub.vx v8, v8, a0 395; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma 396; RV64-BITS-512-NEXT: vmerge.vim v10, v10, 1, v0 397; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma 398; RV64-BITS-512-NEXT: vrgather.vv v13, v10, v8 399; RV64-BITS-512-NEXT: vrgather.vv v12, v11, v8 400; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma 401; RV64-BITS-512-NEXT: vmsne.vi v0, v12, 0 402; RV64-BITS-512-NEXT: ret 403 %res = call <vscale x 16 x i1> @llvm.vector.reverse.nxv16i1(<vscale x 16 x i1> %a) 404 ret <vscale x 16 x i1> %res 405} 406 407define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) { 408; RV32-BITS-UNKNOWN-LABEL: reverse_nxv32i1: 409; RV32-BITS-UNKNOWN: # %bb.0: 410; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb 411; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma 412; RV32-BITS-UNKNOWN-NEXT: vid.v v8 413; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e8, m4, ta, ma 414; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v12, 0 415; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 416; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma 417; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v16, v8, a0 418; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma 419; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v12, v12, 1, v0 420; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma 421; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v12, v16 422; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v13, v16 423; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v14, v16 424; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v8, v15, v16 425; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma 426; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 427; RV32-BITS-UNKNOWN-NEXT: ret 428; 429; RV32-BITS-256-LABEL: reverse_nxv32i1: 430; RV32-BITS-256: # %bb.0: 431; RV32-BITS-256-NEXT: csrr a0, vlenb 432; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma 433; RV32-BITS-256-NEXT: vid.v v8 434; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m4, ta, ma 435; RV32-BITS-256-NEXT: vmv.v.i v12, 0 436; RV32-BITS-256-NEXT: addi a0, a0, -1 437; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma 438; RV32-BITS-256-NEXT: vrsub.vx v16, v8, a0 439; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma 440; RV32-BITS-256-NEXT: vmerge.vim v12, v12, 1, v0 441; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma 442; RV32-BITS-256-NEXT: vrgather.vv v11, v12, v16 443; RV32-BITS-256-NEXT: vrgather.vv v10, v13, v16 444; RV32-BITS-256-NEXT: vrgather.vv v9, v14, v16 445; RV32-BITS-256-NEXT: vrgather.vv v8, v15, v16 446; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma 447; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0 448; RV32-BITS-256-NEXT: ret 449; 450; RV32-BITS-512-LABEL: reverse_nxv32i1: 451; RV32-BITS-512: # %bb.0: 452; RV32-BITS-512-NEXT: csrr a0, vlenb 453; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma 454; RV32-BITS-512-NEXT: vid.v v8 455; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, ma 456; RV32-BITS-512-NEXT: vmv.v.i v12, 0 457; RV32-BITS-512-NEXT: addi a0, a0, -1 458; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma 459; RV32-BITS-512-NEXT: vrsub.vx v16, v8, a0 460; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma 461; RV32-BITS-512-NEXT: vmerge.vim v12, v12, 1, v0 462; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma 463; RV32-BITS-512-NEXT: vrgather.vv v11, v12, v16 464; RV32-BITS-512-NEXT: vrgather.vv v10, v13, v16 465; RV32-BITS-512-NEXT: vrgather.vv v9, v14, v16 466; RV32-BITS-512-NEXT: vrgather.vv v8, v15, v16 467; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma 468; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0 469; RV32-BITS-512-NEXT: ret 470; 471; RV64-BITS-UNKNOWN-LABEL: reverse_nxv32i1: 472; RV64-BITS-UNKNOWN: # %bb.0: 473; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb 474; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma 475; RV64-BITS-UNKNOWN-NEXT: vid.v v8 476; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e8, m4, ta, ma 477; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v12, 0 478; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 479; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma 480; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v16, v8, a0 481; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma 482; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v12, v12, 1, v0 483; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma 484; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v12, v16 485; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v13, v16 486; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v14, v16 487; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v8, v15, v16 488; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma 489; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 490; RV64-BITS-UNKNOWN-NEXT: ret 491; 492; RV64-BITS-256-LABEL: reverse_nxv32i1: 493; RV64-BITS-256: # %bb.0: 494; RV64-BITS-256-NEXT: csrr a0, vlenb 495; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma 496; RV64-BITS-256-NEXT: vid.v v8 497; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m4, ta, ma 498; RV64-BITS-256-NEXT: vmv.v.i v12, 0 499; RV64-BITS-256-NEXT: addi a0, a0, -1 500; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma 501; RV64-BITS-256-NEXT: vrsub.vx v16, v8, a0 502; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma 503; RV64-BITS-256-NEXT: vmerge.vim v12, v12, 1, v0 504; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma 505; RV64-BITS-256-NEXT: vrgather.vv v11, v12, v16 506; RV64-BITS-256-NEXT: vrgather.vv v10, v13, v16 507; RV64-BITS-256-NEXT: vrgather.vv v9, v14, v16 508; RV64-BITS-256-NEXT: vrgather.vv v8, v15, v16 509; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma 510; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0 511; RV64-BITS-256-NEXT: ret 512; 513; RV64-BITS-512-LABEL: reverse_nxv32i1: 514; RV64-BITS-512: # %bb.0: 515; RV64-BITS-512-NEXT: csrr a0, vlenb 516; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma 517; RV64-BITS-512-NEXT: vid.v v8 518; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, ma 519; RV64-BITS-512-NEXT: vmv.v.i v12, 0 520; RV64-BITS-512-NEXT: addi a0, a0, -1 521; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma 522; RV64-BITS-512-NEXT: vrsub.vx v16, v8, a0 523; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma 524; RV64-BITS-512-NEXT: vmerge.vim v12, v12, 1, v0 525; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma 526; RV64-BITS-512-NEXT: vrgather.vv v11, v12, v16 527; RV64-BITS-512-NEXT: vrgather.vv v10, v13, v16 528; RV64-BITS-512-NEXT: vrgather.vv v9, v14, v16 529; RV64-BITS-512-NEXT: vrgather.vv v8, v15, v16 530; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma 531; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0 532; RV64-BITS-512-NEXT: ret 533 %res = call <vscale x 32 x i1> @llvm.vector.reverse.nxv32i1(<vscale x 32 x i1> %a) 534 ret <vscale x 32 x i1> %res 535} 536 537define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) { 538; RV32-BITS-UNKNOWN-LABEL: reverse_nxv64i1: 539; RV32-BITS-UNKNOWN: # %bb.0: 540; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb 541; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma 542; RV32-BITS-UNKNOWN-NEXT: vid.v v8 543; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e8, m8, ta, ma 544; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v24, 0 545; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 546; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma 547; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v16, v8, a0 548; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma 549; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v24, v24, 1, v0 550; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma 551; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v15, v24, v16 552; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v14, v25, v16 553; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v26, v16 554; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v27, v16 555; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v28, v16 556; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v29, v16 557; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v30, v16 558; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v8, v31, v16 559; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma 560; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 561; RV32-BITS-UNKNOWN-NEXT: ret 562; 563; RV32-BITS-256-LABEL: reverse_nxv64i1: 564; RV32-BITS-256: # %bb.0: 565; RV32-BITS-256-NEXT: csrr a0, vlenb 566; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma 567; RV32-BITS-256-NEXT: vid.v v8 568; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m8, ta, ma 569; RV32-BITS-256-NEXT: vmv.v.i v16, 0 570; RV32-BITS-256-NEXT: addi a0, a0, -1 571; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma 572; RV32-BITS-256-NEXT: vrsub.vx v24, v8, a0 573; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma 574; RV32-BITS-256-NEXT: vmerge.vim v16, v16, 1, v0 575; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma 576; RV32-BITS-256-NEXT: vrgather.vv v15, v16, v24 577; RV32-BITS-256-NEXT: vrgather.vv v14, v17, v24 578; RV32-BITS-256-NEXT: vrgather.vv v13, v18, v24 579; RV32-BITS-256-NEXT: vrgather.vv v12, v19, v24 580; RV32-BITS-256-NEXT: vrgather.vv v11, v20, v24 581; RV32-BITS-256-NEXT: vrgather.vv v10, v21, v24 582; RV32-BITS-256-NEXT: vrgather.vv v9, v22, v24 583; RV32-BITS-256-NEXT: vrgather.vv v8, v23, v24 584; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma 585; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0 586; RV32-BITS-256-NEXT: ret 587; 588; RV32-BITS-512-LABEL: reverse_nxv64i1: 589; RV32-BITS-512: # %bb.0: 590; RV32-BITS-512-NEXT: csrr a0, vlenb 591; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma 592; RV32-BITS-512-NEXT: vid.v v8 593; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m8, ta, ma 594; RV32-BITS-512-NEXT: vmv.v.i v16, 0 595; RV32-BITS-512-NEXT: addi a0, a0, -1 596; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma 597; RV32-BITS-512-NEXT: vrsub.vx v24, v8, a0 598; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma 599; RV32-BITS-512-NEXT: vmerge.vim v16, v16, 1, v0 600; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma 601; RV32-BITS-512-NEXT: vrgather.vv v15, v16, v24 602; RV32-BITS-512-NEXT: vrgather.vv v14, v17, v24 603; RV32-BITS-512-NEXT: vrgather.vv v13, v18, v24 604; RV32-BITS-512-NEXT: vrgather.vv v12, v19, v24 605; RV32-BITS-512-NEXT: vrgather.vv v11, v20, v24 606; RV32-BITS-512-NEXT: vrgather.vv v10, v21, v24 607; RV32-BITS-512-NEXT: vrgather.vv v9, v22, v24 608; RV32-BITS-512-NEXT: vrgather.vv v8, v23, v24 609; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma 610; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0 611; RV32-BITS-512-NEXT: ret 612; 613; RV64-BITS-UNKNOWN-LABEL: reverse_nxv64i1: 614; RV64-BITS-UNKNOWN: # %bb.0: 615; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb 616; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma 617; RV64-BITS-UNKNOWN-NEXT: vid.v v8 618; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e8, m8, ta, ma 619; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v24, 0 620; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 621; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma 622; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v16, v8, a0 623; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma 624; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v24, v24, 1, v0 625; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma 626; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v15, v24, v16 627; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v14, v25, v16 628; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v26, v16 629; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v27, v16 630; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v28, v16 631; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v29, v16 632; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v30, v16 633; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v8, v31, v16 634; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma 635; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 636; RV64-BITS-UNKNOWN-NEXT: ret 637; 638; RV64-BITS-256-LABEL: reverse_nxv64i1: 639; RV64-BITS-256: # %bb.0: 640; RV64-BITS-256-NEXT: csrr a0, vlenb 641; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma 642; RV64-BITS-256-NEXT: vid.v v8 643; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m8, ta, ma 644; RV64-BITS-256-NEXT: vmv.v.i v16, 0 645; RV64-BITS-256-NEXT: addi a0, a0, -1 646; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma 647; RV64-BITS-256-NEXT: vrsub.vx v24, v8, a0 648; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma 649; RV64-BITS-256-NEXT: vmerge.vim v16, v16, 1, v0 650; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma 651; RV64-BITS-256-NEXT: vrgather.vv v15, v16, v24 652; RV64-BITS-256-NEXT: vrgather.vv v14, v17, v24 653; RV64-BITS-256-NEXT: vrgather.vv v13, v18, v24 654; RV64-BITS-256-NEXT: vrgather.vv v12, v19, v24 655; RV64-BITS-256-NEXT: vrgather.vv v11, v20, v24 656; RV64-BITS-256-NEXT: vrgather.vv v10, v21, v24 657; RV64-BITS-256-NEXT: vrgather.vv v9, v22, v24 658; RV64-BITS-256-NEXT: vrgather.vv v8, v23, v24 659; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma 660; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0 661; RV64-BITS-256-NEXT: ret 662; 663; RV64-BITS-512-LABEL: reverse_nxv64i1: 664; RV64-BITS-512: # %bb.0: 665; RV64-BITS-512-NEXT: csrr a0, vlenb 666; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma 667; RV64-BITS-512-NEXT: vid.v v8 668; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m8, ta, ma 669; RV64-BITS-512-NEXT: vmv.v.i v16, 0 670; RV64-BITS-512-NEXT: addi a0, a0, -1 671; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma 672; RV64-BITS-512-NEXT: vrsub.vx v24, v8, a0 673; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma 674; RV64-BITS-512-NEXT: vmerge.vim v16, v16, 1, v0 675; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma 676; RV64-BITS-512-NEXT: vrgather.vv v15, v16, v24 677; RV64-BITS-512-NEXT: vrgather.vv v14, v17, v24 678; RV64-BITS-512-NEXT: vrgather.vv v13, v18, v24 679; RV64-BITS-512-NEXT: vrgather.vv v12, v19, v24 680; RV64-BITS-512-NEXT: vrgather.vv v11, v20, v24 681; RV64-BITS-512-NEXT: vrgather.vv v10, v21, v24 682; RV64-BITS-512-NEXT: vrgather.vv v9, v22, v24 683; RV64-BITS-512-NEXT: vrgather.vv v8, v23, v24 684; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma 685; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0 686; RV64-BITS-512-NEXT: ret 687 %res = call <vscale x 64 x i1> @llvm.vector.reverse.nxv64i1(<vscale x 64 x i1> %a) 688 ret <vscale x 64 x i1> %res 689} 690 691; 692; VECTOR_REVERSE - integer 693; 694 695define <vscale x 1 x i8> @reverse_nxv1i8(<vscale x 1 x i8> %a) { 696; RV32-BITS-UNKNOWN-LABEL: reverse_nxv1i8: 697; RV32-BITS-UNKNOWN: # %bb.0: 698; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb 699; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 3 700; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 701; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma 702; RV32-BITS-UNKNOWN-NEXT: vid.v v9 703; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0 704; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma 705; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 706; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 707; RV32-BITS-UNKNOWN-NEXT: ret 708; 709; RV32-BITS-256-LABEL: reverse_nxv1i8: 710; RV32-BITS-256: # %bb.0: 711; RV32-BITS-256-NEXT: csrr a0, vlenb 712; RV32-BITS-256-NEXT: srli a0, a0, 3 713; RV32-BITS-256-NEXT: addi a0, a0, -1 714; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, mf8, ta, ma 715; RV32-BITS-256-NEXT: vid.v v9 716; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0 717; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10 718; RV32-BITS-256-NEXT: vmv1r.v v8, v9 719; RV32-BITS-256-NEXT: ret 720; 721; RV32-BITS-512-LABEL: reverse_nxv1i8: 722; RV32-BITS-512: # %bb.0: 723; RV32-BITS-512-NEXT: csrr a0, vlenb 724; RV32-BITS-512-NEXT: srli a0, a0, 3 725; RV32-BITS-512-NEXT: addi a0, a0, -1 726; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, mf8, ta, ma 727; RV32-BITS-512-NEXT: vid.v v9 728; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0 729; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10 730; RV32-BITS-512-NEXT: vmv1r.v v8, v9 731; RV32-BITS-512-NEXT: ret 732; 733; RV64-BITS-UNKNOWN-LABEL: reverse_nxv1i8: 734; RV64-BITS-UNKNOWN: # %bb.0: 735; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb 736; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 3 737; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 738; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma 739; RV64-BITS-UNKNOWN-NEXT: vid.v v9 740; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0 741; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma 742; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 743; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 744; RV64-BITS-UNKNOWN-NEXT: ret 745; 746; RV64-BITS-256-LABEL: reverse_nxv1i8: 747; RV64-BITS-256: # %bb.0: 748; RV64-BITS-256-NEXT: csrr a0, vlenb 749; RV64-BITS-256-NEXT: srli a0, a0, 3 750; RV64-BITS-256-NEXT: addi a0, a0, -1 751; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, mf8, ta, ma 752; RV64-BITS-256-NEXT: vid.v v9 753; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0 754; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10 755; RV64-BITS-256-NEXT: vmv1r.v v8, v9 756; RV64-BITS-256-NEXT: ret 757; 758; RV64-BITS-512-LABEL: reverse_nxv1i8: 759; RV64-BITS-512: # %bb.0: 760; RV64-BITS-512-NEXT: csrr a0, vlenb 761; RV64-BITS-512-NEXT: srli a0, a0, 3 762; RV64-BITS-512-NEXT: addi a0, a0, -1 763; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, mf8, ta, ma 764; RV64-BITS-512-NEXT: vid.v v9 765; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0 766; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10 767; RV64-BITS-512-NEXT: vmv1r.v v8, v9 768; RV64-BITS-512-NEXT: ret 769 %res = call <vscale x 1 x i8> @llvm.vector.reverse.nxv1i8(<vscale x 1 x i8> %a) 770 ret <vscale x 1 x i8> %res 771} 772 773define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) { 774; RV32-BITS-UNKNOWN-LABEL: reverse_nxv2i8: 775; RV32-BITS-UNKNOWN: # %bb.0: 776; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb 777; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 2 778; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 779; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma 780; RV32-BITS-UNKNOWN-NEXT: vid.v v9 781; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0 782; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma 783; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 784; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 785; RV32-BITS-UNKNOWN-NEXT: ret 786; 787; RV32-BITS-256-LABEL: reverse_nxv2i8: 788; RV32-BITS-256: # %bb.0: 789; RV32-BITS-256-NEXT: csrr a0, vlenb 790; RV32-BITS-256-NEXT: srli a0, a0, 2 791; RV32-BITS-256-NEXT: addi a0, a0, -1 792; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, mf4, ta, ma 793; RV32-BITS-256-NEXT: vid.v v9 794; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0 795; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10 796; RV32-BITS-256-NEXT: vmv1r.v v8, v9 797; RV32-BITS-256-NEXT: ret 798; 799; RV32-BITS-512-LABEL: reverse_nxv2i8: 800; RV32-BITS-512: # %bb.0: 801; RV32-BITS-512-NEXT: csrr a0, vlenb 802; RV32-BITS-512-NEXT: srli a0, a0, 2 803; RV32-BITS-512-NEXT: addi a0, a0, -1 804; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, mf4, ta, ma 805; RV32-BITS-512-NEXT: vid.v v9 806; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0 807; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10 808; RV32-BITS-512-NEXT: vmv1r.v v8, v9 809; RV32-BITS-512-NEXT: ret 810; 811; RV64-BITS-UNKNOWN-LABEL: reverse_nxv2i8: 812; RV64-BITS-UNKNOWN: # %bb.0: 813; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb 814; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 2 815; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 816; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma 817; RV64-BITS-UNKNOWN-NEXT: vid.v v9 818; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0 819; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma 820; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 821; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 822; RV64-BITS-UNKNOWN-NEXT: ret 823; 824; RV64-BITS-256-LABEL: reverse_nxv2i8: 825; RV64-BITS-256: # %bb.0: 826; RV64-BITS-256-NEXT: csrr a0, vlenb 827; RV64-BITS-256-NEXT: srli a0, a0, 2 828; RV64-BITS-256-NEXT: addi a0, a0, -1 829; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, mf4, ta, ma 830; RV64-BITS-256-NEXT: vid.v v9 831; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0 832; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10 833; RV64-BITS-256-NEXT: vmv1r.v v8, v9 834; RV64-BITS-256-NEXT: ret 835; 836; RV64-BITS-512-LABEL: reverse_nxv2i8: 837; RV64-BITS-512: # %bb.0: 838; RV64-BITS-512-NEXT: csrr a0, vlenb 839; RV64-BITS-512-NEXT: srli a0, a0, 2 840; RV64-BITS-512-NEXT: addi a0, a0, -1 841; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, mf4, ta, ma 842; RV64-BITS-512-NEXT: vid.v v9 843; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0 844; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10 845; RV64-BITS-512-NEXT: vmv1r.v v8, v9 846; RV64-BITS-512-NEXT: ret 847 %res = call <vscale x 2 x i8> @llvm.vector.reverse.nxv2i8(<vscale x 2 x i8> %a) 848 ret <vscale x 2 x i8> %res 849} 850 851define <vscale x 4 x i8> @reverse_nxv4i8(<vscale x 4 x i8> %a) { 852; RV32-BITS-UNKNOWN-LABEL: reverse_nxv4i8: 853; RV32-BITS-UNKNOWN: # %bb.0: 854; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb 855; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 1 856; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 857; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m1, ta, ma 858; RV32-BITS-UNKNOWN-NEXT: vid.v v9 859; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0 860; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma 861; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 862; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 863; RV32-BITS-UNKNOWN-NEXT: ret 864; 865; RV32-BITS-256-LABEL: reverse_nxv4i8: 866; RV32-BITS-256: # %bb.0: 867; RV32-BITS-256-NEXT: csrr a0, vlenb 868; RV32-BITS-256-NEXT: srli a0, a0, 1 869; RV32-BITS-256-NEXT: addi a0, a0, -1 870; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, mf2, ta, ma 871; RV32-BITS-256-NEXT: vid.v v9 872; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0 873; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10 874; RV32-BITS-256-NEXT: vmv1r.v v8, v9 875; RV32-BITS-256-NEXT: ret 876; 877; RV32-BITS-512-LABEL: reverse_nxv4i8: 878; RV32-BITS-512: # %bb.0: 879; RV32-BITS-512-NEXT: csrr a0, vlenb 880; RV32-BITS-512-NEXT: srli a0, a0, 1 881; RV32-BITS-512-NEXT: addi a0, a0, -1 882; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, mf2, ta, ma 883; RV32-BITS-512-NEXT: vid.v v9 884; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0 885; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10 886; RV32-BITS-512-NEXT: vmv1r.v v8, v9 887; RV32-BITS-512-NEXT: ret 888; 889; RV64-BITS-UNKNOWN-LABEL: reverse_nxv4i8: 890; RV64-BITS-UNKNOWN: # %bb.0: 891; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb 892; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 1 893; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 894; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m1, ta, ma 895; RV64-BITS-UNKNOWN-NEXT: vid.v v9 896; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0 897; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma 898; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 899; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 900; RV64-BITS-UNKNOWN-NEXT: ret 901; 902; RV64-BITS-256-LABEL: reverse_nxv4i8: 903; RV64-BITS-256: # %bb.0: 904; RV64-BITS-256-NEXT: csrr a0, vlenb 905; RV64-BITS-256-NEXT: srli a0, a0, 1 906; RV64-BITS-256-NEXT: addi a0, a0, -1 907; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, mf2, ta, ma 908; RV64-BITS-256-NEXT: vid.v v9 909; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0 910; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10 911; RV64-BITS-256-NEXT: vmv1r.v v8, v9 912; RV64-BITS-256-NEXT: ret 913; 914; RV64-BITS-512-LABEL: reverse_nxv4i8: 915; RV64-BITS-512: # %bb.0: 916; RV64-BITS-512-NEXT: csrr a0, vlenb 917; RV64-BITS-512-NEXT: srli a0, a0, 1 918; RV64-BITS-512-NEXT: addi a0, a0, -1 919; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, mf2, ta, ma 920; RV64-BITS-512-NEXT: vid.v v9 921; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0 922; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10 923; RV64-BITS-512-NEXT: vmv1r.v v8, v9 924; RV64-BITS-512-NEXT: ret 925 %res = call <vscale x 4 x i8> @llvm.vector.reverse.nxv4i8(<vscale x 4 x i8> %a) 926 ret <vscale x 4 x i8> %res 927} 928 929define <vscale x 8 x i8> @reverse_nxv8i8(<vscale x 8 x i8> %a) { 930; RV32-BITS-UNKNOWN-LABEL: reverse_nxv8i8: 931; RV32-BITS-UNKNOWN: # %bb.0: 932; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb 933; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 934; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma 935; RV32-BITS-UNKNOWN-NEXT: vid.v v10 936; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v10, a0 937; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma 938; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 939; RV32-BITS-UNKNOWN-NEXT: vmv.v.v v8, v9 940; RV32-BITS-UNKNOWN-NEXT: ret 941; 942; RV32-BITS-256-LABEL: reverse_nxv8i8: 943; RV32-BITS-256: # %bb.0: 944; RV32-BITS-256-NEXT: csrr a0, vlenb 945; RV32-BITS-256-NEXT: addi a0, a0, -1 946; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma 947; RV32-BITS-256-NEXT: vid.v v9 948; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0 949; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10 950; RV32-BITS-256-NEXT: vmv.v.v v8, v9 951; RV32-BITS-256-NEXT: ret 952; 953; RV32-BITS-512-LABEL: reverse_nxv8i8: 954; RV32-BITS-512: # %bb.0: 955; RV32-BITS-512-NEXT: csrr a0, vlenb 956; RV32-BITS-512-NEXT: addi a0, a0, -1 957; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma 958; RV32-BITS-512-NEXT: vid.v v9 959; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0 960; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10 961; RV32-BITS-512-NEXT: vmv.v.v v8, v9 962; RV32-BITS-512-NEXT: ret 963; 964; RV64-BITS-UNKNOWN-LABEL: reverse_nxv8i8: 965; RV64-BITS-UNKNOWN: # %bb.0: 966; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb 967; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 968; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma 969; RV64-BITS-UNKNOWN-NEXT: vid.v v10 970; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v10, a0 971; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma 972; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 973; RV64-BITS-UNKNOWN-NEXT: vmv.v.v v8, v9 974; RV64-BITS-UNKNOWN-NEXT: ret 975; 976; RV64-BITS-256-LABEL: reverse_nxv8i8: 977; RV64-BITS-256: # %bb.0: 978; RV64-BITS-256-NEXT: csrr a0, vlenb 979; RV64-BITS-256-NEXT: addi a0, a0, -1 980; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma 981; RV64-BITS-256-NEXT: vid.v v9 982; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0 983; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10 984; RV64-BITS-256-NEXT: vmv.v.v v8, v9 985; RV64-BITS-256-NEXT: ret 986; 987; RV64-BITS-512-LABEL: reverse_nxv8i8: 988; RV64-BITS-512: # %bb.0: 989; RV64-BITS-512-NEXT: csrr a0, vlenb 990; RV64-BITS-512-NEXT: addi a0, a0, -1 991; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma 992; RV64-BITS-512-NEXT: vid.v v9 993; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0 994; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10 995; RV64-BITS-512-NEXT: vmv.v.v v8, v9 996; RV64-BITS-512-NEXT: ret 997 %res = call <vscale x 8 x i8> @llvm.vector.reverse.nxv8i8(<vscale x 8 x i8> %a) 998 ret <vscale x 8 x i8> %res 999} 1000 1001define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) { 1002; RV32-BITS-UNKNOWN-LABEL: reverse_nxv16i8: 1003; RV32-BITS-UNKNOWN: # %bb.0: 1004; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb 1005; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 1006; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma 1007; RV32-BITS-UNKNOWN-NEXT: vid.v v10 1008; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v12, v10, a0 1009; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma 1010; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v8, v12 1011; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v9, v12 1012; RV32-BITS-UNKNOWN-NEXT: vmv2r.v v8, v10 1013; RV32-BITS-UNKNOWN-NEXT: ret 1014; 1015; RV32-BITS-256-LABEL: reverse_nxv16i8: 1016; RV32-BITS-256: # %bb.0: 1017; RV32-BITS-256-NEXT: csrr a0, vlenb 1018; RV32-BITS-256-NEXT: addi a0, a0, -1 1019; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma 1020; RV32-BITS-256-NEXT: vid.v v10 1021; RV32-BITS-256-NEXT: vrsub.vx v12, v10, a0 1022; RV32-BITS-256-NEXT: vrgather.vv v11, v8, v12 1023; RV32-BITS-256-NEXT: vrgather.vv v10, v9, v12 1024; RV32-BITS-256-NEXT: vmv2r.v v8, v10 1025; RV32-BITS-256-NEXT: ret 1026; 1027; RV32-BITS-512-LABEL: reverse_nxv16i8: 1028; RV32-BITS-512: # %bb.0: 1029; RV32-BITS-512-NEXT: csrr a0, vlenb 1030; RV32-BITS-512-NEXT: addi a0, a0, -1 1031; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma 1032; RV32-BITS-512-NEXT: vid.v v10 1033; RV32-BITS-512-NEXT: vrsub.vx v12, v10, a0 1034; RV32-BITS-512-NEXT: vrgather.vv v11, v8, v12 1035; RV32-BITS-512-NEXT: vrgather.vv v10, v9, v12 1036; RV32-BITS-512-NEXT: vmv2r.v v8, v10 1037; RV32-BITS-512-NEXT: ret 1038; 1039; RV64-BITS-UNKNOWN-LABEL: reverse_nxv16i8: 1040; RV64-BITS-UNKNOWN: # %bb.0: 1041; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb 1042; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 1043; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma 1044; RV64-BITS-UNKNOWN-NEXT: vid.v v10 1045; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v12, v10, a0 1046; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma 1047; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v8, v12 1048; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v9, v12 1049; RV64-BITS-UNKNOWN-NEXT: vmv2r.v v8, v10 1050; RV64-BITS-UNKNOWN-NEXT: ret 1051; 1052; RV64-BITS-256-LABEL: reverse_nxv16i8: 1053; RV64-BITS-256: # %bb.0: 1054; RV64-BITS-256-NEXT: csrr a0, vlenb 1055; RV64-BITS-256-NEXT: addi a0, a0, -1 1056; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma 1057; RV64-BITS-256-NEXT: vid.v v10 1058; RV64-BITS-256-NEXT: vrsub.vx v12, v10, a0 1059; RV64-BITS-256-NEXT: vrgather.vv v11, v8, v12 1060; RV64-BITS-256-NEXT: vrgather.vv v10, v9, v12 1061; RV64-BITS-256-NEXT: vmv2r.v v8, v10 1062; RV64-BITS-256-NEXT: ret 1063; 1064; RV64-BITS-512-LABEL: reverse_nxv16i8: 1065; RV64-BITS-512: # %bb.0: 1066; RV64-BITS-512-NEXT: csrr a0, vlenb 1067; RV64-BITS-512-NEXT: addi a0, a0, -1 1068; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma 1069; RV64-BITS-512-NEXT: vid.v v10 1070; RV64-BITS-512-NEXT: vrsub.vx v12, v10, a0 1071; RV64-BITS-512-NEXT: vrgather.vv v11, v8, v12 1072; RV64-BITS-512-NEXT: vrgather.vv v10, v9, v12 1073; RV64-BITS-512-NEXT: vmv2r.v v8, v10 1074; RV64-BITS-512-NEXT: ret 1075 %res = call <vscale x 16 x i8> @llvm.vector.reverse.nxv16i8(<vscale x 16 x i8> %a) 1076 ret <vscale x 16 x i8> %res 1077} 1078 1079define <vscale x 32 x i8> @reverse_nxv32i8(<vscale x 32 x i8> %a) { 1080; RV32-BITS-UNKNOWN-LABEL: reverse_nxv32i8: 1081; RV32-BITS-UNKNOWN: # %bb.0: 1082; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb 1083; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 1084; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma 1085; RV32-BITS-UNKNOWN-NEXT: vid.v v12 1086; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v16, v12, a0 1087; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma 1088; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v15, v8, v16 1089; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v14, v9, v16 1090; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v10, v16 1091; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v11, v16 1092; RV32-BITS-UNKNOWN-NEXT: vmv4r.v v8, v12 1093; RV32-BITS-UNKNOWN-NEXT: ret 1094; 1095; RV32-BITS-256-LABEL: reverse_nxv32i8: 1096; RV32-BITS-256: # %bb.0: 1097; RV32-BITS-256-NEXT: csrr a0, vlenb 1098; RV32-BITS-256-NEXT: addi a0, a0, -1 1099; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma 1100; RV32-BITS-256-NEXT: vid.v v12 1101; RV32-BITS-256-NEXT: vrsub.vx v16, v12, a0 1102; RV32-BITS-256-NEXT: vrgather.vv v15, v8, v16 1103; RV32-BITS-256-NEXT: vrgather.vv v14, v9, v16 1104; RV32-BITS-256-NEXT: vrgather.vv v13, v10, v16 1105; RV32-BITS-256-NEXT: vrgather.vv v12, v11, v16 1106; RV32-BITS-256-NEXT: vmv4r.v v8, v12 1107; RV32-BITS-256-NEXT: ret 1108; 1109; RV32-BITS-512-LABEL: reverse_nxv32i8: 1110; RV32-BITS-512: # %bb.0: 1111; RV32-BITS-512-NEXT: csrr a0, vlenb 1112; RV32-BITS-512-NEXT: addi a0, a0, -1 1113; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma 1114; RV32-BITS-512-NEXT: vid.v v12 1115; RV32-BITS-512-NEXT: vrsub.vx v16, v12, a0 1116; RV32-BITS-512-NEXT: vrgather.vv v15, v8, v16 1117; RV32-BITS-512-NEXT: vrgather.vv v14, v9, v16 1118; RV32-BITS-512-NEXT: vrgather.vv v13, v10, v16 1119; RV32-BITS-512-NEXT: vrgather.vv v12, v11, v16 1120; RV32-BITS-512-NEXT: vmv4r.v v8, v12 1121; RV32-BITS-512-NEXT: ret 1122; 1123; RV64-BITS-UNKNOWN-LABEL: reverse_nxv32i8: 1124; RV64-BITS-UNKNOWN: # %bb.0: 1125; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb 1126; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 1127; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma 1128; RV64-BITS-UNKNOWN-NEXT: vid.v v12 1129; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v16, v12, a0 1130; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma 1131; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v15, v8, v16 1132; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v14, v9, v16 1133; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v10, v16 1134; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v11, v16 1135; RV64-BITS-UNKNOWN-NEXT: vmv4r.v v8, v12 1136; RV64-BITS-UNKNOWN-NEXT: ret 1137; 1138; RV64-BITS-256-LABEL: reverse_nxv32i8: 1139; RV64-BITS-256: # %bb.0: 1140; RV64-BITS-256-NEXT: csrr a0, vlenb 1141; RV64-BITS-256-NEXT: addi a0, a0, -1 1142; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma 1143; RV64-BITS-256-NEXT: vid.v v12 1144; RV64-BITS-256-NEXT: vrsub.vx v16, v12, a0 1145; RV64-BITS-256-NEXT: vrgather.vv v15, v8, v16 1146; RV64-BITS-256-NEXT: vrgather.vv v14, v9, v16 1147; RV64-BITS-256-NEXT: vrgather.vv v13, v10, v16 1148; RV64-BITS-256-NEXT: vrgather.vv v12, v11, v16 1149; RV64-BITS-256-NEXT: vmv4r.v v8, v12 1150; RV64-BITS-256-NEXT: ret 1151; 1152; RV64-BITS-512-LABEL: reverse_nxv32i8: 1153; RV64-BITS-512: # %bb.0: 1154; RV64-BITS-512-NEXT: csrr a0, vlenb 1155; RV64-BITS-512-NEXT: addi a0, a0, -1 1156; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma 1157; RV64-BITS-512-NEXT: vid.v v12 1158; RV64-BITS-512-NEXT: vrsub.vx v16, v12, a0 1159; RV64-BITS-512-NEXT: vrgather.vv v15, v8, v16 1160; RV64-BITS-512-NEXT: vrgather.vv v14, v9, v16 1161; RV64-BITS-512-NEXT: vrgather.vv v13, v10, v16 1162; RV64-BITS-512-NEXT: vrgather.vv v12, v11, v16 1163; RV64-BITS-512-NEXT: vmv4r.v v8, v12 1164; RV64-BITS-512-NEXT: ret 1165 %res = call <vscale x 32 x i8> @llvm.vector.reverse.nxv32i8(<vscale x 32 x i8> %a) 1166 ret <vscale x 32 x i8> %res 1167} 1168 1169define <vscale x 64 x i8> @reverse_nxv64i8(<vscale x 64 x i8> %a) { 1170; RV32-BITS-UNKNOWN-LABEL: reverse_nxv64i8: 1171; RV32-BITS-UNKNOWN: # %bb.0: 1172; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1173; RV32-BITS-UNKNOWN-NEXT: vmv8r.v v16, v8 1174; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb 1175; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 1176; RV32-BITS-UNKNOWN-NEXT: vid.v v8 1177; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v24, v8, a0 1178; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma 1179; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v15, v16, v24 1180; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v14, v17, v24 1181; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v18, v24 1182; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v19, v24 1183; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v20, v24 1184; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v21, v24 1185; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v22, v24 1186; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v8, v23, v24 1187; RV32-BITS-UNKNOWN-NEXT: ret 1188; 1189; RV32-BITS-256-LABEL: reverse_nxv64i8: 1190; RV32-BITS-256: # %bb.0: 1191; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma 1192; RV32-BITS-256-NEXT: vmv8r.v v16, v8 1193; RV32-BITS-256-NEXT: csrr a0, vlenb 1194; RV32-BITS-256-NEXT: addi a0, a0, -1 1195; RV32-BITS-256-NEXT: vid.v v8 1196; RV32-BITS-256-NEXT: vrsub.vx v24, v8, a0 1197; RV32-BITS-256-NEXT: vrgather.vv v15, v16, v24 1198; RV32-BITS-256-NEXT: vrgather.vv v14, v17, v24 1199; RV32-BITS-256-NEXT: vrgather.vv v13, v18, v24 1200; RV32-BITS-256-NEXT: vrgather.vv v12, v19, v24 1201; RV32-BITS-256-NEXT: vrgather.vv v11, v20, v24 1202; RV32-BITS-256-NEXT: vrgather.vv v10, v21, v24 1203; RV32-BITS-256-NEXT: vrgather.vv v9, v22, v24 1204; RV32-BITS-256-NEXT: vrgather.vv v8, v23, v24 1205; RV32-BITS-256-NEXT: ret 1206; 1207; RV32-BITS-512-LABEL: reverse_nxv64i8: 1208; RV32-BITS-512: # %bb.0: 1209; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma 1210; RV32-BITS-512-NEXT: vmv8r.v v16, v8 1211; RV32-BITS-512-NEXT: csrr a0, vlenb 1212; RV32-BITS-512-NEXT: addi a0, a0, -1 1213; RV32-BITS-512-NEXT: vid.v v8 1214; RV32-BITS-512-NEXT: vrsub.vx v24, v8, a0 1215; RV32-BITS-512-NEXT: vrgather.vv v15, v16, v24 1216; RV32-BITS-512-NEXT: vrgather.vv v14, v17, v24 1217; RV32-BITS-512-NEXT: vrgather.vv v13, v18, v24 1218; RV32-BITS-512-NEXT: vrgather.vv v12, v19, v24 1219; RV32-BITS-512-NEXT: vrgather.vv v11, v20, v24 1220; RV32-BITS-512-NEXT: vrgather.vv v10, v21, v24 1221; RV32-BITS-512-NEXT: vrgather.vv v9, v22, v24 1222; RV32-BITS-512-NEXT: vrgather.vv v8, v23, v24 1223; RV32-BITS-512-NEXT: ret 1224; 1225; RV64-BITS-UNKNOWN-LABEL: reverse_nxv64i8: 1226; RV64-BITS-UNKNOWN: # %bb.0: 1227; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1228; RV64-BITS-UNKNOWN-NEXT: vmv8r.v v16, v8 1229; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb 1230; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 1231; RV64-BITS-UNKNOWN-NEXT: vid.v v8 1232; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v24, v8, a0 1233; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma 1234; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v15, v16, v24 1235; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v14, v17, v24 1236; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v13, v18, v24 1237; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v19, v24 1238; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v20, v24 1239; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v21, v24 1240; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v22, v24 1241; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v8, v23, v24 1242; RV64-BITS-UNKNOWN-NEXT: ret 1243; 1244; RV64-BITS-256-LABEL: reverse_nxv64i8: 1245; RV64-BITS-256: # %bb.0: 1246; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma 1247; RV64-BITS-256-NEXT: vmv8r.v v16, v8 1248; RV64-BITS-256-NEXT: csrr a0, vlenb 1249; RV64-BITS-256-NEXT: addi a0, a0, -1 1250; RV64-BITS-256-NEXT: vid.v v8 1251; RV64-BITS-256-NEXT: vrsub.vx v24, v8, a0 1252; RV64-BITS-256-NEXT: vrgather.vv v15, v16, v24 1253; RV64-BITS-256-NEXT: vrgather.vv v14, v17, v24 1254; RV64-BITS-256-NEXT: vrgather.vv v13, v18, v24 1255; RV64-BITS-256-NEXT: vrgather.vv v12, v19, v24 1256; RV64-BITS-256-NEXT: vrgather.vv v11, v20, v24 1257; RV64-BITS-256-NEXT: vrgather.vv v10, v21, v24 1258; RV64-BITS-256-NEXT: vrgather.vv v9, v22, v24 1259; RV64-BITS-256-NEXT: vrgather.vv v8, v23, v24 1260; RV64-BITS-256-NEXT: ret 1261; 1262; RV64-BITS-512-LABEL: reverse_nxv64i8: 1263; RV64-BITS-512: # %bb.0: 1264; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma 1265; RV64-BITS-512-NEXT: vmv8r.v v16, v8 1266; RV64-BITS-512-NEXT: csrr a0, vlenb 1267; RV64-BITS-512-NEXT: addi a0, a0, -1 1268; RV64-BITS-512-NEXT: vid.v v8 1269; RV64-BITS-512-NEXT: vrsub.vx v24, v8, a0 1270; RV64-BITS-512-NEXT: vrgather.vv v15, v16, v24 1271; RV64-BITS-512-NEXT: vrgather.vv v14, v17, v24 1272; RV64-BITS-512-NEXT: vrgather.vv v13, v18, v24 1273; RV64-BITS-512-NEXT: vrgather.vv v12, v19, v24 1274; RV64-BITS-512-NEXT: vrgather.vv v11, v20, v24 1275; RV64-BITS-512-NEXT: vrgather.vv v10, v21, v24 1276; RV64-BITS-512-NEXT: vrgather.vv v9, v22, v24 1277; RV64-BITS-512-NEXT: vrgather.vv v8, v23, v24 1278; RV64-BITS-512-NEXT: ret 1279 %res = call <vscale x 64 x i8> @llvm.vector.reverse.nxv64i8(<vscale x 64 x i8> %a) 1280 ret <vscale x 64 x i8> %res 1281} 1282 1283define <vscale x 1 x i16> @reverse_nxv1i16(<vscale x 1 x i16> %a) { 1284; CHECK-LABEL: reverse_nxv1i16: 1285; CHECK: # %bb.0: 1286; CHECK-NEXT: csrr a0, vlenb 1287; CHECK-NEXT: srli a0, a0, 3 1288; CHECK-NEXT: addi a0, a0, -1 1289; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma 1290; CHECK-NEXT: vid.v v9 1291; CHECK-NEXT: vrsub.vx v10, v9, a0 1292; CHECK-NEXT: vrgather.vv v9, v8, v10 1293; CHECK-NEXT: vmv1r.v v8, v9 1294; CHECK-NEXT: ret 1295 %res = call <vscale x 1 x i16> @llvm.vector.reverse.nxv1i16(<vscale x 1 x i16> %a) 1296 ret <vscale x 1 x i16> %res 1297} 1298 1299define <vscale x 2 x i16> @reverse_nxv2i16(<vscale x 2 x i16> %a) { 1300; CHECK-LABEL: reverse_nxv2i16: 1301; CHECK: # %bb.0: 1302; CHECK-NEXT: csrr a0, vlenb 1303; CHECK-NEXT: srli a0, a0, 2 1304; CHECK-NEXT: addi a0, a0, -1 1305; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma 1306; CHECK-NEXT: vid.v v9 1307; CHECK-NEXT: vrsub.vx v10, v9, a0 1308; CHECK-NEXT: vrgather.vv v9, v8, v10 1309; CHECK-NEXT: vmv1r.v v8, v9 1310; CHECK-NEXT: ret 1311 %res = call <vscale x 2 x i16> @llvm.vector.reverse.nxv2i16(<vscale x 2 x i16> %a) 1312 ret <vscale x 2 x i16> %res 1313} 1314 1315define <vscale x 4 x i16> @reverse_nxv4i16(<vscale x 4 x i16> %a) { 1316; CHECK-LABEL: reverse_nxv4i16: 1317; CHECK: # %bb.0: 1318; CHECK-NEXT: csrr a0, vlenb 1319; CHECK-NEXT: srli a0, a0, 1 1320; CHECK-NEXT: addi a0, a0, -1 1321; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma 1322; CHECK-NEXT: vid.v v9 1323; CHECK-NEXT: vrsub.vx v10, v9, a0 1324; CHECK-NEXT: vrgather.vv v9, v8, v10 1325; CHECK-NEXT: vmv.v.v v8, v9 1326; CHECK-NEXT: ret 1327 %res = call <vscale x 4 x i16> @llvm.vector.reverse.nxv4i16(<vscale x 4 x i16> %a) 1328 ret <vscale x 4 x i16> %res 1329} 1330 1331define <vscale x 8 x i16> @reverse_nxv8i16(<vscale x 8 x i16> %a) { 1332; CHECK-LABEL: reverse_nxv8i16: 1333; CHECK: # %bb.0: 1334; CHECK-NEXT: csrr a0, vlenb 1335; CHECK-NEXT: srli a0, a0, 1 1336; CHECK-NEXT: addi a0, a0, -1 1337; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma 1338; CHECK-NEXT: vid.v v10 1339; CHECK-NEXT: vrsub.vx v12, v10, a0 1340; CHECK-NEXT: vrgather.vv v11, v8, v12 1341; CHECK-NEXT: vrgather.vv v10, v9, v12 1342; CHECK-NEXT: vmv2r.v v8, v10 1343; CHECK-NEXT: ret 1344 %res = call <vscale x 8 x i16> @llvm.vector.reverse.nxv8i16(<vscale x 8 x i16> %a) 1345 ret <vscale x 8 x i16> %res 1346} 1347 1348define <vscale x 16 x i16> @reverse_nxv16i16(<vscale x 16 x i16> %a) { 1349; CHECK-LABEL: reverse_nxv16i16: 1350; CHECK: # %bb.0: 1351; CHECK-NEXT: csrr a0, vlenb 1352; CHECK-NEXT: srli a0, a0, 1 1353; CHECK-NEXT: addi a0, a0, -1 1354; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma 1355; CHECK-NEXT: vid.v v12 1356; CHECK-NEXT: vrsub.vx v16, v12, a0 1357; CHECK-NEXT: vrgather.vv v15, v8, v16 1358; CHECK-NEXT: vrgather.vv v14, v9, v16 1359; CHECK-NEXT: vrgather.vv v13, v10, v16 1360; CHECK-NEXT: vrgather.vv v12, v11, v16 1361; CHECK-NEXT: vmv4r.v v8, v12 1362; CHECK-NEXT: ret 1363 %res = call <vscale x 16 x i16> @llvm.vector.reverse.nxv16i16(<vscale x 16 x i16> %a) 1364 ret <vscale x 16 x i16> %res 1365} 1366 1367define <vscale x 32 x i16> @reverse_nxv32i16(<vscale x 32 x i16> %a) { 1368; CHECK-LABEL: reverse_nxv32i16: 1369; CHECK: # %bb.0: 1370; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma 1371; CHECK-NEXT: vmv8r.v v16, v8 1372; CHECK-NEXT: csrr a0, vlenb 1373; CHECK-NEXT: srli a0, a0, 1 1374; CHECK-NEXT: addi a0, a0, -1 1375; CHECK-NEXT: vid.v v8 1376; CHECK-NEXT: vrsub.vx v24, v8, a0 1377; CHECK-NEXT: vrgather.vv v15, v16, v24 1378; CHECK-NEXT: vrgather.vv v14, v17, v24 1379; CHECK-NEXT: vrgather.vv v13, v18, v24 1380; CHECK-NEXT: vrgather.vv v12, v19, v24 1381; CHECK-NEXT: vrgather.vv v11, v20, v24 1382; CHECK-NEXT: vrgather.vv v10, v21, v24 1383; CHECK-NEXT: vrgather.vv v9, v22, v24 1384; CHECK-NEXT: vrgather.vv v8, v23, v24 1385; CHECK-NEXT: ret 1386 %res = call <vscale x 32 x i16> @llvm.vector.reverse.nxv32i16(<vscale x 32 x i16> %a) 1387 ret <vscale x 32 x i16> %res 1388} 1389 1390define <vscale x 1 x i32> @reverse_nxv1i32(<vscale x 1 x i32> %a) { 1391; CHECK-LABEL: reverse_nxv1i32: 1392; CHECK: # %bb.0: 1393; CHECK-NEXT: csrr a0, vlenb 1394; CHECK-NEXT: srli a0, a0, 3 1395; CHECK-NEXT: addi a0, a0, -1 1396; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma 1397; CHECK-NEXT: vid.v v9 1398; CHECK-NEXT: vrsub.vx v10, v9, a0 1399; CHECK-NEXT: vrgather.vv v9, v8, v10 1400; CHECK-NEXT: vmv1r.v v8, v9 1401; CHECK-NEXT: ret 1402 %res = call <vscale x 1 x i32> @llvm.vector.reverse.nxv1i32(<vscale x 1 x i32> %a) 1403 ret <vscale x 1 x i32> %res 1404} 1405 1406define <vscale x 2 x i32> @reverse_nxv2i32(<vscale x 2 x i32> %a) { 1407; CHECK-LABEL: reverse_nxv2i32: 1408; CHECK: # %bb.0: 1409; CHECK-NEXT: csrr a0, vlenb 1410; CHECK-NEXT: srli a0, a0, 2 1411; CHECK-NEXT: addi a0, a0, -1 1412; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma 1413; CHECK-NEXT: vid.v v9 1414; CHECK-NEXT: vrsub.vx v10, v9, a0 1415; CHECK-NEXT: vrgather.vv v9, v8, v10 1416; CHECK-NEXT: vmv.v.v v8, v9 1417; CHECK-NEXT: ret 1418 %res = call <vscale x 2 x i32> @llvm.vector.reverse.nxv2i32(<vscale x 2 x i32> %a) 1419 ret <vscale x 2 x i32> %res 1420} 1421 1422define <vscale x 4 x i32> @reverse_nxv4i32(<vscale x 4 x i32> %a) { 1423; CHECK-LABEL: reverse_nxv4i32: 1424; CHECK: # %bb.0: 1425; CHECK-NEXT: csrr a0, vlenb 1426; CHECK-NEXT: srli a0, a0, 2 1427; CHECK-NEXT: addi a0, a0, -1 1428; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma 1429; CHECK-NEXT: vid.v v10 1430; CHECK-NEXT: vrsub.vx v12, v10, a0 1431; CHECK-NEXT: vrgather.vv v11, v8, v12 1432; CHECK-NEXT: vrgather.vv v10, v9, v12 1433; CHECK-NEXT: vmv2r.v v8, v10 1434; CHECK-NEXT: ret 1435 %res = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> %a) 1436 ret <vscale x 4 x i32> %res 1437} 1438 1439define <vscale x 8 x i32> @reverse_nxv8i32(<vscale x 8 x i32> %a) { 1440; CHECK-LABEL: reverse_nxv8i32: 1441; CHECK: # %bb.0: 1442; CHECK-NEXT: csrr a0, vlenb 1443; CHECK-NEXT: srli a0, a0, 2 1444; CHECK-NEXT: addi a0, a0, -1 1445; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma 1446; CHECK-NEXT: vid.v v12 1447; CHECK-NEXT: vrsub.vx v16, v12, a0 1448; CHECK-NEXT: vrgather.vv v15, v8, v16 1449; CHECK-NEXT: vrgather.vv v14, v9, v16 1450; CHECK-NEXT: vrgather.vv v13, v10, v16 1451; CHECK-NEXT: vrgather.vv v12, v11, v16 1452; CHECK-NEXT: vmv4r.v v8, v12 1453; CHECK-NEXT: ret 1454 %res = call <vscale x 8 x i32> @llvm.vector.reverse.nxv8i32(<vscale x 8 x i32> %a) 1455 ret <vscale x 8 x i32> %res 1456} 1457 1458define <vscale x 16 x i32> @reverse_nxv16i32(<vscale x 16 x i32> %a) { 1459; CHECK-LABEL: reverse_nxv16i32: 1460; CHECK: # %bb.0: 1461; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma 1462; CHECK-NEXT: vmv8r.v v16, v8 1463; CHECK-NEXT: csrr a0, vlenb 1464; CHECK-NEXT: srli a0, a0, 2 1465; CHECK-NEXT: addi a0, a0, -1 1466; CHECK-NEXT: vid.v v8 1467; CHECK-NEXT: vrsub.vx v24, v8, a0 1468; CHECK-NEXT: vrgather.vv v15, v16, v24 1469; CHECK-NEXT: vrgather.vv v14, v17, v24 1470; CHECK-NEXT: vrgather.vv v13, v18, v24 1471; CHECK-NEXT: vrgather.vv v12, v19, v24 1472; CHECK-NEXT: vrgather.vv v11, v20, v24 1473; CHECK-NEXT: vrgather.vv v10, v21, v24 1474; CHECK-NEXT: vrgather.vv v9, v22, v24 1475; CHECK-NEXT: vrgather.vv v8, v23, v24 1476; CHECK-NEXT: ret 1477 %res = call <vscale x 16 x i32> @llvm.vector.reverse.nxv16i32(<vscale x 16 x i32> %a) 1478 ret <vscale x 16 x i32> %res 1479} 1480 1481define <vscale x 1 x i64> @reverse_nxv1i64(<vscale x 1 x i64> %a) { 1482; CHECK-LABEL: reverse_nxv1i64: 1483; CHECK: # %bb.0: 1484; CHECK-NEXT: csrr a0, vlenb 1485; CHECK-NEXT: srli a0, a0, 3 1486; CHECK-NEXT: addi a0, a0, -1 1487; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma 1488; CHECK-NEXT: vid.v v9 1489; CHECK-NEXT: vrsub.vx v10, v9, a0 1490; CHECK-NEXT: vrgather.vv v9, v8, v10 1491; CHECK-NEXT: vmv.v.v v8, v9 1492; CHECK-NEXT: ret 1493 %res = call <vscale x 1 x i64> @llvm.vector.reverse.nxv1i64(<vscale x 1 x i64> %a) 1494 ret <vscale x 1 x i64> %res 1495} 1496 1497define <vscale x 2 x i64> @reverse_nxv2i64(<vscale x 2 x i64> %a) { 1498; CHECK-LABEL: reverse_nxv2i64: 1499; CHECK: # %bb.0: 1500; CHECK-NEXT: csrr a0, vlenb 1501; CHECK-NEXT: srli a0, a0, 3 1502; CHECK-NEXT: addi a0, a0, -1 1503; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma 1504; CHECK-NEXT: vid.v v10 1505; CHECK-NEXT: vrsub.vx v12, v10, a0 1506; CHECK-NEXT: vrgather.vv v11, v8, v12 1507; CHECK-NEXT: vrgather.vv v10, v9, v12 1508; CHECK-NEXT: vmv2r.v v8, v10 1509; CHECK-NEXT: ret 1510 %res = call <vscale x 2 x i64> @llvm.vector.reverse.nxv2i64(<vscale x 2 x i64> %a) 1511 ret <vscale x 2 x i64> %res 1512} 1513 1514define <vscale x 4 x i64> @reverse_nxv4i64(<vscale x 4 x i64> %a) { 1515; CHECK-LABEL: reverse_nxv4i64: 1516; CHECK: # %bb.0: 1517; CHECK-NEXT: csrr a0, vlenb 1518; CHECK-NEXT: srli a0, a0, 3 1519; CHECK-NEXT: addi a0, a0, -1 1520; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma 1521; CHECK-NEXT: vid.v v12 1522; CHECK-NEXT: vrsub.vx v16, v12, a0 1523; CHECK-NEXT: vrgather.vv v15, v8, v16 1524; CHECK-NEXT: vrgather.vv v14, v9, v16 1525; CHECK-NEXT: vrgather.vv v13, v10, v16 1526; CHECK-NEXT: vrgather.vv v12, v11, v16 1527; CHECK-NEXT: vmv4r.v v8, v12 1528; CHECK-NEXT: ret 1529 %res = call <vscale x 4 x i64> @llvm.vector.reverse.nxv4i64(<vscale x 4 x i64> %a) 1530 ret <vscale x 4 x i64> %res 1531} 1532 1533define <vscale x 8 x i64> @reverse_nxv8i64(<vscale x 8 x i64> %a) { 1534; CHECK-LABEL: reverse_nxv8i64: 1535; CHECK: # %bb.0: 1536; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma 1537; CHECK-NEXT: vmv8r.v v16, v8 1538; CHECK-NEXT: csrr a0, vlenb 1539; CHECK-NEXT: srli a0, a0, 3 1540; CHECK-NEXT: addi a0, a0, -1 1541; CHECK-NEXT: vid.v v8 1542; CHECK-NEXT: vrsub.vx v24, v8, a0 1543; CHECK-NEXT: vrgather.vv v15, v16, v24 1544; CHECK-NEXT: vrgather.vv v14, v17, v24 1545; CHECK-NEXT: vrgather.vv v13, v18, v24 1546; CHECK-NEXT: vrgather.vv v12, v19, v24 1547; CHECK-NEXT: vrgather.vv v11, v20, v24 1548; CHECK-NEXT: vrgather.vv v10, v21, v24 1549; CHECK-NEXT: vrgather.vv v9, v22, v24 1550; CHECK-NEXT: vrgather.vv v8, v23, v24 1551; CHECK-NEXT: ret 1552 %res = call <vscale x 8 x i64> @llvm.vector.reverse.nxv8i64(<vscale x 8 x i64> %a) 1553 ret <vscale x 8 x i64> %res 1554} 1555 1556; 1557; VECTOR_REVERSE - floating point 1558; 1559 1560define <vscale x 1 x bfloat> @reverse_nxv1bf16(<vscale x 1 x bfloat> %a) { 1561; CHECK-LABEL: reverse_nxv1bf16: 1562; CHECK: # %bb.0: 1563; CHECK-NEXT: csrr a0, vlenb 1564; CHECK-NEXT: srli a0, a0, 3 1565; CHECK-NEXT: addi a0, a0, -1 1566; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma 1567; CHECK-NEXT: vid.v v9 1568; CHECK-NEXT: vrsub.vx v10, v9, a0 1569; CHECK-NEXT: vrgather.vv v9, v8, v10 1570; CHECK-NEXT: vmv1r.v v8, v9 1571; CHECK-NEXT: ret 1572 %res = call <vscale x 1 x bfloat> @llvm.vector.reverse.nxv1bf16(<vscale x 1 x bfloat> %a) 1573 ret <vscale x 1 x bfloat> %res 1574} 1575 1576define <vscale x 2 x bfloat> @reverse_nxv2bf16(<vscale x 2 x bfloat> %a) { 1577; CHECK-LABEL: reverse_nxv2bf16: 1578; CHECK: # %bb.0: 1579; CHECK-NEXT: csrr a0, vlenb 1580; CHECK-NEXT: srli a0, a0, 2 1581; CHECK-NEXT: addi a0, a0, -1 1582; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma 1583; CHECK-NEXT: vid.v v9 1584; CHECK-NEXT: vrsub.vx v10, v9, a0 1585; CHECK-NEXT: vrgather.vv v9, v8, v10 1586; CHECK-NEXT: vmv1r.v v8, v9 1587; CHECK-NEXT: ret 1588 %res = call <vscale x 2 x bfloat> @llvm.vector.reverse.nxv2bf16(<vscale x 2 x bfloat> %a) 1589 ret <vscale x 2 x bfloat> %res 1590} 1591 1592define <vscale x 4 x bfloat> @reverse_nxv4bf16(<vscale x 4 x bfloat> %a) { 1593; CHECK-LABEL: reverse_nxv4bf16: 1594; CHECK: # %bb.0: 1595; CHECK-NEXT: csrr a0, vlenb 1596; CHECK-NEXT: srli a0, a0, 1 1597; CHECK-NEXT: addi a0, a0, -1 1598; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma 1599; CHECK-NEXT: vid.v v9 1600; CHECK-NEXT: vrsub.vx v10, v9, a0 1601; CHECK-NEXT: vrgather.vv v9, v8, v10 1602; CHECK-NEXT: vmv.v.v v8, v9 1603; CHECK-NEXT: ret 1604 %res = call <vscale x 4 x bfloat> @llvm.vector.reverse.nxv4bf16(<vscale x 4 x bfloat> %a) 1605 ret <vscale x 4 x bfloat> %res 1606} 1607 1608define <vscale x 8 x bfloat> @reverse_nxv8bf16(<vscale x 8 x bfloat> %a) { 1609; CHECK-LABEL: reverse_nxv8bf16: 1610; CHECK: # %bb.0: 1611; CHECK-NEXT: csrr a0, vlenb 1612; CHECK-NEXT: srli a0, a0, 1 1613; CHECK-NEXT: addi a0, a0, -1 1614; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma 1615; CHECK-NEXT: vid.v v10 1616; CHECK-NEXT: vrsub.vx v12, v10, a0 1617; CHECK-NEXT: vrgather.vv v11, v8, v12 1618; CHECK-NEXT: vrgather.vv v10, v9, v12 1619; CHECK-NEXT: vmv2r.v v8, v10 1620; CHECK-NEXT: ret 1621 %res = call <vscale x 8 x bfloat> @llvm.vector.reverse.nxv8bf16(<vscale x 8 x bfloat> %a) 1622 ret <vscale x 8 x bfloat> %res 1623} 1624 1625define <vscale x 16 x bfloat> @reverse_nxv16bf16(<vscale x 16 x bfloat> %a) { 1626; CHECK-LABEL: reverse_nxv16bf16: 1627; CHECK: # %bb.0: 1628; CHECK-NEXT: csrr a0, vlenb 1629; CHECK-NEXT: srli a0, a0, 1 1630; CHECK-NEXT: addi a0, a0, -1 1631; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma 1632; CHECK-NEXT: vid.v v12 1633; CHECK-NEXT: vrsub.vx v16, v12, a0 1634; CHECK-NEXT: vrgather.vv v15, v8, v16 1635; CHECK-NEXT: vrgather.vv v14, v9, v16 1636; CHECK-NEXT: vrgather.vv v13, v10, v16 1637; CHECK-NEXT: vrgather.vv v12, v11, v16 1638; CHECK-NEXT: vmv4r.v v8, v12 1639; CHECK-NEXT: ret 1640 %res = call <vscale x 16 x bfloat> @llvm.vector.reverse.nxv16bf16(<vscale x 16 x bfloat> %a) 1641 ret <vscale x 16 x bfloat> %res 1642} 1643 1644define <vscale x 32 x bfloat> @reverse_nxv32bf16(<vscale x 32 x bfloat> %a) { 1645; CHECK-LABEL: reverse_nxv32bf16: 1646; CHECK: # %bb.0: 1647; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma 1648; CHECK-NEXT: vmv8r.v v16, v8 1649; CHECK-NEXT: csrr a0, vlenb 1650; CHECK-NEXT: srli a0, a0, 1 1651; CHECK-NEXT: addi a0, a0, -1 1652; CHECK-NEXT: vid.v v8 1653; CHECK-NEXT: vrsub.vx v24, v8, a0 1654; CHECK-NEXT: vrgather.vv v15, v16, v24 1655; CHECK-NEXT: vrgather.vv v14, v17, v24 1656; CHECK-NEXT: vrgather.vv v13, v18, v24 1657; CHECK-NEXT: vrgather.vv v12, v19, v24 1658; CHECK-NEXT: vrgather.vv v11, v20, v24 1659; CHECK-NEXT: vrgather.vv v10, v21, v24 1660; CHECK-NEXT: vrgather.vv v9, v22, v24 1661; CHECK-NEXT: vrgather.vv v8, v23, v24 1662; CHECK-NEXT: ret 1663 %res = call <vscale x 32 x bfloat> @llvm.vector.reverse.nxv32bf16(<vscale x 32 x bfloat> %a) 1664 ret <vscale x 32 x bfloat> %res 1665} 1666 1667define <vscale x 1 x half> @reverse_nxv1f16(<vscale x 1 x half> %a) { 1668; CHECK-LABEL: reverse_nxv1f16: 1669; CHECK: # %bb.0: 1670; CHECK-NEXT: csrr a0, vlenb 1671; CHECK-NEXT: srli a0, a0, 3 1672; CHECK-NEXT: addi a0, a0, -1 1673; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma 1674; CHECK-NEXT: vid.v v9 1675; CHECK-NEXT: vrsub.vx v10, v9, a0 1676; CHECK-NEXT: vrgather.vv v9, v8, v10 1677; CHECK-NEXT: vmv1r.v v8, v9 1678; CHECK-NEXT: ret 1679 %res = call <vscale x 1 x half> @llvm.vector.reverse.nxv1f16(<vscale x 1 x half> %a) 1680 ret <vscale x 1 x half> %res 1681} 1682 1683define <vscale x 2 x half> @reverse_nxv2f16(<vscale x 2 x half> %a) { 1684; CHECK-LABEL: reverse_nxv2f16: 1685; CHECK: # %bb.0: 1686; CHECK-NEXT: csrr a0, vlenb 1687; CHECK-NEXT: srli a0, a0, 2 1688; CHECK-NEXT: addi a0, a0, -1 1689; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma 1690; CHECK-NEXT: vid.v v9 1691; CHECK-NEXT: vrsub.vx v10, v9, a0 1692; CHECK-NEXT: vrgather.vv v9, v8, v10 1693; CHECK-NEXT: vmv1r.v v8, v9 1694; CHECK-NEXT: ret 1695 %res = call <vscale x 2 x half> @llvm.vector.reverse.nxv2f16(<vscale x 2 x half> %a) 1696 ret <vscale x 2 x half> %res 1697} 1698 1699define <vscale x 4 x half> @reverse_nxv4f16(<vscale x 4 x half> %a) { 1700; CHECK-LABEL: reverse_nxv4f16: 1701; CHECK: # %bb.0: 1702; CHECK-NEXT: csrr a0, vlenb 1703; CHECK-NEXT: srli a0, a0, 1 1704; CHECK-NEXT: addi a0, a0, -1 1705; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma 1706; CHECK-NEXT: vid.v v9 1707; CHECK-NEXT: vrsub.vx v10, v9, a0 1708; CHECK-NEXT: vrgather.vv v9, v8, v10 1709; CHECK-NEXT: vmv.v.v v8, v9 1710; CHECK-NEXT: ret 1711 %res = call <vscale x 4 x half> @llvm.vector.reverse.nxv4f16(<vscale x 4 x half> %a) 1712 ret <vscale x 4 x half> %res 1713} 1714 1715define <vscale x 8 x half> @reverse_nxv8f16(<vscale x 8 x half> %a) { 1716; CHECK-LABEL: reverse_nxv8f16: 1717; CHECK: # %bb.0: 1718; CHECK-NEXT: csrr a0, vlenb 1719; CHECK-NEXT: srli a0, a0, 1 1720; CHECK-NEXT: addi a0, a0, -1 1721; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma 1722; CHECK-NEXT: vid.v v10 1723; CHECK-NEXT: vrsub.vx v12, v10, a0 1724; CHECK-NEXT: vrgather.vv v11, v8, v12 1725; CHECK-NEXT: vrgather.vv v10, v9, v12 1726; CHECK-NEXT: vmv2r.v v8, v10 1727; CHECK-NEXT: ret 1728 %res = call <vscale x 8 x half> @llvm.vector.reverse.nxv8f16(<vscale x 8 x half> %a) 1729 ret <vscale x 8 x half> %res 1730} 1731 1732define <vscale x 16 x half> @reverse_nxv16f16(<vscale x 16 x half> %a) { 1733; CHECK-LABEL: reverse_nxv16f16: 1734; CHECK: # %bb.0: 1735; CHECK-NEXT: csrr a0, vlenb 1736; CHECK-NEXT: srli a0, a0, 1 1737; CHECK-NEXT: addi a0, a0, -1 1738; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma 1739; CHECK-NEXT: vid.v v12 1740; CHECK-NEXT: vrsub.vx v16, v12, a0 1741; CHECK-NEXT: vrgather.vv v15, v8, v16 1742; CHECK-NEXT: vrgather.vv v14, v9, v16 1743; CHECK-NEXT: vrgather.vv v13, v10, v16 1744; CHECK-NEXT: vrgather.vv v12, v11, v16 1745; CHECK-NEXT: vmv4r.v v8, v12 1746; CHECK-NEXT: ret 1747 %res = call <vscale x 16 x half> @llvm.vector.reverse.nxv16f16(<vscale x 16 x half> %a) 1748 ret <vscale x 16 x half> %res 1749} 1750 1751define <vscale x 32 x half> @reverse_nxv32f16(<vscale x 32 x half> %a) { 1752; CHECK-LABEL: reverse_nxv32f16: 1753; CHECK: # %bb.0: 1754; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma 1755; CHECK-NEXT: vmv8r.v v16, v8 1756; CHECK-NEXT: csrr a0, vlenb 1757; CHECK-NEXT: srli a0, a0, 1 1758; CHECK-NEXT: addi a0, a0, -1 1759; CHECK-NEXT: vid.v v8 1760; CHECK-NEXT: vrsub.vx v24, v8, a0 1761; CHECK-NEXT: vrgather.vv v15, v16, v24 1762; CHECK-NEXT: vrgather.vv v14, v17, v24 1763; CHECK-NEXT: vrgather.vv v13, v18, v24 1764; CHECK-NEXT: vrgather.vv v12, v19, v24 1765; CHECK-NEXT: vrgather.vv v11, v20, v24 1766; CHECK-NEXT: vrgather.vv v10, v21, v24 1767; CHECK-NEXT: vrgather.vv v9, v22, v24 1768; CHECK-NEXT: vrgather.vv v8, v23, v24 1769; CHECK-NEXT: ret 1770 %res = call <vscale x 32 x half> @llvm.vector.reverse.nxv32f16(<vscale x 32 x half> %a) 1771 ret <vscale x 32 x half> %res 1772} 1773 1774define <vscale x 1 x float> @reverse_nxv1f32(<vscale x 1 x float> %a) { 1775; CHECK-LABEL: reverse_nxv1f32: 1776; CHECK: # %bb.0: 1777; CHECK-NEXT: csrr a0, vlenb 1778; CHECK-NEXT: srli a0, a0, 3 1779; CHECK-NEXT: addi a0, a0, -1 1780; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma 1781; CHECK-NEXT: vid.v v9 1782; CHECK-NEXT: vrsub.vx v10, v9, a0 1783; CHECK-NEXT: vrgather.vv v9, v8, v10 1784; CHECK-NEXT: vmv1r.v v8, v9 1785; CHECK-NEXT: ret 1786 %res = call <vscale x 1 x float> @llvm.vector.reverse.nxv1f32(<vscale x 1 x float> %a) 1787 ret <vscale x 1 x float> %res 1788} 1789 1790define <vscale x 2 x float> @reverse_nxv2f32(<vscale x 2 x float> %a) { 1791; CHECK-LABEL: reverse_nxv2f32: 1792; CHECK: # %bb.0: 1793; CHECK-NEXT: csrr a0, vlenb 1794; CHECK-NEXT: srli a0, a0, 2 1795; CHECK-NEXT: addi a0, a0, -1 1796; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma 1797; CHECK-NEXT: vid.v v9 1798; CHECK-NEXT: vrsub.vx v10, v9, a0 1799; CHECK-NEXT: vrgather.vv v9, v8, v10 1800; CHECK-NEXT: vmv.v.v v8, v9 1801; CHECK-NEXT: ret 1802 %res = call <vscale x 2 x float> @llvm.vector.reverse.nxv2f32(<vscale x 2 x float> %a) 1803 ret <vscale x 2 x float> %res 1804} 1805 1806define <vscale x 4 x float> @reverse_nxv4f32(<vscale x 4 x float> %a) { 1807; CHECK-LABEL: reverse_nxv4f32: 1808; CHECK: # %bb.0: 1809; CHECK-NEXT: csrr a0, vlenb 1810; CHECK-NEXT: srli a0, a0, 2 1811; CHECK-NEXT: addi a0, a0, -1 1812; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma 1813; CHECK-NEXT: vid.v v10 1814; CHECK-NEXT: vrsub.vx v12, v10, a0 1815; CHECK-NEXT: vrgather.vv v11, v8, v12 1816; CHECK-NEXT: vrgather.vv v10, v9, v12 1817; CHECK-NEXT: vmv2r.v v8, v10 1818; CHECK-NEXT: ret 1819 %res = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> %a) 1820 ret <vscale x 4 x float> %res 1821} 1822 1823define <vscale x 8 x float> @reverse_nxv8f32(<vscale x 8 x float> %a) { 1824; CHECK-LABEL: reverse_nxv8f32: 1825; CHECK: # %bb.0: 1826; CHECK-NEXT: csrr a0, vlenb 1827; CHECK-NEXT: srli a0, a0, 2 1828; CHECK-NEXT: addi a0, a0, -1 1829; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma 1830; CHECK-NEXT: vid.v v12 1831; CHECK-NEXT: vrsub.vx v16, v12, a0 1832; CHECK-NEXT: vrgather.vv v15, v8, v16 1833; CHECK-NEXT: vrgather.vv v14, v9, v16 1834; CHECK-NEXT: vrgather.vv v13, v10, v16 1835; CHECK-NEXT: vrgather.vv v12, v11, v16 1836; CHECK-NEXT: vmv4r.v v8, v12 1837; CHECK-NEXT: ret 1838 %res = call <vscale x 8 x float> @llvm.vector.reverse.nxv8f32(<vscale x 8 x float> %a) 1839 ret <vscale x 8 x float> %res 1840} 1841 1842define <vscale x 16 x float> @reverse_nxv16f32(<vscale x 16 x float> %a) { 1843; CHECK-LABEL: reverse_nxv16f32: 1844; CHECK: # %bb.0: 1845; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma 1846; CHECK-NEXT: vmv8r.v v16, v8 1847; CHECK-NEXT: csrr a0, vlenb 1848; CHECK-NEXT: srli a0, a0, 2 1849; CHECK-NEXT: addi a0, a0, -1 1850; CHECK-NEXT: vid.v v8 1851; CHECK-NEXT: vrsub.vx v24, v8, a0 1852; CHECK-NEXT: vrgather.vv v15, v16, v24 1853; CHECK-NEXT: vrgather.vv v14, v17, v24 1854; CHECK-NEXT: vrgather.vv v13, v18, v24 1855; CHECK-NEXT: vrgather.vv v12, v19, v24 1856; CHECK-NEXT: vrgather.vv v11, v20, v24 1857; CHECK-NEXT: vrgather.vv v10, v21, v24 1858; CHECK-NEXT: vrgather.vv v9, v22, v24 1859; CHECK-NEXT: vrgather.vv v8, v23, v24 1860; CHECK-NEXT: ret 1861 %res = call <vscale x 16 x float> @llvm.vector.reverse.nxv16f32(<vscale x 16 x float> %a) 1862 ret <vscale x 16 x float> %res 1863} 1864 1865define <vscale x 1 x double> @reverse_nxv1f64(<vscale x 1 x double> %a) { 1866; CHECK-LABEL: reverse_nxv1f64: 1867; CHECK: # %bb.0: 1868; CHECK-NEXT: csrr a0, vlenb 1869; CHECK-NEXT: srli a0, a0, 3 1870; CHECK-NEXT: addi a0, a0, -1 1871; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma 1872; CHECK-NEXT: vid.v v9 1873; CHECK-NEXT: vrsub.vx v10, v9, a0 1874; CHECK-NEXT: vrgather.vv v9, v8, v10 1875; CHECK-NEXT: vmv.v.v v8, v9 1876; CHECK-NEXT: ret 1877 %res = call <vscale x 1 x double> @llvm.vector.reverse.nxv1f64(<vscale x 1 x double> %a) 1878 ret <vscale x 1 x double> %res 1879} 1880 1881define <vscale x 2 x double> @reverse_nxv2f64(<vscale x 2 x double> %a) { 1882; CHECK-LABEL: reverse_nxv2f64: 1883; CHECK: # %bb.0: 1884; CHECK-NEXT: csrr a0, vlenb 1885; CHECK-NEXT: srli a0, a0, 3 1886; CHECK-NEXT: addi a0, a0, -1 1887; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma 1888; CHECK-NEXT: vid.v v10 1889; CHECK-NEXT: vrsub.vx v12, v10, a0 1890; CHECK-NEXT: vrgather.vv v11, v8, v12 1891; CHECK-NEXT: vrgather.vv v10, v9, v12 1892; CHECK-NEXT: vmv2r.v v8, v10 1893; CHECK-NEXT: ret 1894 %res = call <vscale x 2 x double> @llvm.vector.reverse.nxv2f64(<vscale x 2 x double> %a) 1895 ret <vscale x 2 x double> %res 1896} 1897 1898define <vscale x 4 x double> @reverse_nxv4f64(<vscale x 4 x double> %a) { 1899; CHECK-LABEL: reverse_nxv4f64: 1900; CHECK: # %bb.0: 1901; CHECK-NEXT: csrr a0, vlenb 1902; CHECK-NEXT: srli a0, a0, 3 1903; CHECK-NEXT: addi a0, a0, -1 1904; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma 1905; CHECK-NEXT: vid.v v12 1906; CHECK-NEXT: vrsub.vx v16, v12, a0 1907; CHECK-NEXT: vrgather.vv v15, v8, v16 1908; CHECK-NEXT: vrgather.vv v14, v9, v16 1909; CHECK-NEXT: vrgather.vv v13, v10, v16 1910; CHECK-NEXT: vrgather.vv v12, v11, v16 1911; CHECK-NEXT: vmv4r.v v8, v12 1912; CHECK-NEXT: ret 1913 %res = call <vscale x 4 x double> @llvm.vector.reverse.nxv4f64(<vscale x 4 x double> %a) 1914 ret <vscale x 4 x double> %res 1915} 1916 1917define <vscale x 8 x double> @reverse_nxv8f64(<vscale x 8 x double> %a) { 1918; CHECK-LABEL: reverse_nxv8f64: 1919; CHECK: # %bb.0: 1920; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma 1921; CHECK-NEXT: vmv8r.v v16, v8 1922; CHECK-NEXT: csrr a0, vlenb 1923; CHECK-NEXT: srli a0, a0, 3 1924; CHECK-NEXT: addi a0, a0, -1 1925; CHECK-NEXT: vid.v v8 1926; CHECK-NEXT: vrsub.vx v24, v8, a0 1927; CHECK-NEXT: vrgather.vv v15, v16, v24 1928; CHECK-NEXT: vrgather.vv v14, v17, v24 1929; CHECK-NEXT: vrgather.vv v13, v18, v24 1930; CHECK-NEXT: vrgather.vv v12, v19, v24 1931; CHECK-NEXT: vrgather.vv v11, v20, v24 1932; CHECK-NEXT: vrgather.vv v10, v21, v24 1933; CHECK-NEXT: vrgather.vv v9, v22, v24 1934; CHECK-NEXT: vrgather.vv v8, v23, v24 1935; CHECK-NEXT: ret 1936 %res = call <vscale x 8 x double> @llvm.vector.reverse.nxv8f64(<vscale x 8 x double> %a) 1937 ret <vscale x 8 x double> %res 1938} 1939 1940; Test widen reverse vector 1941 1942define <vscale x 3 x i64> @reverse_nxv3i64(<vscale x 3 x i64> %a) { 1943; CHECK-LABEL: reverse_nxv3i64: 1944; CHECK: # %bb.0: 1945; CHECK-NEXT: csrr a0, vlenb 1946; CHECK-NEXT: srli a0, a0, 3 1947; CHECK-NEXT: addi a0, a0, -1 1948; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma 1949; CHECK-NEXT: vid.v v12 1950; CHECK-NEXT: vrsub.vx v14, v12, a0 1951; CHECK-NEXT: vrgather.vv v13, v10, v14 1952; CHECK-NEXT: vrgather.vv v10, v9, v14 1953; CHECK-NEXT: vmv.v.v v12, v13 1954; CHECK-NEXT: vrgather.vv v15, v8, v14 1955; CHECK-NEXT: vmv.v.v v13, v10 1956; CHECK-NEXT: vrgather.vv v8, v11, v14 1957; CHECK-NEXT: vmv.v.v v14, v15 1958; CHECK-NEXT: vmv4r.v v8, v12 1959; CHECK-NEXT: ret 1960 %res = call <vscale x 3 x i64> @llvm.vector.reverse.nxv3i64(<vscale x 3 x i64> %a) 1961 ret <vscale x 3 x i64> %res 1962} 1963 1964define <vscale x 6 x i64> @reverse_nxv6i64(<vscale x 6 x i64> %a) { 1965; CHECK-LABEL: reverse_nxv6i64: 1966; CHECK: # %bb.0: 1967; CHECK-NEXT: csrr a0, vlenb 1968; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma 1969; CHECK-NEXT: vid.v v16 1970; CHECK-NEXT: srli a0, a0, 3 1971; CHECK-NEXT: addi a0, a0, -1 1972; CHECK-NEXT: vrsub.vx v22, v16, a0 1973; CHECK-NEXT: vrgather.vv v21, v10, v22 1974; CHECK-NEXT: vrgather.vv v19, v12, v22 1975; CHECK-NEXT: vrgather.vv v18, v13, v22 1976; CHECK-NEXT: vrgather.vv v20, v11, v22 1977; CHECK-NEXT: vmv2r.v v16, v18 1978; CHECK-NEXT: vmv2r.v v18, v20 1979; CHECK-NEXT: vrgather.vv v31, v8, v22 1980; CHECK-NEXT: vrgather.vv v30, v9, v22 1981; CHECK-NEXT: vrgather.vv v9, v14, v22 1982; CHECK-NEXT: vrgather.vv v8, v15, v22 1983; CHECK-NEXT: vmv2r.v v20, v30 1984; CHECK-NEXT: vmv8r.v v8, v16 1985; CHECK-NEXT: ret 1986 %res = call <vscale x 6 x i64> @llvm.vector.reverse.nxv6i64(<vscale x 6 x i64> %a) 1987 ret <vscale x 6 x i64> %res 1988} 1989 1990define <vscale x 12 x i64> @reverse_nxv12i64(<vscale x 12 x i64> %a) { 1991; RV32-LABEL: reverse_nxv12i64: 1992; RV32: # %bb.0: 1993; RV32-NEXT: addi sp, sp, -80 1994; RV32-NEXT: .cfi_def_cfa_offset 80 1995; RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill 1996; RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill 1997; RV32-NEXT: .cfi_offset ra, -4 1998; RV32-NEXT: .cfi_offset s0, -8 1999; RV32-NEXT: addi s0, sp, 80 2000; RV32-NEXT: .cfi_def_cfa s0, 0 2001; RV32-NEXT: csrr a0, vlenb 2002; RV32-NEXT: slli a0, a0, 4 2003; RV32-NEXT: sub sp, sp, a0 2004; RV32-NEXT: andi sp, sp, -64 2005; RV32-NEXT: csrr a0, vlenb 2006; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma 2007; RV32-NEXT: vid.v v20 2008; RV32-NEXT: srli a1, a0, 3 2009; RV32-NEXT: addi a1, a1, -1 2010; RV32-NEXT: vrsub.vx v20, v20, a1 2011; RV32-NEXT: vrgather.vv v31, v12, v20 2012; RV32-NEXT: vrgather.vv v7, v8, v20 2013; RV32-NEXT: vrgather.vv v30, v13, v20 2014; RV32-NEXT: vrgather.vv v6, v9, v20 2015; RV32-NEXT: vrgather.vv v29, v14, v20 2016; RV32-NEXT: vrgather.vv v5, v10, v20 2017; RV32-NEXT: vrgather.vv v28, v15, v20 2018; RV32-NEXT: vrgather.vv v4, v11, v20 2019; RV32-NEXT: addi a1, sp, 64 2020; RV32-NEXT: slli a0, a0, 3 2021; RV32-NEXT: add a0, a1, a0 2022; RV32-NEXT: vrgather.vv v27, v16, v20 2023; RV32-NEXT: vs4r.v v4, (a0) 2024; RV32-NEXT: vrgather.vv v26, v17, v20 2025; RV32-NEXT: vrgather.vv v25, v18, v20 2026; RV32-NEXT: vrgather.vv v24, v19, v20 2027; RV32-NEXT: vs8r.v v24, (a1) 2028; RV32-NEXT: vl8re64.v v16, (a0) 2029; RV32-NEXT: vl8re64.v v8, (a1) 2030; RV32-NEXT: addi sp, s0, -80 2031; RV32-NEXT: .cfi_def_cfa sp, 80 2032; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload 2033; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload 2034; RV32-NEXT: .cfi_restore ra 2035; RV32-NEXT: .cfi_restore s0 2036; RV32-NEXT: addi sp, sp, 80 2037; RV32-NEXT: .cfi_def_cfa_offset 0 2038; RV32-NEXT: ret 2039; 2040; RV64-LABEL: reverse_nxv12i64: 2041; RV64: # %bb.0: 2042; RV64-NEXT: addi sp, sp, -80 2043; RV64-NEXT: .cfi_def_cfa_offset 80 2044; RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill 2045; RV64-NEXT: sd s0, 64(sp) # 8-byte Folded Spill 2046; RV64-NEXT: .cfi_offset ra, -8 2047; RV64-NEXT: .cfi_offset s0, -16 2048; RV64-NEXT: addi s0, sp, 80 2049; RV64-NEXT: .cfi_def_cfa s0, 0 2050; RV64-NEXT: csrr a0, vlenb 2051; RV64-NEXT: slli a0, a0, 4 2052; RV64-NEXT: sub sp, sp, a0 2053; RV64-NEXT: andi sp, sp, -64 2054; RV64-NEXT: csrr a0, vlenb 2055; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma 2056; RV64-NEXT: vid.v v20 2057; RV64-NEXT: srli a1, a0, 3 2058; RV64-NEXT: addi a1, a1, -1 2059; RV64-NEXT: vrsub.vx v20, v20, a1 2060; RV64-NEXT: vrgather.vv v31, v12, v20 2061; RV64-NEXT: vrgather.vv v7, v8, v20 2062; RV64-NEXT: vrgather.vv v30, v13, v20 2063; RV64-NEXT: vrgather.vv v6, v9, v20 2064; RV64-NEXT: vrgather.vv v29, v14, v20 2065; RV64-NEXT: vrgather.vv v5, v10, v20 2066; RV64-NEXT: vrgather.vv v28, v15, v20 2067; RV64-NEXT: vrgather.vv v4, v11, v20 2068; RV64-NEXT: addi a1, sp, 64 2069; RV64-NEXT: slli a0, a0, 3 2070; RV64-NEXT: add a0, a1, a0 2071; RV64-NEXT: vrgather.vv v27, v16, v20 2072; RV64-NEXT: vs4r.v v4, (a0) 2073; RV64-NEXT: vrgather.vv v26, v17, v20 2074; RV64-NEXT: vrgather.vv v25, v18, v20 2075; RV64-NEXT: vrgather.vv v24, v19, v20 2076; RV64-NEXT: vs8r.v v24, (a1) 2077; RV64-NEXT: vl8re64.v v16, (a0) 2078; RV64-NEXT: vl8re64.v v8, (a1) 2079; RV64-NEXT: addi sp, s0, -80 2080; RV64-NEXT: .cfi_def_cfa sp, 80 2081; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload 2082; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload 2083; RV64-NEXT: .cfi_restore ra 2084; RV64-NEXT: .cfi_restore s0 2085; RV64-NEXT: addi sp, sp, 80 2086; RV64-NEXT: .cfi_def_cfa_offset 0 2087; RV64-NEXT: ret 2088 %res = call <vscale x 12 x i64> @llvm.vector.reverse.nxv12i64(<vscale x 12 x i64> %a) 2089 ret <vscale x 12 x i64> %res 2090} 2091 2092declare <vscale x 2 x i1> @llvm.vector.reverse.nxv2i1(<vscale x 2 x i1>) 2093declare <vscale x 4 x i1> @llvm.vector.reverse.nxv4i1(<vscale x 4 x i1>) 2094declare <vscale x 8 x i1> @llvm.vector.reverse.nxv8i1(<vscale x 8 x i1>) 2095declare <vscale x 16 x i1> @llvm.vector.reverse.nxv16i1(<vscale x 16 x i1>) 2096declare <vscale x 32 x i1> @llvm.vector.reverse.nxv32i1(<vscale x 32 x i1>) 2097declare <vscale x 64 x i1> @llvm.vector.reverse.nxv64i1(<vscale x 64 x i1>) 2098declare <vscale x 1 x i8> @llvm.vector.reverse.nxv1i8(<vscale x 1 x i8>) 2099declare <vscale x 2 x i8> @llvm.vector.reverse.nxv2i8(<vscale x 2 x i8>) 2100declare <vscale x 4 x i8> @llvm.vector.reverse.nxv4i8(<vscale x 4 x i8>) 2101declare <vscale x 8 x i8> @llvm.vector.reverse.nxv8i8(<vscale x 8 x i8>) 2102declare <vscale x 16 x i8> @llvm.vector.reverse.nxv16i8(<vscale x 16 x i8>) 2103declare <vscale x 32 x i8> @llvm.vector.reverse.nxv32i8(<vscale x 32 x i8>) 2104declare <vscale x 64 x i8> @llvm.vector.reverse.nxv64i8(<vscale x 64 x i8>) 2105declare <vscale x 1 x i16> @llvm.vector.reverse.nxv1i16(<vscale x 1 x i16>) 2106declare <vscale x 2 x i16> @llvm.vector.reverse.nxv2i16(<vscale x 2 x i16>) 2107declare <vscale x 4 x i16> @llvm.vector.reverse.nxv4i16(<vscale x 4 x i16>) 2108declare <vscale x 8 x i16> @llvm.vector.reverse.nxv8i16(<vscale x 8 x i16>) 2109declare <vscale x 16 x i16> @llvm.vector.reverse.nxv16i16(<vscale x 16 x i16>) 2110declare <vscale x 32 x i16> @llvm.vector.reverse.nxv32i16(<vscale x 32 x i16>) 2111declare <vscale x 1 x i32> @llvm.vector.reverse.nxv1i32(<vscale x 1 x i32>) 2112declare <vscale x 2 x i32> @llvm.vector.reverse.nxv2i32(<vscale x 2 x i32>) 2113declare <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32>) 2114declare <vscale x 8 x i32> @llvm.vector.reverse.nxv8i32(<vscale x 8 x i32>) 2115declare <vscale x 16 x i32> @llvm.vector.reverse.nxv16i32(<vscale x 16 x i32>) 2116declare <vscale x 1 x i64> @llvm.vector.reverse.nxv1i64(<vscale x 1 x i64>) 2117declare <vscale x 2 x i64> @llvm.vector.reverse.nxv2i64(<vscale x 2 x i64>) 2118declare <vscale x 4 x i64> @llvm.vector.reverse.nxv4i64(<vscale x 4 x i64>) 2119declare <vscale x 8 x i64> @llvm.vector.reverse.nxv8i64(<vscale x 8 x i64>) 2120declare <vscale x 1 x half> @llvm.vector.reverse.nxv1f16(<vscale x 1 x half>) 2121declare <vscale x 2 x half> @llvm.vector.reverse.nxv2f16(<vscale x 2 x half>) 2122declare <vscale x 4 x half> @llvm.vector.reverse.nxv4f16(<vscale x 4 x half>) 2123declare <vscale x 8 x half> @llvm.vector.reverse.nxv8f16(<vscale x 8 x half>) 2124declare <vscale x 16 x half> @llvm.vector.reverse.nxv16f16(<vscale x 16 x half>) 2125declare <vscale x 32 x half> @llvm.vector.reverse.nxv32f16(<vscale x 32 x half>) 2126declare <vscale x 1 x float> @llvm.vector.reverse.nxv1f32(<vscale x 1 x float>) 2127declare <vscale x 2 x float> @llvm.vector.reverse.nxv2f32(<vscale x 2 x float>) 2128declare <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float>) 2129declare <vscale x 8 x float> @llvm.vector.reverse.nxv8f32(<vscale x 8 x float>) 2130declare <vscale x 16 x float> @llvm.vector.reverse.nxv16f32(<vscale x 16 x float>) 2131declare <vscale x 1 x double> @llvm.vector.reverse.nxv1f64(<vscale x 1 x double>) 2132declare <vscale x 2 x double> @llvm.vector.reverse.nxv2f64(<vscale x 2 x double>) 2133declare <vscale x 4 x double> @llvm.vector.reverse.nxv4f64(<vscale x 4 x double>) 2134declare <vscale x 8 x double> @llvm.vector.reverse.nxv8f64(<vscale x 8 x double>) 2135declare <vscale x 3 x i64> @llvm.vector.reverse.nxv3i64(<vscale x 3 x i64>) 2136declare <vscale x 6 x i64> @llvm.vector.reverse.nxv6i64(<vscale x 6 x i64>) 2137declare <vscale x 12 x i64> @llvm.vector.reverse.nxv12i64(<vscale x 12 x i64>) 2138