xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir (revision d9f2b9391887af95acdd91dfea2e72eb3a9d8d05)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \
3# RUN:     -start-after finalize-isel -stop-after prologepilog -o - %s | FileCheck %s
4
5--- |
6  define void @mask_reg_alloc() {
7    ret void
8  }
9...
10---
11name: mask_reg_alloc
12tracksRegLiveness: true
13body:             |
14  bb.0 (%ir-block.0):
15    liveins: $v0, $v1, $v2, $v3
16    ; CHECK-LABEL: name: mask_reg_alloc
17    ; CHECK: liveins: $v0, $v1, $v2, $v3
18    ; CHECK-NEXT: {{  $}}
19    ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 192 /* e8, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
20    ; CHECK-NEXT: renamable $v8 = PseudoVMERGE_VIM_M1 undef renamable $v8, killed renamable $v2, 1, killed renamable $v0, 1, 3 /* e8 */, implicit $vl, implicit $vtype
21    ; CHECK-NEXT: renamable $v0 = COPY killed renamable $v1
22    ; CHECK-NEXT: renamable $v9 = PseudoVMERGE_VIM_M1 undef renamable $v9, killed renamable $v3, 1, killed renamable $v0, 1, 3 /* e8 */, implicit $vl, implicit $vtype
23    ; CHECK-NEXT: renamable $v0 = PseudoVADD_VV_M1 undef renamable $v0, killed renamable $v8, killed renamable $v9, 1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
24    ; CHECK-NEXT: PseudoRET implicit $v0
25    %0:vr = COPY $v0
26    %1:vr = COPY $v1
27    %2:vr = COPY $v2
28    %3:vr = COPY $v3
29    %4:vmv0 = COPY %0
30    %5:vrnov0 = PseudoVMERGE_VIM_M1 undef $noreg, killed %2, 1, %4, 1, 3
31    %6:vmv0 = COPY %1
32    %7:vrnov0 = PseudoVMERGE_VIM_M1 undef $noreg, killed %3, 1, %6, 1, 3
33    %8:vr = PseudoVADD_VV_M1 undef $noreg, killed %5, killed %7, 1, 3, 0
34    $v0 = COPY %8
35    PseudoRET implicit $v0
36...
37