xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs.ll (revision 99fb40d488c9d53dc1dfa0a1791f690523d7e50a) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
3; RUN:   -verify-machineinstrs  | FileCheck %s
4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
5; RUN:   -verify-machineinstrs  | FileCheck %s
6
7define <vscale x 1 x i8> @sext_nxv1i1_nxv1i8(<vscale x 1 x i1> %v) {
8; CHECK-LABEL: sext_nxv1i1_nxv1i8:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
11; CHECK-NEXT:    vmv.v.i v8, 0
12; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
13; CHECK-NEXT:    ret
14  %r = sext <vscale x 1 x i1> %v to <vscale x 1 x i8>
15  ret <vscale x 1 x i8> %r
16}
17
18define <vscale x 1 x i8> @zext_nxv1i1_nxv1i8(<vscale x 1 x i1> %v) {
19; CHECK-LABEL: zext_nxv1i1_nxv1i8:
20; CHECK:       # %bb.0:
21; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
22; CHECK-NEXT:    vmv.v.i v8, 0
23; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
24; CHECK-NEXT:    ret
25  %r = zext <vscale x 1 x i1> %v to <vscale x 1 x i8>
26  ret <vscale x 1 x i8> %r
27}
28
29define <vscale x 1 x i1> @trunc_nxv1i8_nxv1i1(<vscale x 1 x i8> %v) {
30; CHECK-LABEL: trunc_nxv1i8_nxv1i1:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
33; CHECK-NEXT:    vand.vi v8, v8, 1
34; CHECK-NEXT:    vmsne.vi v0, v8, 0
35; CHECK-NEXT:    ret
36  %r = trunc <vscale x 1 x i8> %v to <vscale x 1 x i1>
37  ret <vscale x 1 x i1> %r
38}
39
40define <vscale x 2 x i8> @sext_nxv2i1_nxv2i8(<vscale x 2 x i1> %v) {
41; CHECK-LABEL: sext_nxv2i1_nxv2i8:
42; CHECK:       # %bb.0:
43; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
44; CHECK-NEXT:    vmv.v.i v8, 0
45; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
46; CHECK-NEXT:    ret
47  %r = sext <vscale x 2 x i1> %v to <vscale x 2 x i8>
48  ret <vscale x 2 x i8> %r
49}
50
51define <vscale x 2 x i8> @zext_nxv2i1_nxv2i8(<vscale x 2 x i1> %v) {
52; CHECK-LABEL: zext_nxv2i1_nxv2i8:
53; CHECK:       # %bb.0:
54; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
55; CHECK-NEXT:    vmv.v.i v8, 0
56; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
57; CHECK-NEXT:    ret
58  %r = zext <vscale x 2 x i1> %v to <vscale x 2 x i8>
59  ret <vscale x 2 x i8> %r
60}
61
62define <vscale x 2 x i1> @trunc_nxv2i8_nxv2i1(<vscale x 2 x i8> %v) {
63; CHECK-LABEL: trunc_nxv2i8_nxv2i1:
64; CHECK:       # %bb.0:
65; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
66; CHECK-NEXT:    vand.vi v8, v8, 1
67; CHECK-NEXT:    vmsne.vi v0, v8, 0
68; CHECK-NEXT:    ret
69  %r = trunc <vscale x 2 x i8> %v to <vscale x 2 x i1>
70  ret <vscale x 2 x i1> %r
71}
72
73define <vscale x 4 x i8> @sext_nxv4i1_nxv4i8(<vscale x 4 x i1> %v) {
74; CHECK-LABEL: sext_nxv4i1_nxv4i8:
75; CHECK:       # %bb.0:
76; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
77; CHECK-NEXT:    vmv.v.i v8, 0
78; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
79; CHECK-NEXT:    ret
80  %r = sext <vscale x 4 x i1> %v to <vscale x 4 x i8>
81  ret <vscale x 4 x i8> %r
82}
83
84define <vscale x 4 x i8> @zext_nxv4i1_nxv4i8(<vscale x 4 x i1> %v) {
85; CHECK-LABEL: zext_nxv4i1_nxv4i8:
86; CHECK:       # %bb.0:
87; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
88; CHECK-NEXT:    vmv.v.i v8, 0
89; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
90; CHECK-NEXT:    ret
91  %r = zext <vscale x 4 x i1> %v to <vscale x 4 x i8>
92  ret <vscale x 4 x i8> %r
93}
94
95define <vscale x 4 x i1> @trunc_nxv4i8_nxv4i1(<vscale x 4 x i8> %v) {
96; CHECK-LABEL: trunc_nxv4i8_nxv4i1:
97; CHECK:       # %bb.0:
98; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
99; CHECK-NEXT:    vand.vi v8, v8, 1
100; CHECK-NEXT:    vmsne.vi v0, v8, 0
101; CHECK-NEXT:    ret
102  %r = trunc <vscale x 4 x i8> %v to <vscale x 4 x i1>
103  ret <vscale x 4 x i1> %r
104}
105
106define <vscale x 8 x i8> @sext_nxv8i1_nxv8i8(<vscale x 8 x i1> %v) {
107; CHECK-LABEL: sext_nxv8i1_nxv8i8:
108; CHECK:       # %bb.0:
109; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
110; CHECK-NEXT:    vmv.v.i v8, 0
111; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
112; CHECK-NEXT:    ret
113  %r = sext <vscale x 8 x i1> %v to <vscale x 8 x i8>
114  ret <vscale x 8 x i8> %r
115}
116
117define <vscale x 8 x i8> @zext_nxv8i1_nxv8i8(<vscale x 8 x i1> %v) {
118; CHECK-LABEL: zext_nxv8i1_nxv8i8:
119; CHECK:       # %bb.0:
120; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
121; CHECK-NEXT:    vmv.v.i v8, 0
122; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
123; CHECK-NEXT:    ret
124  %r = zext <vscale x 8 x i1> %v to <vscale x 8 x i8>
125  ret <vscale x 8 x i8> %r
126}
127
128define <vscale x 8 x i1> @trunc_nxv8i8_nxv8i1(<vscale x 8 x i8> %v) {
129; CHECK-LABEL: trunc_nxv8i8_nxv8i1:
130; CHECK:       # %bb.0:
131; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
132; CHECK-NEXT:    vand.vi v8, v8, 1
133; CHECK-NEXT:    vmsne.vi v0, v8, 0
134; CHECK-NEXT:    ret
135  %r = trunc <vscale x 8 x i8> %v to <vscale x 8 x i1>
136  ret <vscale x 8 x i1> %r
137}
138
139define <vscale x 16 x i8> @sext_nxv16i1_nxv16i8(<vscale x 16 x i1> %v) {
140; CHECK-LABEL: sext_nxv16i1_nxv16i8:
141; CHECK:       # %bb.0:
142; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
143; CHECK-NEXT:    vmv.v.i v8, 0
144; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
145; CHECK-NEXT:    ret
146  %r = sext <vscale x 16 x i1> %v to <vscale x 16 x i8>
147  ret <vscale x 16 x i8> %r
148}
149
150define <vscale x 16 x i8> @zext_nxv16i1_nxv16i8(<vscale x 16 x i1> %v) {
151; CHECK-LABEL: zext_nxv16i1_nxv16i8:
152; CHECK:       # %bb.0:
153; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
154; CHECK-NEXT:    vmv.v.i v8, 0
155; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
156; CHECK-NEXT:    ret
157  %r = zext <vscale x 16 x i1> %v to <vscale x 16 x i8>
158  ret <vscale x 16 x i8> %r
159}
160
161define <vscale x 16 x i1> @trunc_nxv16i8_nxv16i1(<vscale x 16 x i8> %v) {
162; CHECK-LABEL: trunc_nxv16i8_nxv16i1:
163; CHECK:       # %bb.0:
164; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
165; CHECK-NEXT:    vand.vi v8, v8, 1
166; CHECK-NEXT:    vmsne.vi v0, v8, 0
167; CHECK-NEXT:    ret
168  %r = trunc <vscale x 16 x i8> %v to <vscale x 16 x i1>
169  ret <vscale x 16 x i1> %r
170}
171
172define <vscale x 32 x i8> @sext_nxv32i1_nxv32i8(<vscale x 32 x i1> %v) {
173; CHECK-LABEL: sext_nxv32i1_nxv32i8:
174; CHECK:       # %bb.0:
175; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
176; CHECK-NEXT:    vmv.v.i v8, 0
177; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
178; CHECK-NEXT:    ret
179  %r = sext <vscale x 32 x i1> %v to <vscale x 32 x i8>
180  ret <vscale x 32 x i8> %r
181}
182
183define <vscale x 32 x i8> @zext_nxv32i1_nxv32i8(<vscale x 32 x i1> %v) {
184; CHECK-LABEL: zext_nxv32i1_nxv32i8:
185; CHECK:       # %bb.0:
186; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
187; CHECK-NEXT:    vmv.v.i v8, 0
188; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
189; CHECK-NEXT:    ret
190  %r = zext <vscale x 32 x i1> %v to <vscale x 32 x i8>
191  ret <vscale x 32 x i8> %r
192}
193
194define <vscale x 32 x i1> @trunc_nxv32i8_nxv32i1(<vscale x 32 x i8> %v) {
195; CHECK-LABEL: trunc_nxv32i8_nxv32i1:
196; CHECK:       # %bb.0:
197; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
198; CHECK-NEXT:    vand.vi v8, v8, 1
199; CHECK-NEXT:    vmsne.vi v0, v8, 0
200; CHECK-NEXT:    ret
201  %r = trunc <vscale x 32 x i8> %v to <vscale x 32 x i1>
202  ret <vscale x 32 x i1> %r
203}
204
205define <vscale x 64 x i8> @sext_nxv64i1_nxv64i8(<vscale x 64 x i1> %v) {
206; CHECK-LABEL: sext_nxv64i1_nxv64i8:
207; CHECK:       # %bb.0:
208; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
209; CHECK-NEXT:    vmv.v.i v8, 0
210; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
211; CHECK-NEXT:    ret
212  %r = sext <vscale x 64 x i1> %v to <vscale x 64 x i8>
213  ret <vscale x 64 x i8> %r
214}
215
216define <vscale x 64 x i8> @zext_nxv64i1_nxv64i8(<vscale x 64 x i1> %v) {
217; CHECK-LABEL: zext_nxv64i1_nxv64i8:
218; CHECK:       # %bb.0:
219; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
220; CHECK-NEXT:    vmv.v.i v8, 0
221; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
222; CHECK-NEXT:    ret
223  %r = zext <vscale x 64 x i1> %v to <vscale x 64 x i8>
224  ret <vscale x 64 x i8> %r
225}
226
227define <vscale x 64 x i1> @trunc_nxv64i8_nxv64i1(<vscale x 64 x i8> %v) {
228; CHECK-LABEL: trunc_nxv64i8_nxv64i1:
229; CHECK:       # %bb.0:
230; CHECK-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
231; CHECK-NEXT:    vand.vi v8, v8, 1
232; CHECK-NEXT:    vmsne.vi v0, v8, 0
233; CHECK-NEXT:    ret
234  %r = trunc <vscale x 64 x i8> %v to <vscale x 64 x i1>
235  ret <vscale x 64 x i1> %r
236}
237
238define <vscale x 1 x i16> @sext_nxv1i1_nxv1i16(<vscale x 1 x i1> %v) {
239; CHECK-LABEL: sext_nxv1i1_nxv1i16:
240; CHECK:       # %bb.0:
241; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
242; CHECK-NEXT:    vmv.v.i v8, 0
243; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
244; CHECK-NEXT:    ret
245  %r = sext <vscale x 1 x i1> %v to <vscale x 1 x i16>
246  ret <vscale x 1 x i16> %r
247}
248
249define <vscale x 1 x i16> @zext_nxv1i1_nxv1i16(<vscale x 1 x i1> %v) {
250; CHECK-LABEL: zext_nxv1i1_nxv1i16:
251; CHECK:       # %bb.0:
252; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
253; CHECK-NEXT:    vmv.v.i v8, 0
254; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
255; CHECK-NEXT:    ret
256  %r = zext <vscale x 1 x i1> %v to <vscale x 1 x i16>
257  ret <vscale x 1 x i16> %r
258}
259
260define <vscale x 1 x i1> @trunc_nxv1i16_nxv1i1(<vscale x 1 x i16> %v) {
261; CHECK-LABEL: trunc_nxv1i16_nxv1i1:
262; CHECK:       # %bb.0:
263; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
264; CHECK-NEXT:    vand.vi v8, v8, 1
265; CHECK-NEXT:    vmsne.vi v0, v8, 0
266; CHECK-NEXT:    ret
267  %r = trunc <vscale x 1 x i16> %v to <vscale x 1 x i1>
268  ret <vscale x 1 x i1> %r
269}
270
271define <vscale x 2 x i16> @sext_nxv2i1_nxv2i16(<vscale x 2 x i1> %v) {
272; CHECK-LABEL: sext_nxv2i1_nxv2i16:
273; CHECK:       # %bb.0:
274; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
275; CHECK-NEXT:    vmv.v.i v8, 0
276; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
277; CHECK-NEXT:    ret
278  %r = sext <vscale x 2 x i1> %v to <vscale x 2 x i16>
279  ret <vscale x 2 x i16> %r
280}
281
282define <vscale x 2 x i16> @zext_nxv2i1_nxv2i16(<vscale x 2 x i1> %v) {
283; CHECK-LABEL: zext_nxv2i1_nxv2i16:
284; CHECK:       # %bb.0:
285; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
286; CHECK-NEXT:    vmv.v.i v8, 0
287; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
288; CHECK-NEXT:    ret
289  %r = zext <vscale x 2 x i1> %v to <vscale x 2 x i16>
290  ret <vscale x 2 x i16> %r
291}
292
293define <vscale x 2 x i1> @trunc_nxv2i16_nxv2i1(<vscale x 2 x i16> %v) {
294; CHECK-LABEL: trunc_nxv2i16_nxv2i1:
295; CHECK:       # %bb.0:
296; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
297; CHECK-NEXT:    vand.vi v8, v8, 1
298; CHECK-NEXT:    vmsne.vi v0, v8, 0
299; CHECK-NEXT:    ret
300  %r = trunc <vscale x 2 x i16> %v to <vscale x 2 x i1>
301  ret <vscale x 2 x i1> %r
302}
303
304define <vscale x 4 x i16> @sext_nxv4i1_nxv4i16(<vscale x 4 x i1> %v) {
305; CHECK-LABEL: sext_nxv4i1_nxv4i16:
306; CHECK:       # %bb.0:
307; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
308; CHECK-NEXT:    vmv.v.i v8, 0
309; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
310; CHECK-NEXT:    ret
311  %r = sext <vscale x 4 x i1> %v to <vscale x 4 x i16>
312  ret <vscale x 4 x i16> %r
313}
314
315define <vscale x 4 x i16> @zext_nxv4i1_nxv4i16(<vscale x 4 x i1> %v) {
316; CHECK-LABEL: zext_nxv4i1_nxv4i16:
317; CHECK:       # %bb.0:
318; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
319; CHECK-NEXT:    vmv.v.i v8, 0
320; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
321; CHECK-NEXT:    ret
322  %r = zext <vscale x 4 x i1> %v to <vscale x 4 x i16>
323  ret <vscale x 4 x i16> %r
324}
325
326define <vscale x 4 x i1> @trunc_nxv4i16_nxv4i1(<vscale x 4 x i16> %v) {
327; CHECK-LABEL: trunc_nxv4i16_nxv4i1:
328; CHECK:       # %bb.0:
329; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
330; CHECK-NEXT:    vand.vi v8, v8, 1
331; CHECK-NEXT:    vmsne.vi v0, v8, 0
332; CHECK-NEXT:    ret
333  %r = trunc <vscale x 4 x i16> %v to <vscale x 4 x i1>
334  ret <vscale x 4 x i1> %r
335}
336
337define <vscale x 8 x i16> @sext_nxv8i1_nxv8i16(<vscale x 8 x i1> %v) {
338; CHECK-LABEL: sext_nxv8i1_nxv8i16:
339; CHECK:       # %bb.0:
340; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
341; CHECK-NEXT:    vmv.v.i v8, 0
342; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
343; CHECK-NEXT:    ret
344  %r = sext <vscale x 8 x i1> %v to <vscale x 8 x i16>
345  ret <vscale x 8 x i16> %r
346}
347
348define <vscale x 8 x i16> @zext_nxv8i1_nxv8i16(<vscale x 8 x i1> %v) {
349; CHECK-LABEL: zext_nxv8i1_nxv8i16:
350; CHECK:       # %bb.0:
351; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
352; CHECK-NEXT:    vmv.v.i v8, 0
353; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
354; CHECK-NEXT:    ret
355  %r = zext <vscale x 8 x i1> %v to <vscale x 8 x i16>
356  ret <vscale x 8 x i16> %r
357}
358
359define <vscale x 8 x i1> @trunc_nxv8i16_nxv8i1(<vscale x 8 x i16> %v) {
360; CHECK-LABEL: trunc_nxv8i16_nxv8i1:
361; CHECK:       # %bb.0:
362; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
363; CHECK-NEXT:    vand.vi v8, v8, 1
364; CHECK-NEXT:    vmsne.vi v0, v8, 0
365; CHECK-NEXT:    ret
366  %r = trunc <vscale x 8 x i16> %v to <vscale x 8 x i1>
367  ret <vscale x 8 x i1> %r
368}
369
370define <vscale x 16 x i16> @sext_nxv16i1_nxv16i16(<vscale x 16 x i1> %v) {
371; CHECK-LABEL: sext_nxv16i1_nxv16i16:
372; CHECK:       # %bb.0:
373; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
374; CHECK-NEXT:    vmv.v.i v8, 0
375; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
376; CHECK-NEXT:    ret
377  %r = sext <vscale x 16 x i1> %v to <vscale x 16 x i16>
378  ret <vscale x 16 x i16> %r
379}
380
381define <vscale x 16 x i16> @zext_nxv16i1_nxv16i16(<vscale x 16 x i1> %v) {
382; CHECK-LABEL: zext_nxv16i1_nxv16i16:
383; CHECK:       # %bb.0:
384; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
385; CHECK-NEXT:    vmv.v.i v8, 0
386; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
387; CHECK-NEXT:    ret
388  %r = zext <vscale x 16 x i1> %v to <vscale x 16 x i16>
389  ret <vscale x 16 x i16> %r
390}
391
392define <vscale x 16 x i1> @trunc_nxv16i16_nxv16i1(<vscale x 16 x i16> %v) {
393; CHECK-LABEL: trunc_nxv16i16_nxv16i1:
394; CHECK:       # %bb.0:
395; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
396; CHECK-NEXT:    vand.vi v8, v8, 1
397; CHECK-NEXT:    vmsne.vi v0, v8, 0
398; CHECK-NEXT:    ret
399  %r = trunc <vscale x 16 x i16> %v to <vscale x 16 x i1>
400  ret <vscale x 16 x i1> %r
401}
402
403define <vscale x 32 x i16> @sext_nxv32i1_nxv32i16(<vscale x 32 x i1> %v) {
404; CHECK-LABEL: sext_nxv32i1_nxv32i16:
405; CHECK:       # %bb.0:
406; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
407; CHECK-NEXT:    vmv.v.i v8, 0
408; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
409; CHECK-NEXT:    ret
410  %r = sext <vscale x 32 x i1> %v to <vscale x 32 x i16>
411  ret <vscale x 32 x i16> %r
412}
413
414define <vscale x 32 x i16> @zext_nxv32i1_nxv32i16(<vscale x 32 x i1> %v) {
415; CHECK-LABEL: zext_nxv32i1_nxv32i16:
416; CHECK:       # %bb.0:
417; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
418; CHECK-NEXT:    vmv.v.i v8, 0
419; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
420; CHECK-NEXT:    ret
421  %r = zext <vscale x 32 x i1> %v to <vscale x 32 x i16>
422  ret <vscale x 32 x i16> %r
423}
424
425define <vscale x 32 x i1> @trunc_nxv32i16_nxv32i1(<vscale x 32 x i16> %v) {
426; CHECK-LABEL: trunc_nxv32i16_nxv32i1:
427; CHECK:       # %bb.0:
428; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
429; CHECK-NEXT:    vand.vi v8, v8, 1
430; CHECK-NEXT:    vmsne.vi v0, v8, 0
431; CHECK-NEXT:    ret
432  %r = trunc <vscale x 32 x i16> %v to <vscale x 32 x i1>
433  ret <vscale x 32 x i1> %r
434}
435
436define <vscale x 1 x i32> @sext_nxv1i1_nxv1i32(<vscale x 1 x i1> %v) {
437; CHECK-LABEL: sext_nxv1i1_nxv1i32:
438; CHECK:       # %bb.0:
439; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
440; CHECK-NEXT:    vmv.v.i v8, 0
441; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
442; CHECK-NEXT:    ret
443  %r = sext <vscale x 1 x i1> %v to <vscale x 1 x i32>
444  ret <vscale x 1 x i32> %r
445}
446
447define <vscale x 1 x i32> @zext_nxv1i1_nxv1i32(<vscale x 1 x i1> %v) {
448; CHECK-LABEL: zext_nxv1i1_nxv1i32:
449; CHECK:       # %bb.0:
450; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
451; CHECK-NEXT:    vmv.v.i v8, 0
452; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
453; CHECK-NEXT:    ret
454  %r = zext <vscale x 1 x i1> %v to <vscale x 1 x i32>
455  ret <vscale x 1 x i32> %r
456}
457
458define <vscale x 1 x i1> @trunc_nxv1i32_nxv1i1(<vscale x 1 x i32> %v) {
459; CHECK-LABEL: trunc_nxv1i32_nxv1i1:
460; CHECK:       # %bb.0:
461; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
462; CHECK-NEXT:    vand.vi v8, v8, 1
463; CHECK-NEXT:    vmsne.vi v0, v8, 0
464; CHECK-NEXT:    ret
465  %r = trunc <vscale x 1 x i32> %v to <vscale x 1 x i1>
466  ret <vscale x 1 x i1> %r
467}
468
469define <vscale x 2 x i32> @sext_nxv2i1_nxv2i32(<vscale x 2 x i1> %v) {
470; CHECK-LABEL: sext_nxv2i1_nxv2i32:
471; CHECK:       # %bb.0:
472; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
473; CHECK-NEXT:    vmv.v.i v8, 0
474; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
475; CHECK-NEXT:    ret
476  %r = sext <vscale x 2 x i1> %v to <vscale x 2 x i32>
477  ret <vscale x 2 x i32> %r
478}
479
480define <vscale x 2 x i32> @zext_nxv2i1_nxv2i32(<vscale x 2 x i1> %v) {
481; CHECK-LABEL: zext_nxv2i1_nxv2i32:
482; CHECK:       # %bb.0:
483; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
484; CHECK-NEXT:    vmv.v.i v8, 0
485; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
486; CHECK-NEXT:    ret
487  %r = zext <vscale x 2 x i1> %v to <vscale x 2 x i32>
488  ret <vscale x 2 x i32> %r
489}
490
491define <vscale x 2 x i1> @trunc_nxv2i32_nxv2i1(<vscale x 2 x i32> %v) {
492; CHECK-LABEL: trunc_nxv2i32_nxv2i1:
493; CHECK:       # %bb.0:
494; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
495; CHECK-NEXT:    vand.vi v8, v8, 1
496; CHECK-NEXT:    vmsne.vi v0, v8, 0
497; CHECK-NEXT:    ret
498  %r = trunc <vscale x 2 x i32> %v to <vscale x 2 x i1>
499  ret <vscale x 2 x i1> %r
500}
501
502define <vscale x 4 x i32> @sext_nxv4i1_nxv4i32(<vscale x 4 x i1> %v) {
503; CHECK-LABEL: sext_nxv4i1_nxv4i32:
504; CHECK:       # %bb.0:
505; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
506; CHECK-NEXT:    vmv.v.i v8, 0
507; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
508; CHECK-NEXT:    ret
509  %r = sext <vscale x 4 x i1> %v to <vscale x 4 x i32>
510  ret <vscale x 4 x i32> %r
511}
512
513define <vscale x 4 x i32> @zext_nxv4i1_nxv4i32(<vscale x 4 x i1> %v) {
514; CHECK-LABEL: zext_nxv4i1_nxv4i32:
515; CHECK:       # %bb.0:
516; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
517; CHECK-NEXT:    vmv.v.i v8, 0
518; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
519; CHECK-NEXT:    ret
520  %r = zext <vscale x 4 x i1> %v to <vscale x 4 x i32>
521  ret <vscale x 4 x i32> %r
522}
523
524define <vscale x 4 x i1> @trunc_nxv4i32_nxv4i1(<vscale x 4 x i32> %v) {
525; CHECK-LABEL: trunc_nxv4i32_nxv4i1:
526; CHECK:       # %bb.0:
527; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
528; CHECK-NEXT:    vand.vi v8, v8, 1
529; CHECK-NEXT:    vmsne.vi v0, v8, 0
530; CHECK-NEXT:    ret
531  %r = trunc <vscale x 4 x i32> %v to <vscale x 4 x i1>
532  ret <vscale x 4 x i1> %r
533}
534
535define <vscale x 8 x i32> @sext_nxv8i1_nxv8i32(<vscale x 8 x i1> %v) {
536; CHECK-LABEL: sext_nxv8i1_nxv8i32:
537; CHECK:       # %bb.0:
538; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
539; CHECK-NEXT:    vmv.v.i v8, 0
540; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
541; CHECK-NEXT:    ret
542  %r = sext <vscale x 8 x i1> %v to <vscale x 8 x i32>
543  ret <vscale x 8 x i32> %r
544}
545
546define <vscale x 8 x i32> @zext_nxv8i1_nxv8i32(<vscale x 8 x i1> %v) {
547; CHECK-LABEL: zext_nxv8i1_nxv8i32:
548; CHECK:       # %bb.0:
549; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
550; CHECK-NEXT:    vmv.v.i v8, 0
551; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
552; CHECK-NEXT:    ret
553  %r = zext <vscale x 8 x i1> %v to <vscale x 8 x i32>
554  ret <vscale x 8 x i32> %r
555}
556
557define <vscale x 8 x i1> @trunc_nxv8i32_nxv8i1(<vscale x 8 x i32> %v) {
558; CHECK-LABEL: trunc_nxv8i32_nxv8i1:
559; CHECK:       # %bb.0:
560; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
561; CHECK-NEXT:    vand.vi v8, v8, 1
562; CHECK-NEXT:    vmsne.vi v0, v8, 0
563; CHECK-NEXT:    ret
564  %r = trunc <vscale x 8 x i32> %v to <vscale x 8 x i1>
565  ret <vscale x 8 x i1> %r
566}
567
568define <vscale x 16 x i32> @sext_nxv16i1_nxv16i32(<vscale x 16 x i1> %v) {
569; CHECK-LABEL: sext_nxv16i1_nxv16i32:
570; CHECK:       # %bb.0:
571; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
572; CHECK-NEXT:    vmv.v.i v8, 0
573; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
574; CHECK-NEXT:    ret
575  %r = sext <vscale x 16 x i1> %v to <vscale x 16 x i32>
576  ret <vscale x 16 x i32> %r
577}
578
579define <vscale x 16 x i32> @zext_nxv16i1_nxv16i32(<vscale x 16 x i1> %v) {
580; CHECK-LABEL: zext_nxv16i1_nxv16i32:
581; CHECK:       # %bb.0:
582; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
583; CHECK-NEXT:    vmv.v.i v8, 0
584; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
585; CHECK-NEXT:    ret
586  %r = zext <vscale x 16 x i1> %v to <vscale x 16 x i32>
587  ret <vscale x 16 x i32> %r
588}
589
590define <vscale x 16 x i1> @trunc_nxv16i32_nxv16i1(<vscale x 16 x i32> %v) {
591; CHECK-LABEL: trunc_nxv16i32_nxv16i1:
592; CHECK:       # %bb.0:
593; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
594; CHECK-NEXT:    vand.vi v8, v8, 1
595; CHECK-NEXT:    vmsne.vi v0, v8, 0
596; CHECK-NEXT:    ret
597  %r = trunc <vscale x 16 x i32> %v to <vscale x 16 x i1>
598  ret <vscale x 16 x i1> %r
599}
600
601define <vscale x 1 x i64> @sext_nxv1i1_nxv1i64(<vscale x 1 x i1> %v) {
602; CHECK-LABEL: sext_nxv1i1_nxv1i64:
603; CHECK:       # %bb.0:
604; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
605; CHECK-NEXT:    vmv.v.i v8, 0
606; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
607; CHECK-NEXT:    ret
608  %r = sext <vscale x 1 x i1> %v to <vscale x 1 x i64>
609  ret <vscale x 1 x i64> %r
610}
611
612define <vscale x 1 x i64> @zext_nxv1i1_nxv1i64(<vscale x 1 x i1> %v) {
613; CHECK-LABEL: zext_nxv1i1_nxv1i64:
614; CHECK:       # %bb.0:
615; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
616; CHECK-NEXT:    vmv.v.i v8, 0
617; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
618; CHECK-NEXT:    ret
619  %r = zext <vscale x 1 x i1> %v to <vscale x 1 x i64>
620  ret <vscale x 1 x i64> %r
621}
622
623define <vscale x 1 x i1> @trunc_nxv1i64_nxv1i1(<vscale x 1 x i64> %v) {
624; CHECK-LABEL: trunc_nxv1i64_nxv1i1:
625; CHECK:       # %bb.0:
626; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
627; CHECK-NEXT:    vand.vi v8, v8, 1
628; CHECK-NEXT:    vmsne.vi v0, v8, 0
629; CHECK-NEXT:    ret
630  %r = trunc <vscale x 1 x i64> %v to <vscale x 1 x i1>
631  ret <vscale x 1 x i1> %r
632}
633
634define <vscale x 2 x i64> @sext_nxv2i1_nxv2i64(<vscale x 2 x i1> %v) {
635; CHECK-LABEL: sext_nxv2i1_nxv2i64:
636; CHECK:       # %bb.0:
637; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
638; CHECK-NEXT:    vmv.v.i v8, 0
639; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
640; CHECK-NEXT:    ret
641  %r = sext <vscale x 2 x i1> %v to <vscale x 2 x i64>
642  ret <vscale x 2 x i64> %r
643}
644
645define <vscale x 2 x i64> @zext_nxv2i1_nxv2i64(<vscale x 2 x i1> %v) {
646; CHECK-LABEL: zext_nxv2i1_nxv2i64:
647; CHECK:       # %bb.0:
648; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
649; CHECK-NEXT:    vmv.v.i v8, 0
650; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
651; CHECK-NEXT:    ret
652  %r = zext <vscale x 2 x i1> %v to <vscale x 2 x i64>
653  ret <vscale x 2 x i64> %r
654}
655
656define <vscale x 2 x i1> @trunc_nxv2i64_nxv2i1(<vscale x 2 x i64> %v) {
657; CHECK-LABEL: trunc_nxv2i64_nxv2i1:
658; CHECK:       # %bb.0:
659; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
660; CHECK-NEXT:    vand.vi v8, v8, 1
661; CHECK-NEXT:    vmsne.vi v0, v8, 0
662; CHECK-NEXT:    ret
663  %r = trunc <vscale x 2 x i64> %v to <vscale x 2 x i1>
664  ret <vscale x 2 x i1> %r
665}
666
667define <vscale x 4 x i64> @sext_nxv4i1_nxv4i64(<vscale x 4 x i1> %v) {
668; CHECK-LABEL: sext_nxv4i1_nxv4i64:
669; CHECK:       # %bb.0:
670; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
671; CHECK-NEXT:    vmv.v.i v8, 0
672; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
673; CHECK-NEXT:    ret
674  %r = sext <vscale x 4 x i1> %v to <vscale x 4 x i64>
675  ret <vscale x 4 x i64> %r
676}
677
678define <vscale x 4 x i64> @zext_nxv4i1_nxv4i64(<vscale x 4 x i1> %v) {
679; CHECK-LABEL: zext_nxv4i1_nxv4i64:
680; CHECK:       # %bb.0:
681; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
682; CHECK-NEXT:    vmv.v.i v8, 0
683; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
684; CHECK-NEXT:    ret
685  %r = zext <vscale x 4 x i1> %v to <vscale x 4 x i64>
686  ret <vscale x 4 x i64> %r
687}
688
689define <vscale x 4 x i1> @trunc_nxv4i64_nxv4i1(<vscale x 4 x i64> %v) {
690; CHECK-LABEL: trunc_nxv4i64_nxv4i1:
691; CHECK:       # %bb.0:
692; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
693; CHECK-NEXT:    vand.vi v8, v8, 1
694; CHECK-NEXT:    vmsne.vi v0, v8, 0
695; CHECK-NEXT:    ret
696  %r = trunc <vscale x 4 x i64> %v to <vscale x 4 x i1>
697  ret <vscale x 4 x i1> %r
698}
699
700define <vscale x 8 x i64> @sext_nxv8i1_nxv8i64(<vscale x 8 x i1> %v) {
701; CHECK-LABEL: sext_nxv8i1_nxv8i64:
702; CHECK:       # %bb.0:
703; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
704; CHECK-NEXT:    vmv.v.i v8, 0
705; CHECK-NEXT:    vmerge.vim v8, v8, -1, v0
706; CHECK-NEXT:    ret
707  %r = sext <vscale x 8 x i1> %v to <vscale x 8 x i64>
708  ret <vscale x 8 x i64> %r
709}
710
711define <vscale x 8 x i64> @zext_nxv8i1_nxv8i64(<vscale x 8 x i1> %v) {
712; CHECK-LABEL: zext_nxv8i1_nxv8i64:
713; CHECK:       # %bb.0:
714; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
715; CHECK-NEXT:    vmv.v.i v8, 0
716; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
717; CHECK-NEXT:    ret
718  %r = zext <vscale x 8 x i1> %v to <vscale x 8 x i64>
719  ret <vscale x 8 x i64> %r
720}
721
722define <vscale x 8 x i1> @trunc_nxv8i64_nxv8i1(<vscale x 8 x i64> %v) {
723; CHECK-LABEL: trunc_nxv8i64_nxv8i1:
724; CHECK:       # %bb.0:
725; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
726; CHECK-NEXT:    vand.vi v8, v8, 1
727; CHECK-NEXT:    vmsne.vi v0, v8, 0
728; CHECK-NEXT:    ret
729  %r = trunc <vscale x 8 x i64> %v to <vscale x 8 x i1>
730  ret <vscale x 8 x i1> %r
731}
732