xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+f,+d \
3; RUN:     -target-abi=ilp32d -verify-machineinstrs | FileCheck %s --check-prefix=RV32
4; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d \
5; RUN:     -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i32
6; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+f,+d \
7; RUN:     -target-abi=lp64d -verify-machineinstrs | FileCheck %s --check-prefix=RV64-i64
8
9define <vscale x 1 x iXLen> @lrint_nxv1f32(<vscale x 1 x float> %x, <vscale x 1 x i1> %m, i32 zeroext %evl) {
10; RV32-LABEL: lrint_nxv1f32:
11; RV32:       # %bb.0:
12; RV32-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
13; RV32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
14; RV32-NEXT:    ret
15;
16; RV64-i32-LABEL: lrint_nxv1f32:
17; RV64-i32:       # %bb.0:
18; RV64-i32-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
19; RV64-i32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
20; RV64-i32-NEXT:    ret
21;
22; RV64-i64-LABEL: lrint_nxv1f32:
23; RV64-i64:       # %bb.0:
24; RV64-i64-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
25; RV64-i64-NEXT:    vfwcvt.x.f.v v9, v8, v0.t
26; RV64-i64-NEXT:    vmv1r.v v8, v9
27; RV64-i64-NEXT:    ret
28  %a = call <vscale x 1 x iXLen> @llvm.vp.lrint.nxv1iXLen.nxv1f32(<vscale x 1 x float> %x, <vscale x 1 x i1> %m, i32 %evl)
29  ret <vscale x 1 x iXLen> %a
30}
31declare <vscale x 1 x iXLen> @llvm.vp.lrint.nxv1iXLen.nxv1f32(<vscale x 1 x float>, <vscale x 1 x i1>, i32)
32
33define <vscale x 2 x iXLen> @lrint_nxv2f32(<vscale x 2 x float> %x, <vscale x 2 x i1> %m, i32 zeroext %evl) {
34; RV32-LABEL: lrint_nxv2f32:
35; RV32:       # %bb.0:
36; RV32-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
37; RV32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
38; RV32-NEXT:    ret
39;
40; RV64-i32-LABEL: lrint_nxv2f32:
41; RV64-i32:       # %bb.0:
42; RV64-i32-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
43; RV64-i32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
44; RV64-i32-NEXT:    ret
45;
46; RV64-i64-LABEL: lrint_nxv2f32:
47; RV64-i64:       # %bb.0:
48; RV64-i64-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
49; RV64-i64-NEXT:    vfwcvt.x.f.v v10, v8, v0.t
50; RV64-i64-NEXT:    vmv2r.v v8, v10
51; RV64-i64-NEXT:    ret
52  %a = call <vscale x 2 x iXLen> @llvm.vp.lrint.nxv2iXLen.nxv2f32(<vscale x 2 x float> %x, <vscale x 2 x i1> %m, i32 %evl)
53  ret <vscale x 2 x iXLen> %a
54}
55declare <vscale x 2 x iXLen> @llvm.vp.lrint.nxv2iXLen.nxv2f32(<vscale x 2 x float>, <vscale x 2 x i1>, i32)
56
57define <vscale x 4 x iXLen> @lrint_nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x i1> %m, i32 zeroext %evl) {
58; RV32-LABEL: lrint_nxv4f32:
59; RV32:       # %bb.0:
60; RV32-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
61; RV32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
62; RV32-NEXT:    ret
63;
64; RV64-i32-LABEL: lrint_nxv4f32:
65; RV64-i32:       # %bb.0:
66; RV64-i32-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
67; RV64-i32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
68; RV64-i32-NEXT:    ret
69;
70; RV64-i64-LABEL: lrint_nxv4f32:
71; RV64-i64:       # %bb.0:
72; RV64-i64-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
73; RV64-i64-NEXT:    vfwcvt.x.f.v v12, v8, v0.t
74; RV64-i64-NEXT:    vmv4r.v v8, v12
75; RV64-i64-NEXT:    ret
76  %a = call <vscale x 4 x iXLen> @llvm.vp.lrint.nxv4iXLen.nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x i1> %m, i32 %evl)
77  ret <vscale x 4 x iXLen> %a
78}
79declare <vscale x 4 x iXLen> @llvm.vp.lrint.nxv4iXLen.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, i32)
80
81define <vscale x 8 x iXLen> @lrint_nxv8f32(<vscale x 8 x float> %x, <vscale x 8 x i1> %m, i32 zeroext %evl) {
82; RV32-LABEL: lrint_nxv8f32:
83; RV32:       # %bb.0:
84; RV32-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
85; RV32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
86; RV32-NEXT:    ret
87;
88; RV64-i32-LABEL: lrint_nxv8f32:
89; RV64-i32:       # %bb.0:
90; RV64-i32-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
91; RV64-i32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
92; RV64-i32-NEXT:    ret
93;
94; RV64-i64-LABEL: lrint_nxv8f32:
95; RV64-i64:       # %bb.0:
96; RV64-i64-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
97; RV64-i64-NEXT:    vfwcvt.x.f.v v16, v8, v0.t
98; RV64-i64-NEXT:    vmv8r.v v8, v16
99; RV64-i64-NEXT:    ret
100  %a = call <vscale x 8 x iXLen> @llvm.vp.lrint.nxv8iXLen.nxv8f32(<vscale x 8 x float> %x, <vscale x 8 x i1> %m, i32 %evl)
101  ret <vscale x 8 x iXLen> %a
102}
103declare <vscale x 8 x iXLen> @llvm.vp.lrint.nxv8iXLen.nxv8f32(<vscale x 8 x float>, <vscale x 8 x i1>, i32)
104
105define <vscale x 16 x iXLen> @lrint_nxv16f32(<vscale x 16 x float> %x, <vscale x 16 x i1> %m, i32 zeroext %evl) {
106; RV32-LABEL: lrint_nxv16f32:
107; RV32:       # %bb.0:
108; RV32-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
109; RV32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
110; RV32-NEXT:    ret
111;
112; RV64-i32-LABEL: lrint_nxv16f32:
113; RV64-i32:       # %bb.0:
114; RV64-i32-NEXT:    vsetvli zero, a0, e32, m8, ta, ma
115; RV64-i32-NEXT:    vfcvt.x.f.v v8, v8, v0.t
116; RV64-i32-NEXT:    ret
117;
118; RV64-i64-LABEL: lrint_nxv16f32:
119; RV64-i64:       # %bb.0:
120; RV64-i64-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
121; RV64-i64-NEXT:    vmv1r.v v24, v0
122; RV64-i64-NEXT:    csrr a1, vlenb
123; RV64-i64-NEXT:    srli a2, a1, 3
124; RV64-i64-NEXT:    sub a3, a0, a1
125; RV64-i64-NEXT:    vslidedown.vx v0, v0, a2
126; RV64-i64-NEXT:    sltu a2, a0, a3
127; RV64-i64-NEXT:    addi a2, a2, -1
128; RV64-i64-NEXT:    and a2, a2, a3
129; RV64-i64-NEXT:    vsetvli zero, a2, e32, m4, ta, ma
130; RV64-i64-NEXT:    vfwcvt.x.f.v v16, v12, v0.t
131; RV64-i64-NEXT:    bltu a0, a1, .LBB4_2
132; RV64-i64-NEXT:  # %bb.1:
133; RV64-i64-NEXT:    mv a0, a1
134; RV64-i64-NEXT:  .LBB4_2:
135; RV64-i64-NEXT:    vmv1r.v v0, v24
136; RV64-i64-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
137; RV64-i64-NEXT:    vfwcvt.x.f.v v24, v8, v0.t
138; RV64-i64-NEXT:    vmv8r.v v8, v24
139; RV64-i64-NEXT:    ret
140  %a = call <vscale x 16 x iXLen> @llvm.vp.lrint.nxv16iXLen.nxv16f32(<vscale x 16 x float> %x, <vscale x 16 x i1> %m, i32 %evl)
141  ret <vscale x 16 x iXLen> %a
142}
143declare <vscale x 16 x iXLen> @llvm.vp.lrint.nxv16iXLen.nxv16f32(<vscale x 16 x float>, <vscale x 16 x i1>, i32)
144
145define <vscale x 1 x iXLen> @lrint_nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x i1> %m, i32 zeroext %evl) {
146; RV32-LABEL: lrint_nxv1f64:
147; RV32:       # %bb.0:
148; RV32-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
149; RV32-NEXT:    vfncvt.x.f.w v9, v8, v0.t
150; RV32-NEXT:    vmv1r.v v8, v9
151; RV32-NEXT:    ret
152;
153; RV64-i32-LABEL: lrint_nxv1f64:
154; RV64-i32:       # %bb.0:
155; RV64-i32-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
156; RV64-i32-NEXT:    vfncvt.x.f.w v9, v8, v0.t
157; RV64-i32-NEXT:    vmv1r.v v8, v9
158; RV64-i32-NEXT:    ret
159;
160; RV64-i64-LABEL: lrint_nxv1f64:
161; RV64-i64:       # %bb.0:
162; RV64-i64-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
163; RV64-i64-NEXT:    vfcvt.x.f.v v8, v8, v0.t
164; RV64-i64-NEXT:    ret
165  %a = call <vscale x 1 x iXLen> @llvm.vp.lrint.nxv1iXLen.nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x i1> %m, i32 %evl)
166  ret <vscale x 1 x iXLen> %a
167}
168declare <vscale x 1 x iXLen> @llvm.vp.lrint.nxv1iXLen.nxv1f64(<vscale x 1 x double>, <vscale x 1 x i1>, i32)
169
170define <vscale x 2 x iXLen> @lrint_nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x i1> %m, i32 zeroext %evl) {
171; RV32-LABEL: lrint_nxv2f64:
172; RV32:       # %bb.0:
173; RV32-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
174; RV32-NEXT:    vfncvt.x.f.w v10, v8, v0.t
175; RV32-NEXT:    vmv.v.v v8, v10
176; RV32-NEXT:    ret
177;
178; RV64-i32-LABEL: lrint_nxv2f64:
179; RV64-i32:       # %bb.0:
180; RV64-i32-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
181; RV64-i32-NEXT:    vfncvt.x.f.w v10, v8, v0.t
182; RV64-i32-NEXT:    vmv.v.v v8, v10
183; RV64-i32-NEXT:    ret
184;
185; RV64-i64-LABEL: lrint_nxv2f64:
186; RV64-i64:       # %bb.0:
187; RV64-i64-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
188; RV64-i64-NEXT:    vfcvt.x.f.v v8, v8, v0.t
189; RV64-i64-NEXT:    ret
190  %a = call <vscale x 2 x iXLen> @llvm.vp.lrint.nxv2iXLen.nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x i1> %m, i32 %evl)
191  ret <vscale x 2 x iXLen> %a
192}
193declare <vscale x 2 x iXLen> @llvm.vp.lrint.nxv2iXLen.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, i32)
194
195define <vscale x 4 x iXLen> @lrint_nxv4f64(<vscale x 4 x double> %x, <vscale x 4 x i1> %m, i32 zeroext %evl) {
196; RV32-LABEL: lrint_nxv4f64:
197; RV32:       # %bb.0:
198; RV32-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
199; RV32-NEXT:    vfncvt.x.f.w v12, v8, v0.t
200; RV32-NEXT:    vmv.v.v v8, v12
201; RV32-NEXT:    ret
202;
203; RV64-i32-LABEL: lrint_nxv4f64:
204; RV64-i32:       # %bb.0:
205; RV64-i32-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
206; RV64-i32-NEXT:    vfncvt.x.f.w v12, v8, v0.t
207; RV64-i32-NEXT:    vmv.v.v v8, v12
208; RV64-i32-NEXT:    ret
209;
210; RV64-i64-LABEL: lrint_nxv4f64:
211; RV64-i64:       # %bb.0:
212; RV64-i64-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
213; RV64-i64-NEXT:    vfcvt.x.f.v v8, v8, v0.t
214; RV64-i64-NEXT:    ret
215  %a = call <vscale x 4 x iXLen> @llvm.vp.lrint.nxv4iXLen.nxv4f64(<vscale x 4 x double> %x, <vscale x 4 x i1> %m, i32 %evl)
216  ret <vscale x 4 x iXLen> %a
217}
218declare <vscale x 4 x iXLen> @llvm.vp.lrint.nxv4iXLen.nxv4f64(<vscale x 4 x double>, <vscale x 4 x i1>, i32)
219
220define <vscale x 8 x iXLen> @lrint_nxv8f64(<vscale x 8 x double> %x, <vscale x 8 x i1> %m, i32 zeroext %evl) {
221; RV32-LABEL: lrint_nxv8f64:
222; RV32:       # %bb.0:
223; RV32-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
224; RV32-NEXT:    vfncvt.x.f.w v16, v8, v0.t
225; RV32-NEXT:    vmv.v.v v8, v16
226; RV32-NEXT:    ret
227;
228; RV64-i32-LABEL: lrint_nxv8f64:
229; RV64-i32:       # %bb.0:
230; RV64-i32-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
231; RV64-i32-NEXT:    vfncvt.x.f.w v16, v8, v0.t
232; RV64-i32-NEXT:    vmv.v.v v8, v16
233; RV64-i32-NEXT:    ret
234;
235; RV64-i64-LABEL: lrint_nxv8f64:
236; RV64-i64:       # %bb.0:
237; RV64-i64-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
238; RV64-i64-NEXT:    vfcvt.x.f.v v8, v8, v0.t
239; RV64-i64-NEXT:    ret
240  %a = call <vscale x 8 x iXLen> @llvm.vp.lrint.nxv8iXLen.nxv8f64(<vscale x 8 x double> %x, <vscale x 8 x i1> %m, i32 %evl)
241  ret <vscale x 8 x iXLen> %a
242}
243declare <vscale x 8 x iXLen> @llvm.vp.lrint.nxv8iXLen.nxv8f64(<vscale x 8 x double>, <vscale x 8 x i1>, i32)
244