xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/llrint-sdnode.ll (revision 7a7603883506e1b02be9da560edc6d75d440a1e9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v,+f,+d -target-abi=ilp32d \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+v,+f,+d -target-abi=lp64d \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s
6
7define <vscale x 1 x i64> @llrint_nxv1i64_nxv1f32(<vscale x 1 x float> %x) {
8; CHECK-LABEL: llrint_nxv1i64_nxv1f32:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
11; CHECK-NEXT:    vfwcvt.x.f.v v9, v8
12; CHECK-NEXT:    vmv1r.v v8, v9
13; CHECK-NEXT:    ret
14  %a = call <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1f32(<vscale x 1 x float> %x)
15  ret <vscale x 1 x i64> %a
16}
17declare <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1f32(<vscale x 1 x float>)
18
19define <vscale x 2 x i64> @llrint_nxv2i64_nxv2f32(<vscale x 2 x float> %x) {
20; CHECK-LABEL: llrint_nxv2i64_nxv2f32:
21; CHECK:       # %bb.0:
22; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
23; CHECK-NEXT:    vfwcvt.x.f.v v10, v8
24; CHECK-NEXT:    vmv2r.v v8, v10
25; CHECK-NEXT:    ret
26  %a = call <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2f32(<vscale x 2 x float> %x)
27  ret <vscale x 2 x i64> %a
28}
29declare <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2f32(<vscale x 2 x float>)
30
31define <vscale x 4 x i64> @llrint_nxv4i64_nxv4f32(<vscale x 4 x float> %x) {
32; CHECK-LABEL: llrint_nxv4i64_nxv4f32:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
35; CHECK-NEXT:    vfwcvt.x.f.v v12, v8
36; CHECK-NEXT:    vmv4r.v v8, v12
37; CHECK-NEXT:    ret
38  %a = call <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f32(<vscale x 4 x float> %x)
39  ret <vscale x 4 x i64> %a
40}
41declare <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f32(<vscale x 4 x float>)
42
43define <vscale x 8 x i64> @llrint_nxv8i64_nxv8f32(<vscale x 8 x float> %x) {
44; CHECK-LABEL: llrint_nxv8i64_nxv8f32:
45; CHECK:       # %bb.0:
46; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
47; CHECK-NEXT:    vfwcvt.x.f.v v16, v8
48; CHECK-NEXT:    vmv8r.v v8, v16
49; CHECK-NEXT:    ret
50  %a = call <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f32(<vscale x 8 x float> %x)
51  ret <vscale x 8 x i64> %a
52}
53declare <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f32(<vscale x 8 x float>)
54
55define <vscale x 16 x i64> @llrint_nxv16i64_nxv16f32(<vscale x 16 x float> %x) {
56; CHECK-LABEL: llrint_nxv16i64_nxv16f32:
57; CHECK:       # %bb.0:
58; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
59; CHECK-NEXT:    vfwcvt.x.f.v v24, v8
60; CHECK-NEXT:    vfwcvt.x.f.v v16, v12
61; CHECK-NEXT:    vmv8r.v v8, v24
62; CHECK-NEXT:    ret
63  %a = call <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f32(<vscale x 16 x float> %x)
64  ret <vscale x 16 x i64> %a
65}
66declare <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f32(<vscale x 16 x float>)
67
68define <vscale x 1 x i64> @llrint_nxv1i64_nxv1f64(<vscale x 1 x double> %x) {
69; CHECK-LABEL: llrint_nxv1i64_nxv1f64:
70; CHECK:       # %bb.0:
71; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
72; CHECK-NEXT:    vfcvt.x.f.v v8, v8
73; CHECK-NEXT:    ret
74  %a = call <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1f64(<vscale x 1 x double> %x)
75  ret <vscale x 1 x i64> %a
76}
77declare <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1f64(<vscale x 1 x double>)
78
79define <vscale x 2 x i64> @llrint_nxv2i64_nxv2f64(<vscale x 2 x double> %x) {
80; CHECK-LABEL: llrint_nxv2i64_nxv2f64:
81; CHECK:       # %bb.0:
82; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
83; CHECK-NEXT:    vfcvt.x.f.v v8, v8
84; CHECK-NEXT:    ret
85  %a = call <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2f64(<vscale x 2 x double> %x)
86  ret <vscale x 2 x i64> %a
87}
88declare <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2f64(<vscale x 2 x double>)
89
90define <vscale x 4 x i64> @llrint_nxv4i64_nxv4f64(<vscale x 4 x double> %x) {
91; CHECK-LABEL: llrint_nxv4i64_nxv4f64:
92; CHECK:       # %bb.0:
93; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
94; CHECK-NEXT:    vfcvt.x.f.v v8, v8
95; CHECK-NEXT:    ret
96  %a = call <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f64(<vscale x 4 x double> %x)
97  ret <vscale x 4 x i64> %a
98}
99declare <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f64(<vscale x 4 x double>)
100
101define <vscale x 8 x i64> @llrint_nxv8i64_nxv8f64(<vscale x 8 x double> %x) {
102; CHECK-LABEL: llrint_nxv8i64_nxv8f64:
103; CHECK:       # %bb.0:
104; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
105; CHECK-NEXT:    vfcvt.x.f.v v8, v8
106; CHECK-NEXT:    ret
107  %a = call <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f64(<vscale x 8 x double> %x)
108  ret <vscale x 8 x i64> %a
109}
110declare <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f64(<vscale x 8 x double>)
111