1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s 3; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s 4 5; Check that we are able to legalize scalable-vector loads that require widening. 6 7define <vscale x 3 x i8> @load_nxv3i8(ptr %ptr) { 8; CHECK-LABEL: load_nxv3i8: 9; CHECK: # %bb.0: 10; CHECK-NEXT: csrr a1, vlenb 11; CHECK-NEXT: srli a1, a1, 3 12; CHECK-NEXT: slli a2, a1, 1 13; CHECK-NEXT: add a1, a2, a1 14; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma 15; CHECK-NEXT: vle8.v v8, (a0) 16; CHECK-NEXT: ret 17 %v = load <vscale x 3 x i8>, ptr %ptr 18 ret <vscale x 3 x i8> %v 19} 20 21define <vscale x 5 x half> @load_nxv5f16(ptr %ptr) { 22; CHECK-LABEL: load_nxv5f16: 23; CHECK: # %bb.0: 24; CHECK-NEXT: csrr a1, vlenb 25; CHECK-NEXT: srli a1, a1, 3 26; CHECK-NEXT: slli a2, a1, 2 27; CHECK-NEXT: add a1, a2, a1 28; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma 29; CHECK-NEXT: vle16.v v8, (a0) 30; CHECK-NEXT: ret 31 %v = load <vscale x 5 x half>, ptr %ptr 32 ret <vscale x 5 x half> %v 33} 34 35define <vscale x 7 x half> @load_nxv7f16(ptr %ptr, ptr %out) { 36; CHECK-LABEL: load_nxv7f16: 37; CHECK: # %bb.0: 38; CHECK-NEXT: csrr a2, vlenb 39; CHECK-NEXT: srli a3, a2, 3 40; CHECK-NEXT: sub a2, a2, a3 41; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma 42; CHECK-NEXT: vle16.v v8, (a0) 43; CHECK-NEXT: vse16.v v8, (a1) 44; CHECK-NEXT: ret 45 %v = load <vscale x 7 x half>, ptr %ptr 46 store <vscale x 7 x half> %v, ptr %out 47 ret <vscale x 7 x half> %v 48} 49