xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll (revision f1bb88bee248fb30e3145a2a19373233b7a59882) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
3; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
4
5declare i32 @llvm.experimental.get.vector.length.i16(i16, i32, i1)
6declare i32 @llvm.experimental.get.vector.length.i32(i32, i32, i1)
7declare i32 @llvm.experimental.get.vector.length.i64(i64, i32, i1)
8
9define i32 @vector_length_i16(i16 zeroext %tc) {
10; CHECK-LABEL: vector_length_i16:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    csrr a1, vlenb
13; CHECK-NEXT:    srli a1, a1, 2
14; CHECK-NEXT:    bltu a0, a1, .LBB0_2
15; CHECK-NEXT:  # %bb.1:
16; CHECK-NEXT:    mv a0, a1
17; CHECK-NEXT:  .LBB0_2:
18; CHECK-NEXT:    ret
19  %a = call i32 @llvm.experimental.get.vector.length.i16(i16 %tc, i32 2, i1 true)
20  ret i32 %a
21}
22
23define i32 @vector_length_i32(i32 zeroext %tc) {
24; CHECK-LABEL: vector_length_i32:
25; CHECK:       # %bb.0:
26; CHECK-NEXT:    vsetvli a0, a0, e8, mf4, ta, ma
27; CHECK-NEXT:    ret
28  %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 2, i1 true)
29  ret i32 %a
30}
31
32define i32 @vector_length_XLen(iXLen zeroext %tc) {
33; CHECK-LABEL: vector_length_XLen:
34; CHECK:       # %bb.0:
35; CHECK-NEXT:    vsetvli a0, a0, e8, mf4, ta, ma
36; CHECK-NEXT:    ret
37  %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 2, i1 true)
38  ret i32 %a
39}
40
41define i32 @vector_length_i16_fixed(i16 zeroext %tc) {
42; CHECK-LABEL: vector_length_i16_fixed:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    li a1, 2
45; CHECK-NEXT:    bltu a0, a1, .LBB3_2
46; CHECK-NEXT:  # %bb.1:
47; CHECK-NEXT:    li a0, 2
48; CHECK-NEXT:  .LBB3_2:
49; CHECK-NEXT:    ret
50  %a = call i32 @llvm.experimental.get.vector.length.i16(i16 %tc, i32 2, i1 false)
51  ret i32 %a
52}
53
54define i32 @vector_length_i32_fixed(i32 zeroext %tc) {
55; CHECK-LABEL: vector_length_i32_fixed:
56; CHECK:       # %bb.0:
57; CHECK-NEXT:    li a1, 2
58; CHECK-NEXT:    bltu a0, a1, .LBB4_2
59; CHECK-NEXT:  # %bb.1:
60; CHECK-NEXT:    li a0, 2
61; CHECK-NEXT:  .LBB4_2:
62; CHECK-NEXT:    ret
63  %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 2, i1 false)
64  ret i32 %a
65}
66
67define i32 @vector_length_XLen_fixed(iXLen zeroext %tc) {
68; CHECK-LABEL: vector_length_XLen_fixed:
69; CHECK:       # %bb.0:
70; CHECK-NEXT:    li a1, 2
71; CHECK-NEXT:    bltu a0, a1, .LBB5_2
72; CHECK-NEXT:  # %bb.1:
73; CHECK-NEXT:    li a0, 2
74; CHECK-NEXT:  .LBB5_2:
75; CHECK-NEXT:    ret
76  %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 2, i1 false)
77  ret i32 %a
78}
79
80define i32 @vector_length_vf1_i32(i32 zeroext %tc) {
81; CHECK-LABEL: vector_length_vf1_i32:
82; CHECK:       # %bb.0:
83; CHECK-NEXT:    vsetvli a0, a0, e8, mf8, ta, ma
84; CHECK-NEXT:    ret
85  %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 1, i1 true)
86  ret i32 %a
87}
88
89define i32 @vector_length_vf1_XLen(iXLen zeroext %tc) {
90; CHECK-LABEL: vector_length_vf1_XLen:
91; CHECK:       # %bb.0:
92; CHECK-NEXT:    vsetvli a0, a0, e8, mf8, ta, ma
93; CHECK-NEXT:    ret
94  %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 1, i1 true)
95  ret i32 %a
96}
97
98define i32 @vector_length_vf2_i32(i32 zeroext %tc) {
99; CHECK-LABEL: vector_length_vf2_i32:
100; CHECK:       # %bb.0:
101; CHECK-NEXT:    vsetvli a0, a0, e8, mf4, ta, ma
102; CHECK-NEXT:    ret
103  %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 2, i1 true)
104  ret i32 %a
105}
106
107define i32 @vector_length_vf2_XLen(iXLen zeroext %tc) {
108; CHECK-LABEL: vector_length_vf2_XLen:
109; CHECK:       # %bb.0:
110; CHECK-NEXT:    vsetvli a0, a0, e8, mf4, ta, ma
111; CHECK-NEXT:    ret
112  %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 2, i1 true)
113  ret i32 %a
114}
115
116define i32 @vector_length_vf4_i32(i32 zeroext %tc) {
117; CHECK-LABEL: vector_length_vf4_i32:
118; CHECK:       # %bb.0:
119; CHECK-NEXT:    vsetvli a0, a0, e8, mf2, ta, ma
120; CHECK-NEXT:    ret
121  %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 4, i1 true)
122  ret i32 %a
123}
124
125define i32 @vector_length_vf4_XLen(iXLen zeroext %tc) {
126; CHECK-LABEL: vector_length_vf4_XLen:
127; CHECK:       # %bb.0:
128; CHECK-NEXT:    vsetvli a0, a0, e8, mf2, ta, ma
129; CHECK-NEXT:    ret
130  %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 4, i1 true)
131  ret i32 %a
132}
133
134define i32 @vector_length_vf8_i32(i32 zeroext %tc) {
135; CHECK-LABEL: vector_length_vf8_i32:
136; CHECK:       # %bb.0:
137; CHECK-NEXT:    vsetvli a0, a0, e8, m1, ta, ma
138; CHECK-NEXT:    ret
139  %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 8, i1 true)
140  ret i32 %a
141}
142
143define i32 @vector_length_vf8_XLen(iXLen zeroext %tc) {
144; CHECK-LABEL: vector_length_vf8_XLen:
145; CHECK:       # %bb.0:
146; CHECK-NEXT:    vsetvli a0, a0, e8, m1, ta, ma
147; CHECK-NEXT:    ret
148  %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 8, i1 true)
149  ret i32 %a
150}
151
152define i32 @vector_length_vf16_i32(i32 zeroext %tc) {
153; CHECK-LABEL: vector_length_vf16_i32:
154; CHECK:       # %bb.0:
155; CHECK-NEXT:    vsetvli a0, a0, e8, m2, ta, ma
156; CHECK-NEXT:    ret
157  %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 16, i1 true)
158  ret i32 %a
159}
160
161define i32 @vector_length_vf16_XLen(iXLen zeroext %tc) {
162; CHECK-LABEL: vector_length_vf16_XLen:
163; CHECK:       # %bb.0:
164; CHECK-NEXT:    vsetvli a0, a0, e8, m2, ta, ma
165; CHECK-NEXT:    ret
166  %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 16, i1 true)
167  ret i32 %a
168}
169
170define i32 @vector_length_vf32_i32(i32 zeroext %tc) {
171; CHECK-LABEL: vector_length_vf32_i32:
172; CHECK:       # %bb.0:
173; CHECK-NEXT:    vsetvli a0, a0, e8, m4, ta, ma
174; CHECK-NEXT:    ret
175  %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 32, i1 true)
176  ret i32 %a
177}
178
179define i32 @vector_length_vf32_XLen(iXLen zeroext %tc) {
180; CHECK-LABEL: vector_length_vf32_XLen:
181; CHECK:       # %bb.0:
182; CHECK-NEXT:    vsetvli a0, a0, e8, m4, ta, ma
183; CHECK-NEXT:    ret
184  %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 32, i1 true)
185  ret i32 %a
186}
187
188define i32 @vector_length_vf64_i32(i32 zeroext %tc) {
189; CHECK-LABEL: vector_length_vf64_i32:
190; CHECK:       # %bb.0:
191; CHECK-NEXT:    vsetvli a0, a0, e8, m8, ta, ma
192; CHECK-NEXT:    ret
193  %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 64, i1 true)
194  ret i32 %a
195}
196
197define i32 @vector_length_vf64_XLen(iXLen zeroext %tc) {
198; CHECK-LABEL: vector_length_vf64_XLen:
199; CHECK:       # %bb.0:
200; CHECK-NEXT:    vsetvli a0, a0, e8, m8, ta, ma
201; CHECK-NEXT:    ret
202  %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 64, i1 true)
203  ret i32 %a
204}
205
206define i32 @vector_length_vf128_i32(i32 zeroext %tc) {
207; RV32-LABEL: vector_length_vf128_i32:
208; RV32:       # %bb.0:
209; RV32-NEXT:    csrr a1, vlenb
210; RV32-NEXT:    slli a1, a1, 4
211; RV32-NEXT:    bltu a0, a1, .LBB20_2
212; RV32-NEXT:  # %bb.1:
213; RV32-NEXT:    mv a0, a1
214; RV32-NEXT:  .LBB20_2:
215; RV32-NEXT:    ret
216;
217; RV64-LABEL: vector_length_vf128_i32:
218; RV64:       # %bb.0:
219; RV64-NEXT:    sext.w a0, a0
220; RV64-NEXT:    csrr a1, vlenb
221; RV64-NEXT:    slli a1, a1, 4
222; RV64-NEXT:    bltu a0, a1, .LBB20_2
223; RV64-NEXT:  # %bb.1:
224; RV64-NEXT:    mv a0, a1
225; RV64-NEXT:  .LBB20_2:
226; RV64-NEXT:    ret
227  %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 128, i1 true)
228  ret i32 %a
229}
230
231define i32 @vector_length_vf128_XLen(iXLen zeroext %tc) {
232; RV32-LABEL: vector_length_vf128_XLen:
233; RV32:       # %bb.0:
234; RV32-NEXT:    csrr a1, vlenb
235; RV32-NEXT:    slli a1, a1, 4
236; RV32-NEXT:    bltu a0, a1, .LBB21_2
237; RV32-NEXT:  # %bb.1:
238; RV32-NEXT:    mv a0, a1
239; RV32-NEXT:  .LBB21_2:
240; RV32-NEXT:    ret
241;
242; RV64-LABEL: vector_length_vf128_XLen:
243; RV64:       # %bb.0:
244; RV64-NEXT:    sext.w a0, a0
245; RV64-NEXT:    csrr a1, vlenb
246; RV64-NEXT:    slli a1, a1, 4
247; RV64-NEXT:    bltu a0, a1, .LBB21_2
248; RV64-NEXT:  # %bb.1:
249; RV64-NEXT:    mv a0, a1
250; RV64-NEXT:  .LBB21_2:
251; RV64-NEXT:    ret
252  %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 128, i1 true)
253  ret i32 %a
254}
255
256define i32 @vector_length_vf3_i32(i32 zeroext %tc) {
257; RV32-LABEL: vector_length_vf3_i32:
258; RV32:       # %bb.0:
259; RV32-NEXT:    csrr a1, vlenb
260; RV32-NEXT:    srli a1, a1, 3
261; RV32-NEXT:    slli a2, a1, 1
262; RV32-NEXT:    add a1, a2, a1
263; RV32-NEXT:    bltu a0, a1, .LBB22_2
264; RV32-NEXT:  # %bb.1:
265; RV32-NEXT:    mv a0, a1
266; RV32-NEXT:  .LBB22_2:
267; RV32-NEXT:    ret
268;
269; RV64-LABEL: vector_length_vf3_i32:
270; RV64:       # %bb.0:
271; RV64-NEXT:    sext.w a0, a0
272; RV64-NEXT:    csrr a1, vlenb
273; RV64-NEXT:    srli a1, a1, 3
274; RV64-NEXT:    slli a2, a1, 1
275; RV64-NEXT:    add a1, a2, a1
276; RV64-NEXT:    bltu a0, a1, .LBB22_2
277; RV64-NEXT:  # %bb.1:
278; RV64-NEXT:    mv a0, a1
279; RV64-NEXT:  .LBB22_2:
280; RV64-NEXT:    ret
281  %a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 3, i1 true)
282  ret i32 %a
283}
284
285define i32 @vector_length_vf3_XLen(iXLen zeroext %tc) {
286; RV32-LABEL: vector_length_vf3_XLen:
287; RV32:       # %bb.0:
288; RV32-NEXT:    csrr a1, vlenb
289; RV32-NEXT:    srli a1, a1, 3
290; RV32-NEXT:    slli a2, a1, 1
291; RV32-NEXT:    add a1, a2, a1
292; RV32-NEXT:    bltu a0, a1, .LBB23_2
293; RV32-NEXT:  # %bb.1:
294; RV32-NEXT:    mv a0, a1
295; RV32-NEXT:  .LBB23_2:
296; RV32-NEXT:    ret
297;
298; RV64-LABEL: vector_length_vf3_XLen:
299; RV64:       # %bb.0:
300; RV64-NEXT:    sext.w a0, a0
301; RV64-NEXT:    csrr a1, vlenb
302; RV64-NEXT:    srli a1, a1, 3
303; RV64-NEXT:    slli a2, a1, 1
304; RV64-NEXT:    add a1, a2, a1
305; RV64-NEXT:    bltu a0, a1, .LBB23_2
306; RV64-NEXT:  # %bb.1:
307; RV64-NEXT:    mv a0, a1
308; RV64-NEXT:  .LBB23_2:
309; RV64-NEXT:    ret
310  %a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 3, i1 true)
311  ret i32 %a
312}
313