xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s
4
5declare <vscale x 1 x i8> @llvm.vp.fshr.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
6define <vscale x 1 x i8> @fshr_v1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, <vscale x 1 x i8> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
7; CHECK-LABEL: fshr_v1i8:
8; CHECK:       # %bb.0:
9; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
10; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
11; CHECK-NEXT:    vnot.v v11, v10, v0.t
12; CHECK-NEXT:    vand.vi v11, v11, 7, v0.t
13; CHECK-NEXT:    vsll.vv v8, v8, v11, v0.t
14; CHECK-NEXT:    vand.vi v10, v10, 7, v0.t
15; CHECK-NEXT:    vsrl.vv v9, v9, v10, v0.t
16; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
17; CHECK-NEXT:    ret
18  %res = call <vscale x 1 x i8> @llvm.vp.fshr.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, <vscale x 1 x i8> %c, <vscale x 1 x i1> %m, i32 %evl)
19  ret <vscale x 1 x i8> %res
20}
21
22declare <vscale x 1 x i8> @llvm.vp.fshl.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i32)
23define <vscale x 1 x i8> @fshl_v1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, <vscale x 1 x i8> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
24; CHECK-LABEL: fshl_v1i8:
25; CHECK:       # %bb.0:
26; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
27; CHECK-NEXT:    vsrl.vi v9, v9, 1, v0.t
28; CHECK-NEXT:    vnot.v v11, v10, v0.t
29; CHECK-NEXT:    vand.vi v11, v11, 7, v0.t
30; CHECK-NEXT:    vsrl.vv v9, v9, v11, v0.t
31; CHECK-NEXT:    vand.vi v10, v10, 7, v0.t
32; CHECK-NEXT:    vsll.vv v8, v8, v10, v0.t
33; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
34; CHECK-NEXT:    ret
35  %res = call <vscale x 1 x i8> @llvm.vp.fshl.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, <vscale x 1 x i8> %c, <vscale x 1 x i1> %m, i32 %evl)
36  ret <vscale x 1 x i8> %res
37}
38
39declare <vscale x 2 x i8> @llvm.vp.fshr.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
40define <vscale x 2 x i8> @fshr_v2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, <vscale x 2 x i8> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {
41; CHECK-LABEL: fshr_v2i8:
42; CHECK:       # %bb.0:
43; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
44; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
45; CHECK-NEXT:    vnot.v v11, v10, v0.t
46; CHECK-NEXT:    vand.vi v11, v11, 7, v0.t
47; CHECK-NEXT:    vsll.vv v8, v8, v11, v0.t
48; CHECK-NEXT:    vand.vi v10, v10, 7, v0.t
49; CHECK-NEXT:    vsrl.vv v9, v9, v10, v0.t
50; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
51; CHECK-NEXT:    ret
52  %res = call <vscale x 2 x i8> @llvm.vp.fshr.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, <vscale x 2 x i8> %c, <vscale x 2 x i1> %m, i32 %evl)
53  ret <vscale x 2 x i8> %res
54}
55
56declare <vscale x 2 x i8> @llvm.vp.fshl.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i32)
57define <vscale x 2 x i8> @fshl_v2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, <vscale x 2 x i8> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {
58; CHECK-LABEL: fshl_v2i8:
59; CHECK:       # %bb.0:
60; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
61; CHECK-NEXT:    vsrl.vi v9, v9, 1, v0.t
62; CHECK-NEXT:    vnot.v v11, v10, v0.t
63; CHECK-NEXT:    vand.vi v11, v11, 7, v0.t
64; CHECK-NEXT:    vsrl.vv v9, v9, v11, v0.t
65; CHECK-NEXT:    vand.vi v10, v10, 7, v0.t
66; CHECK-NEXT:    vsll.vv v8, v8, v10, v0.t
67; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
68; CHECK-NEXT:    ret
69  %res = call <vscale x 2 x i8> @llvm.vp.fshl.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, <vscale x 2 x i8> %c, <vscale x 2 x i1> %m, i32 %evl)
70  ret <vscale x 2 x i8> %res
71}
72
73declare <vscale x 4 x i8> @llvm.vp.fshr.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
74define <vscale x 4 x i8> @fshr_v4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, <vscale x 4 x i8> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {
75; CHECK-LABEL: fshr_v4i8:
76; CHECK:       # %bb.0:
77; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
78; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
79; CHECK-NEXT:    vnot.v v11, v10, v0.t
80; CHECK-NEXT:    vand.vi v11, v11, 7, v0.t
81; CHECK-NEXT:    vsll.vv v8, v8, v11, v0.t
82; CHECK-NEXT:    vand.vi v10, v10, 7, v0.t
83; CHECK-NEXT:    vsrl.vv v9, v9, v10, v0.t
84; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
85; CHECK-NEXT:    ret
86  %res = call <vscale x 4 x i8> @llvm.vp.fshr.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, <vscale x 4 x i8> %c, <vscale x 4 x i1> %m, i32 %evl)
87  ret <vscale x 4 x i8> %res
88}
89
90declare <vscale x 4 x i8> @llvm.vp.fshl.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i32)
91define <vscale x 4 x i8> @fshl_v4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, <vscale x 4 x i8> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {
92; CHECK-LABEL: fshl_v4i8:
93; CHECK:       # %bb.0:
94; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
95; CHECK-NEXT:    vsrl.vi v9, v9, 1, v0.t
96; CHECK-NEXT:    vnot.v v11, v10, v0.t
97; CHECK-NEXT:    vand.vi v11, v11, 7, v0.t
98; CHECK-NEXT:    vsrl.vv v9, v9, v11, v0.t
99; CHECK-NEXT:    vand.vi v10, v10, 7, v0.t
100; CHECK-NEXT:    vsll.vv v8, v8, v10, v0.t
101; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
102; CHECK-NEXT:    ret
103  %res = call <vscale x 4 x i8> @llvm.vp.fshl.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b, <vscale x 4 x i8> %c, <vscale x 4 x i1> %m, i32 %evl)
104  ret <vscale x 4 x i8> %res
105}
106
107declare <vscale x 8 x i8> @llvm.vp.fshr.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
108define <vscale x 8 x i8> @fshr_v8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {
109; CHECK-LABEL: fshr_v8i8:
110; CHECK:       # %bb.0:
111; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
112; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
113; CHECK-NEXT:    vnot.v v11, v10, v0.t
114; CHECK-NEXT:    vand.vi v11, v11, 7, v0.t
115; CHECK-NEXT:    vsll.vv v8, v8, v11, v0.t
116; CHECK-NEXT:    vand.vi v10, v10, 7, v0.t
117; CHECK-NEXT:    vsrl.vv v9, v9, v10, v0.t
118; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
119; CHECK-NEXT:    ret
120  %res = call <vscale x 8 x i8> @llvm.vp.fshr.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i1> %m, i32 %evl)
121  ret <vscale x 8 x i8> %res
122}
123
124declare <vscale x 8 x i8> @llvm.vp.fshl.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i32)
125define <vscale x 8 x i8> @fshl_v8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {
126; CHECK-LABEL: fshl_v8i8:
127; CHECK:       # %bb.0:
128; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
129; CHECK-NEXT:    vsrl.vi v9, v9, 1, v0.t
130; CHECK-NEXT:    vnot.v v11, v10, v0.t
131; CHECK-NEXT:    vand.vi v11, v11, 7, v0.t
132; CHECK-NEXT:    vsrl.vv v9, v9, v11, v0.t
133; CHECK-NEXT:    vand.vi v10, v10, 7, v0.t
134; CHECK-NEXT:    vsll.vv v8, v8, v10, v0.t
135; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
136; CHECK-NEXT:    ret
137  %res = call <vscale x 8 x i8> @llvm.vp.fshl.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i1> %m, i32 %evl)
138  ret <vscale x 8 x i8> %res
139}
140
141declare <vscale x 16 x i8> @llvm.vp.fshr.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, i32)
142define <vscale x 16 x i8> @fshr_v16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {
143; CHECK-LABEL: fshr_v16i8:
144; CHECK:       # %bb.0:
145; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
146; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
147; CHECK-NEXT:    vnot.v v14, v12, v0.t
148; CHECK-NEXT:    vand.vi v14, v14, 7, v0.t
149; CHECK-NEXT:    vsll.vv v8, v8, v14, v0.t
150; CHECK-NEXT:    vand.vi v12, v12, 7, v0.t
151; CHECK-NEXT:    vsrl.vv v10, v10, v12, v0.t
152; CHECK-NEXT:    vor.vv v8, v8, v10, v0.t
153; CHECK-NEXT:    ret
154  %res = call <vscale x 16 x i8> @llvm.vp.fshr.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i1> %m, i32 %evl)
155  ret <vscale x 16 x i8> %res
156}
157
158declare <vscale x 16 x i8> @llvm.vp.fshl.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, i32)
159define <vscale x 16 x i8> @fshl_v16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {
160; CHECK-LABEL: fshl_v16i8:
161; CHECK:       # %bb.0:
162; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
163; CHECK-NEXT:    vsrl.vi v10, v10, 1, v0.t
164; CHECK-NEXT:    vnot.v v14, v12, v0.t
165; CHECK-NEXT:    vand.vi v14, v14, 7, v0.t
166; CHECK-NEXT:    vsrl.vv v10, v10, v14, v0.t
167; CHECK-NEXT:    vand.vi v12, v12, 7, v0.t
168; CHECK-NEXT:    vsll.vv v8, v8, v12, v0.t
169; CHECK-NEXT:    vor.vv v8, v8, v10, v0.t
170; CHECK-NEXT:    ret
171  %res = call <vscale x 16 x i8> @llvm.vp.fshl.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i1> %m, i32 %evl)
172  ret <vscale x 16 x i8> %res
173}
174
175declare <vscale x 32 x i8> @llvm.vp.fshr.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i1>, i32)
176define <vscale x 32 x i8> @fshr_v32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, <vscale x 32 x i8> %c, <vscale x 32 x i1> %m, i32 zeroext %evl) {
177; CHECK-LABEL: fshr_v32i8:
178; CHECK:       # %bb.0:
179; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
180; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
181; CHECK-NEXT:    vnot.v v20, v16, v0.t
182; CHECK-NEXT:    vand.vi v20, v20, 7, v0.t
183; CHECK-NEXT:    vsll.vv v8, v8, v20, v0.t
184; CHECK-NEXT:    vand.vi v16, v16, 7, v0.t
185; CHECK-NEXT:    vsrl.vv v12, v12, v16, v0.t
186; CHECK-NEXT:    vor.vv v8, v8, v12, v0.t
187; CHECK-NEXT:    ret
188  %res = call <vscale x 32 x i8> @llvm.vp.fshr.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, <vscale x 32 x i8> %c, <vscale x 32 x i1> %m, i32 %evl)
189  ret <vscale x 32 x i8> %res
190}
191
192declare <vscale x 32 x i8> @llvm.vp.fshl.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i1>, i32)
193define <vscale x 32 x i8> @fshl_v32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, <vscale x 32 x i8> %c, <vscale x 32 x i1> %m, i32 zeroext %evl) {
194; CHECK-LABEL: fshl_v32i8:
195; CHECK:       # %bb.0:
196; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
197; CHECK-NEXT:    vsrl.vi v12, v12, 1, v0.t
198; CHECK-NEXT:    vnot.v v20, v16, v0.t
199; CHECK-NEXT:    vand.vi v20, v20, 7, v0.t
200; CHECK-NEXT:    vsrl.vv v12, v12, v20, v0.t
201; CHECK-NEXT:    vand.vi v16, v16, 7, v0.t
202; CHECK-NEXT:    vsll.vv v8, v8, v16, v0.t
203; CHECK-NEXT:    vor.vv v8, v8, v12, v0.t
204; CHECK-NEXT:    ret
205  %res = call <vscale x 32 x i8> @llvm.vp.fshl.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b, <vscale x 32 x i8> %c, <vscale x 32 x i1> %m, i32 %evl)
206  ret <vscale x 32 x i8> %res
207}
208
209declare <vscale x 64 x i8> @llvm.vp.fshr.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i1>, i32)
210define <vscale x 64 x i8> @fshr_v64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, <vscale x 64 x i8> %c, <vscale x 64 x i1> %m, i32 zeroext %evl) {
211; CHECK-LABEL: fshr_v64i8:
212; CHECK:       # %bb.0:
213; CHECK-NEXT:    addi sp, sp, -16
214; CHECK-NEXT:    .cfi_def_cfa_offset 16
215; CHECK-NEXT:    csrr a2, vlenb
216; CHECK-NEXT:    slli a2, a2, 3
217; CHECK-NEXT:    sub sp, sp, a2
218; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
219; CHECK-NEXT:    addi a2, sp, 16
220; CHECK-NEXT:    vs8r.v v16, (a2) # Unknown-size Folded Spill
221; CHECK-NEXT:    vl8r.v v24, (a0)
222; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
223; CHECK-NEXT:    vsll.vi v16, v8, 1, v0.t
224; CHECK-NEXT:    vnot.v v8, v24, v0.t
225; CHECK-NEXT:    vand.vi v8, v8, 7, v0.t
226; CHECK-NEXT:    vsll.vv v8, v16, v8, v0.t
227; CHECK-NEXT:    vand.vi v16, v24, 7, v0.t
228; CHECK-NEXT:    addi a0, sp, 16
229; CHECK-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
230; CHECK-NEXT:    vsrl.vv v16, v24, v16, v0.t
231; CHECK-NEXT:    vor.vv v8, v8, v16, v0.t
232; CHECK-NEXT:    csrr a0, vlenb
233; CHECK-NEXT:    slli a0, a0, 3
234; CHECK-NEXT:    add sp, sp, a0
235; CHECK-NEXT:    .cfi_def_cfa sp, 16
236; CHECK-NEXT:    addi sp, sp, 16
237; CHECK-NEXT:    .cfi_def_cfa_offset 0
238; CHECK-NEXT:    ret
239  %res = call <vscale x 64 x i8> @llvm.vp.fshr.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, <vscale x 64 x i8> %c, <vscale x 64 x i1> %m, i32 %evl)
240  ret <vscale x 64 x i8> %res
241}
242
243declare <vscale x 64 x i8> @llvm.vp.fshl.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i1>, i32)
244define <vscale x 64 x i8> @fshl_v64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, <vscale x 64 x i8> %c, <vscale x 64 x i1> %m, i32 zeroext %evl) {
245; CHECK-LABEL: fshl_v64i8:
246; CHECK:       # %bb.0:
247; CHECK-NEXT:    addi sp, sp, -16
248; CHECK-NEXT:    .cfi_def_cfa_offset 16
249; CHECK-NEXT:    csrr a2, vlenb
250; CHECK-NEXT:    slli a2, a2, 3
251; CHECK-NEXT:    sub sp, sp, a2
252; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
253; CHECK-NEXT:    addi a2, sp, 16
254; CHECK-NEXT:    vs8r.v v8, (a2) # Unknown-size Folded Spill
255; CHECK-NEXT:    vl8r.v v24, (a0)
256; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
257; CHECK-NEXT:    vsrl.vi v16, v16, 1, v0.t
258; CHECK-NEXT:    vnot.v v8, v24, v0.t
259; CHECK-NEXT:    vand.vi v8, v8, 7, v0.t
260; CHECK-NEXT:    vsrl.vv v8, v16, v8, v0.t
261; CHECK-NEXT:    vand.vi v16, v24, 7, v0.t
262; CHECK-NEXT:    addi a0, sp, 16
263; CHECK-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
264; CHECK-NEXT:    vsll.vv v16, v24, v16, v0.t
265; CHECK-NEXT:    vor.vv v8, v16, v8, v0.t
266; CHECK-NEXT:    csrr a0, vlenb
267; CHECK-NEXT:    slli a0, a0, 3
268; CHECK-NEXT:    add sp, sp, a0
269; CHECK-NEXT:    .cfi_def_cfa sp, 16
270; CHECK-NEXT:    addi sp, sp, 16
271; CHECK-NEXT:    .cfi_def_cfa_offset 0
272; CHECK-NEXT:    ret
273  %res = call <vscale x 64 x i8> @llvm.vp.fshl.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b, <vscale x 64 x i8> %c, <vscale x 64 x i1> %m, i32 %evl)
274  ret <vscale x 64 x i8> %res
275}
276
277declare <vscale x 1 x i16> @llvm.vp.fshr.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
278define <vscale x 1 x i16> @fshr_v1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, <vscale x 1 x i16> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
279; CHECK-LABEL: fshr_v1i16:
280; CHECK:       # %bb.0:
281; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
282; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
283; CHECK-NEXT:    vnot.v v11, v10, v0.t
284; CHECK-NEXT:    vand.vi v11, v11, 15, v0.t
285; CHECK-NEXT:    vsll.vv v8, v8, v11, v0.t
286; CHECK-NEXT:    vand.vi v10, v10, 15, v0.t
287; CHECK-NEXT:    vsrl.vv v9, v9, v10, v0.t
288; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
289; CHECK-NEXT:    ret
290  %res = call <vscale x 1 x i16> @llvm.vp.fshr.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, <vscale x 1 x i16> %c, <vscale x 1 x i1> %m, i32 %evl)
291  ret <vscale x 1 x i16> %res
292}
293
294declare <vscale x 1 x i16> @llvm.vp.fshl.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i1>, i32)
295define <vscale x 1 x i16> @fshl_v1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, <vscale x 1 x i16> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
296; CHECK-LABEL: fshl_v1i16:
297; CHECK:       # %bb.0:
298; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
299; CHECK-NEXT:    vsrl.vi v9, v9, 1, v0.t
300; CHECK-NEXT:    vnot.v v11, v10, v0.t
301; CHECK-NEXT:    vand.vi v11, v11, 15, v0.t
302; CHECK-NEXT:    vsrl.vv v9, v9, v11, v0.t
303; CHECK-NEXT:    vand.vi v10, v10, 15, v0.t
304; CHECK-NEXT:    vsll.vv v8, v8, v10, v0.t
305; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
306; CHECK-NEXT:    ret
307  %res = call <vscale x 1 x i16> @llvm.vp.fshl.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b, <vscale x 1 x i16> %c, <vscale x 1 x i1> %m, i32 %evl)
308  ret <vscale x 1 x i16> %res
309}
310
311declare <vscale x 2 x i16> @llvm.vp.fshr.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
312define <vscale x 2 x i16> @fshr_v2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, <vscale x 2 x i16> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {
313; CHECK-LABEL: fshr_v2i16:
314; CHECK:       # %bb.0:
315; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
316; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
317; CHECK-NEXT:    vnot.v v11, v10, v0.t
318; CHECK-NEXT:    vand.vi v11, v11, 15, v0.t
319; CHECK-NEXT:    vsll.vv v8, v8, v11, v0.t
320; CHECK-NEXT:    vand.vi v10, v10, 15, v0.t
321; CHECK-NEXT:    vsrl.vv v9, v9, v10, v0.t
322; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
323; CHECK-NEXT:    ret
324  %res = call <vscale x 2 x i16> @llvm.vp.fshr.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, <vscale x 2 x i16> %c, <vscale x 2 x i1> %m, i32 %evl)
325  ret <vscale x 2 x i16> %res
326}
327
328declare <vscale x 2 x i16> @llvm.vp.fshl.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i1>, i32)
329define <vscale x 2 x i16> @fshl_v2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, <vscale x 2 x i16> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {
330; CHECK-LABEL: fshl_v2i16:
331; CHECK:       # %bb.0:
332; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
333; CHECK-NEXT:    vsrl.vi v9, v9, 1, v0.t
334; CHECK-NEXT:    vnot.v v11, v10, v0.t
335; CHECK-NEXT:    vand.vi v11, v11, 15, v0.t
336; CHECK-NEXT:    vsrl.vv v9, v9, v11, v0.t
337; CHECK-NEXT:    vand.vi v10, v10, 15, v0.t
338; CHECK-NEXT:    vsll.vv v8, v8, v10, v0.t
339; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
340; CHECK-NEXT:    ret
341  %res = call <vscale x 2 x i16> @llvm.vp.fshl.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, <vscale x 2 x i16> %c, <vscale x 2 x i1> %m, i32 %evl)
342  ret <vscale x 2 x i16> %res
343}
344
345declare <vscale x 4 x i16> @llvm.vp.fshr.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
346define <vscale x 4 x i16> @fshr_v4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {
347; CHECK-LABEL: fshr_v4i16:
348; CHECK:       # %bb.0:
349; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
350; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
351; CHECK-NEXT:    vnot.v v11, v10, v0.t
352; CHECK-NEXT:    vand.vi v11, v11, 15, v0.t
353; CHECK-NEXT:    vsll.vv v8, v8, v11, v0.t
354; CHECK-NEXT:    vand.vi v10, v10, 15, v0.t
355; CHECK-NEXT:    vsrl.vv v9, v9, v10, v0.t
356; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
357; CHECK-NEXT:    ret
358  %res = call <vscale x 4 x i16> @llvm.vp.fshr.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, <vscale x 4 x i1> %m, i32 %evl)
359  ret <vscale x 4 x i16> %res
360}
361
362declare <vscale x 4 x i16> @llvm.vp.fshl.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i1>, i32)
363define <vscale x 4 x i16> @fshl_v4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {
364; CHECK-LABEL: fshl_v4i16:
365; CHECK:       # %bb.0:
366; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
367; CHECK-NEXT:    vsrl.vi v9, v9, 1, v0.t
368; CHECK-NEXT:    vnot.v v11, v10, v0.t
369; CHECK-NEXT:    vand.vi v11, v11, 15, v0.t
370; CHECK-NEXT:    vsrl.vv v9, v9, v11, v0.t
371; CHECK-NEXT:    vand.vi v10, v10, 15, v0.t
372; CHECK-NEXT:    vsll.vv v8, v8, v10, v0.t
373; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
374; CHECK-NEXT:    ret
375  %res = call <vscale x 4 x i16> @llvm.vp.fshl.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, <vscale x 4 x i1> %m, i32 %evl)
376  ret <vscale x 4 x i16> %res
377}
378
379declare <vscale x 8 x i16> @llvm.vp.fshr.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
380define <vscale x 8 x i16> @fshr_v8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {
381; CHECK-LABEL: fshr_v8i16:
382; CHECK:       # %bb.0:
383; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
384; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
385; CHECK-NEXT:    vnot.v v14, v12, v0.t
386; CHECK-NEXT:    vand.vi v14, v14, 15, v0.t
387; CHECK-NEXT:    vsll.vv v8, v8, v14, v0.t
388; CHECK-NEXT:    vand.vi v12, v12, 15, v0.t
389; CHECK-NEXT:    vsrl.vv v10, v10, v12, v0.t
390; CHECK-NEXT:    vor.vv v8, v8, v10, v0.t
391; CHECK-NEXT:    ret
392  %res = call <vscale x 8 x i16> @llvm.vp.fshr.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i1> %m, i32 %evl)
393  ret <vscale x 8 x i16> %res
394}
395
396declare <vscale x 8 x i16> @llvm.vp.fshl.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, i32)
397define <vscale x 8 x i16> @fshl_v8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {
398; CHECK-LABEL: fshl_v8i16:
399; CHECK:       # %bb.0:
400; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
401; CHECK-NEXT:    vsrl.vi v10, v10, 1, v0.t
402; CHECK-NEXT:    vnot.v v14, v12, v0.t
403; CHECK-NEXT:    vand.vi v14, v14, 15, v0.t
404; CHECK-NEXT:    vsrl.vv v10, v10, v14, v0.t
405; CHECK-NEXT:    vand.vi v12, v12, 15, v0.t
406; CHECK-NEXT:    vsll.vv v8, v8, v12, v0.t
407; CHECK-NEXT:    vor.vv v8, v8, v10, v0.t
408; CHECK-NEXT:    ret
409  %res = call <vscale x 8 x i16> @llvm.vp.fshl.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i1> %m, i32 %evl)
410  ret <vscale x 8 x i16> %res
411}
412
413declare <vscale x 16 x i16> @llvm.vp.fshr.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i1>, i32)
414define <vscale x 16 x i16> @fshr_v16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, <vscale x 16 x i16> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {
415; CHECK-LABEL: fshr_v16i16:
416; CHECK:       # %bb.0:
417; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
418; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
419; CHECK-NEXT:    vnot.v v20, v16, v0.t
420; CHECK-NEXT:    vand.vi v20, v20, 15, v0.t
421; CHECK-NEXT:    vsll.vv v8, v8, v20, v0.t
422; CHECK-NEXT:    vand.vi v16, v16, 15, v0.t
423; CHECK-NEXT:    vsrl.vv v12, v12, v16, v0.t
424; CHECK-NEXT:    vor.vv v8, v8, v12, v0.t
425; CHECK-NEXT:    ret
426  %res = call <vscale x 16 x i16> @llvm.vp.fshr.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, <vscale x 16 x i16> %c, <vscale x 16 x i1> %m, i32 %evl)
427  ret <vscale x 16 x i16> %res
428}
429
430declare <vscale x 16 x i16> @llvm.vp.fshl.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i1>, i32)
431define <vscale x 16 x i16> @fshl_v16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, <vscale x 16 x i16> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {
432; CHECK-LABEL: fshl_v16i16:
433; CHECK:       # %bb.0:
434; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
435; CHECK-NEXT:    vsrl.vi v12, v12, 1, v0.t
436; CHECK-NEXT:    vnot.v v20, v16, v0.t
437; CHECK-NEXT:    vand.vi v20, v20, 15, v0.t
438; CHECK-NEXT:    vsrl.vv v12, v12, v20, v0.t
439; CHECK-NEXT:    vand.vi v16, v16, 15, v0.t
440; CHECK-NEXT:    vsll.vv v8, v8, v16, v0.t
441; CHECK-NEXT:    vor.vv v8, v8, v12, v0.t
442; CHECK-NEXT:    ret
443  %res = call <vscale x 16 x i16> @llvm.vp.fshl.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b, <vscale x 16 x i16> %c, <vscale x 16 x i1> %m, i32 %evl)
444  ret <vscale x 16 x i16> %res
445}
446
447declare <vscale x 32 x i16> @llvm.vp.fshr.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>, <vscale x 32 x i16>, <vscale x 32 x i1>, i32)
448define <vscale x 32 x i16> @fshr_v32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, <vscale x 32 x i16> %c, <vscale x 32 x i1> %m, i32 zeroext %evl) {
449; CHECK-LABEL: fshr_v32i16:
450; CHECK:       # %bb.0:
451; CHECK-NEXT:    addi sp, sp, -16
452; CHECK-NEXT:    .cfi_def_cfa_offset 16
453; CHECK-NEXT:    csrr a2, vlenb
454; CHECK-NEXT:    slli a2, a2, 3
455; CHECK-NEXT:    sub sp, sp, a2
456; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
457; CHECK-NEXT:    addi a2, sp, 16
458; CHECK-NEXT:    vs8r.v v16, (a2) # Unknown-size Folded Spill
459; CHECK-NEXT:    vl8re16.v v24, (a0)
460; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma
461; CHECK-NEXT:    vsll.vi v16, v8, 1, v0.t
462; CHECK-NEXT:    vnot.v v8, v24, v0.t
463; CHECK-NEXT:    vand.vi v8, v8, 15, v0.t
464; CHECK-NEXT:    vsll.vv v8, v16, v8, v0.t
465; CHECK-NEXT:    vand.vi v16, v24, 15, v0.t
466; CHECK-NEXT:    addi a0, sp, 16
467; CHECK-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
468; CHECK-NEXT:    vsrl.vv v16, v24, v16, v0.t
469; CHECK-NEXT:    vor.vv v8, v8, v16, v0.t
470; CHECK-NEXT:    csrr a0, vlenb
471; CHECK-NEXT:    slli a0, a0, 3
472; CHECK-NEXT:    add sp, sp, a0
473; CHECK-NEXT:    .cfi_def_cfa sp, 16
474; CHECK-NEXT:    addi sp, sp, 16
475; CHECK-NEXT:    .cfi_def_cfa_offset 0
476; CHECK-NEXT:    ret
477  %res = call <vscale x 32 x i16> @llvm.vp.fshr.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, <vscale x 32 x i16> %c, <vscale x 32 x i1> %m, i32 %evl)
478  ret <vscale x 32 x i16> %res
479}
480
481declare <vscale x 32 x i16> @llvm.vp.fshl.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>, <vscale x 32 x i16>, <vscale x 32 x i1>, i32)
482define <vscale x 32 x i16> @fshl_v32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, <vscale x 32 x i16> %c, <vscale x 32 x i1> %m, i32 zeroext %evl) {
483; CHECK-LABEL: fshl_v32i16:
484; CHECK:       # %bb.0:
485; CHECK-NEXT:    addi sp, sp, -16
486; CHECK-NEXT:    .cfi_def_cfa_offset 16
487; CHECK-NEXT:    csrr a2, vlenb
488; CHECK-NEXT:    slli a2, a2, 3
489; CHECK-NEXT:    sub sp, sp, a2
490; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
491; CHECK-NEXT:    addi a2, sp, 16
492; CHECK-NEXT:    vs8r.v v8, (a2) # Unknown-size Folded Spill
493; CHECK-NEXT:    vl8re16.v v24, (a0)
494; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma
495; CHECK-NEXT:    vsrl.vi v16, v16, 1, v0.t
496; CHECK-NEXT:    vnot.v v8, v24, v0.t
497; CHECK-NEXT:    vand.vi v8, v8, 15, v0.t
498; CHECK-NEXT:    vsrl.vv v8, v16, v8, v0.t
499; CHECK-NEXT:    vand.vi v16, v24, 15, v0.t
500; CHECK-NEXT:    addi a0, sp, 16
501; CHECK-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
502; CHECK-NEXT:    vsll.vv v16, v24, v16, v0.t
503; CHECK-NEXT:    vor.vv v8, v16, v8, v0.t
504; CHECK-NEXT:    csrr a0, vlenb
505; CHECK-NEXT:    slli a0, a0, 3
506; CHECK-NEXT:    add sp, sp, a0
507; CHECK-NEXT:    .cfi_def_cfa sp, 16
508; CHECK-NEXT:    addi sp, sp, 16
509; CHECK-NEXT:    .cfi_def_cfa_offset 0
510; CHECK-NEXT:    ret
511  %res = call <vscale x 32 x i16> @llvm.vp.fshl.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b, <vscale x 32 x i16> %c, <vscale x 32 x i1> %m, i32 %evl)
512  ret <vscale x 32 x i16> %res
513}
514
515declare <vscale x 1 x i32> @llvm.vp.fshr.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
516define <vscale x 1 x i32> @fshr_v1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
517; CHECK-LABEL: fshr_v1i32:
518; CHECK:       # %bb.0:
519; CHECK-NEXT:    li a1, 31
520; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
521; CHECK-NEXT:    vand.vx v11, v10, a1, v0.t
522; CHECK-NEXT:    vsrl.vv v9, v9, v11, v0.t
523; CHECK-NEXT:    vnot.v v10, v10, v0.t
524; CHECK-NEXT:    vand.vx v10, v10, a1, v0.t
525; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
526; CHECK-NEXT:    vsll.vv v8, v8, v10, v0.t
527; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
528; CHECK-NEXT:    ret
529  %res = call <vscale x 1 x i32> @llvm.vp.fshr.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c, <vscale x 1 x i1> %m, i32 %evl)
530  ret <vscale x 1 x i32> %res
531}
532
533declare <vscale x 1 x i32> @llvm.vp.fshl.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i32)
534define <vscale x 1 x i32> @fshl_v1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
535; CHECK-LABEL: fshl_v1i32:
536; CHECK:       # %bb.0:
537; CHECK-NEXT:    li a1, 31
538; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
539; CHECK-NEXT:    vand.vx v11, v10, a1, v0.t
540; CHECK-NEXT:    vsll.vv v8, v8, v11, v0.t
541; CHECK-NEXT:    vnot.v v10, v10, v0.t
542; CHECK-NEXT:    vand.vx v10, v10, a1, v0.t
543; CHECK-NEXT:    vsrl.vi v9, v9, 1, v0.t
544; CHECK-NEXT:    vsrl.vv v9, v9, v10, v0.t
545; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
546; CHECK-NEXT:    ret
547  %res = call <vscale x 1 x i32> @llvm.vp.fshl.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c, <vscale x 1 x i1> %m, i32 %evl)
548  ret <vscale x 1 x i32> %res
549}
550
551declare <vscale x 2 x i32> @llvm.vp.fshr.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
552define <vscale x 2 x i32> @fshr_v2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {
553; CHECK-LABEL: fshr_v2i32:
554; CHECK:       # %bb.0:
555; CHECK-NEXT:    li a1, 31
556; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
557; CHECK-NEXT:    vand.vx v11, v10, a1, v0.t
558; CHECK-NEXT:    vsrl.vv v9, v9, v11, v0.t
559; CHECK-NEXT:    vnot.v v10, v10, v0.t
560; CHECK-NEXT:    vand.vx v10, v10, a1, v0.t
561; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
562; CHECK-NEXT:    vsll.vv v8, v8, v10, v0.t
563; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
564; CHECK-NEXT:    ret
565  %res = call <vscale x 2 x i32> @llvm.vp.fshr.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i1> %m, i32 %evl)
566  ret <vscale x 2 x i32> %res
567}
568
569declare <vscale x 2 x i32> @llvm.vp.fshl.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i32)
570define <vscale x 2 x i32> @fshl_v2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {
571; CHECK-LABEL: fshl_v2i32:
572; CHECK:       # %bb.0:
573; CHECK-NEXT:    li a1, 31
574; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
575; CHECK-NEXT:    vand.vx v11, v10, a1, v0.t
576; CHECK-NEXT:    vsll.vv v8, v8, v11, v0.t
577; CHECK-NEXT:    vnot.v v10, v10, v0.t
578; CHECK-NEXT:    vand.vx v10, v10, a1, v0.t
579; CHECK-NEXT:    vsrl.vi v9, v9, 1, v0.t
580; CHECK-NEXT:    vsrl.vv v9, v9, v10, v0.t
581; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
582; CHECK-NEXT:    ret
583  %res = call <vscale x 2 x i32> @llvm.vp.fshl.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i1> %m, i32 %evl)
584  ret <vscale x 2 x i32> %res
585}
586
587declare <vscale x 4 x i32> @llvm.vp.fshr.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
588define <vscale x 4 x i32> @fshr_v4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {
589; CHECK-LABEL: fshr_v4i32:
590; CHECK:       # %bb.0:
591; CHECK-NEXT:    li a1, 31
592; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
593; CHECK-NEXT:    vand.vx v14, v12, a1, v0.t
594; CHECK-NEXT:    vsrl.vv v10, v10, v14, v0.t
595; CHECK-NEXT:    vnot.v v12, v12, v0.t
596; CHECK-NEXT:    vand.vx v12, v12, a1, v0.t
597; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
598; CHECK-NEXT:    vsll.vv v8, v8, v12, v0.t
599; CHECK-NEXT:    vor.vv v8, v8, v10, v0.t
600; CHECK-NEXT:    ret
601  %res = call <vscale x 4 x i32> @llvm.vp.fshr.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i1> %m, i32 %evl)
602  ret <vscale x 4 x i32> %res
603}
604
605declare <vscale x 4 x i32> @llvm.vp.fshl.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
606define <vscale x 4 x i32> @fshl_v4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {
607; CHECK-LABEL: fshl_v4i32:
608; CHECK:       # %bb.0:
609; CHECK-NEXT:    li a1, 31
610; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
611; CHECK-NEXT:    vand.vx v14, v12, a1, v0.t
612; CHECK-NEXT:    vsll.vv v8, v8, v14, v0.t
613; CHECK-NEXT:    vnot.v v12, v12, v0.t
614; CHECK-NEXT:    vand.vx v12, v12, a1, v0.t
615; CHECK-NEXT:    vsrl.vi v10, v10, 1, v0.t
616; CHECK-NEXT:    vsrl.vv v10, v10, v12, v0.t
617; CHECK-NEXT:    vor.vv v8, v8, v10, v0.t
618; CHECK-NEXT:    ret
619  %res = call <vscale x 4 x i32> @llvm.vp.fshl.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i1> %m, i32 %evl)
620  ret <vscale x 4 x i32> %res
621}
622
623declare <vscale x 8 x i32> @llvm.vp.fshr.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
624define <vscale x 8 x i32> @fshr_v8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, <vscale x 8 x i32> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {
625; CHECK-LABEL: fshr_v8i32:
626; CHECK:       # %bb.0:
627; CHECK-NEXT:    li a1, 31
628; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
629; CHECK-NEXT:    vand.vx v20, v16, a1, v0.t
630; CHECK-NEXT:    vsrl.vv v12, v12, v20, v0.t
631; CHECK-NEXT:    vnot.v v16, v16, v0.t
632; CHECK-NEXT:    vand.vx v16, v16, a1, v0.t
633; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
634; CHECK-NEXT:    vsll.vv v8, v8, v16, v0.t
635; CHECK-NEXT:    vor.vv v8, v8, v12, v0.t
636; CHECK-NEXT:    ret
637  %res = call <vscale x 8 x i32> @llvm.vp.fshr.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, <vscale x 8 x i32> %c, <vscale x 8 x i1> %m, i32 %evl)
638  ret <vscale x 8 x i32> %res
639}
640
641declare <vscale x 8 x i32> @llvm.vp.fshl.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i1>, i32)
642define <vscale x 8 x i32> @fshl_v8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, <vscale x 8 x i32> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {
643; CHECK-LABEL: fshl_v8i32:
644; CHECK:       # %bb.0:
645; CHECK-NEXT:    li a1, 31
646; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
647; CHECK-NEXT:    vand.vx v20, v16, a1, v0.t
648; CHECK-NEXT:    vsll.vv v8, v8, v20, v0.t
649; CHECK-NEXT:    vnot.v v16, v16, v0.t
650; CHECK-NEXT:    vand.vx v16, v16, a1, v0.t
651; CHECK-NEXT:    vsrl.vi v12, v12, 1, v0.t
652; CHECK-NEXT:    vsrl.vv v12, v12, v16, v0.t
653; CHECK-NEXT:    vor.vv v8, v8, v12, v0.t
654; CHECK-NEXT:    ret
655  %res = call <vscale x 8 x i32> @llvm.vp.fshl.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, <vscale x 8 x i32> %c, <vscale x 8 x i1> %m, i32 %evl)
656  ret <vscale x 8 x i32> %res
657}
658
659declare <vscale x 16 x i32> @llvm.vp.fshr.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i1>, i32)
660define <vscale x 16 x i32> @fshr_v16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, <vscale x 16 x i32> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {
661; CHECK-LABEL: fshr_v16i32:
662; CHECK:       # %bb.0:
663; CHECK-NEXT:    addi sp, sp, -16
664; CHECK-NEXT:    .cfi_def_cfa_offset 16
665; CHECK-NEXT:    csrr a2, vlenb
666; CHECK-NEXT:    slli a2, a2, 3
667; CHECK-NEXT:    sub sp, sp, a2
668; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
669; CHECK-NEXT:    addi a2, sp, 16
670; CHECK-NEXT:    vs8r.v v8, (a2) # Unknown-size Folded Spill
671; CHECK-NEXT:    vl8re32.v v24, (a0)
672; CHECK-NEXT:    li a0, 31
673; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma
674; CHECK-NEXT:    vand.vx v8, v24, a0, v0.t
675; CHECK-NEXT:    vsrl.vv v16, v16, v8, v0.t
676; CHECK-NEXT:    vnot.v v8, v24, v0.t
677; CHECK-NEXT:    vand.vx v8, v8, a0, v0.t
678; CHECK-NEXT:    addi a0, sp, 16
679; CHECK-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
680; CHECK-NEXT:    vsll.vi v24, v24, 1, v0.t
681; CHECK-NEXT:    vsll.vv v8, v24, v8, v0.t
682; CHECK-NEXT:    vor.vv v8, v8, v16, v0.t
683; CHECK-NEXT:    csrr a0, vlenb
684; CHECK-NEXT:    slli a0, a0, 3
685; CHECK-NEXT:    add sp, sp, a0
686; CHECK-NEXT:    .cfi_def_cfa sp, 16
687; CHECK-NEXT:    addi sp, sp, 16
688; CHECK-NEXT:    .cfi_def_cfa_offset 0
689; CHECK-NEXT:    ret
690  %res = call <vscale x 16 x i32> @llvm.vp.fshr.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, <vscale x 16 x i32> %c, <vscale x 16 x i1> %m, i32 %evl)
691  ret <vscale x 16 x i32> %res
692}
693
694declare <vscale x 16 x i32> @llvm.vp.fshl.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i1>, i32)
695define <vscale x 16 x i32> @fshl_v16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, <vscale x 16 x i32> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {
696; CHECK-LABEL: fshl_v16i32:
697; CHECK:       # %bb.0:
698; CHECK-NEXT:    addi sp, sp, -16
699; CHECK-NEXT:    .cfi_def_cfa_offset 16
700; CHECK-NEXT:    csrr a2, vlenb
701; CHECK-NEXT:    slli a2, a2, 3
702; CHECK-NEXT:    sub sp, sp, a2
703; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
704; CHECK-NEXT:    addi a2, sp, 16
705; CHECK-NEXT:    vs8r.v v16, (a2) # Unknown-size Folded Spill
706; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma
707; CHECK-NEXT:    vmv8r.v v16, v8
708; CHECK-NEXT:    vl8re32.v v24, (a0)
709; CHECK-NEXT:    li a0, 31
710; CHECK-NEXT:    vand.vx v8, v24, a0, v0.t
711; CHECK-NEXT:    vsll.vv v8, v16, v8, v0.t
712; CHECK-NEXT:    vnot.v v16, v24, v0.t
713; CHECK-NEXT:    vand.vx v16, v16, a0, v0.t
714; CHECK-NEXT:    addi a0, sp, 16
715; CHECK-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
716; CHECK-NEXT:    vsrl.vi v24, v24, 1, v0.t
717; CHECK-NEXT:    vsrl.vv v16, v24, v16, v0.t
718; CHECK-NEXT:    vor.vv v8, v8, v16, v0.t
719; CHECK-NEXT:    csrr a0, vlenb
720; CHECK-NEXT:    slli a0, a0, 3
721; CHECK-NEXT:    add sp, sp, a0
722; CHECK-NEXT:    .cfi_def_cfa sp, 16
723; CHECK-NEXT:    addi sp, sp, 16
724; CHECK-NEXT:    .cfi_def_cfa_offset 0
725; CHECK-NEXT:    ret
726  %res = call <vscale x 16 x i32> @llvm.vp.fshl.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b, <vscale x 16 x i32> %c, <vscale x 16 x i1> %m, i32 %evl)
727  ret <vscale x 16 x i32> %res
728}
729
730declare <vscale x 1 x i64> @llvm.vp.fshr.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i32)
731define <vscale x 1 x i64> @fshr_v1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, <vscale x 1 x i64> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
732; CHECK-LABEL: fshr_v1i64:
733; CHECK:       # %bb.0:
734; CHECK-NEXT:    li a1, 63
735; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
736; CHECK-NEXT:    vand.vx v11, v10, a1, v0.t
737; CHECK-NEXT:    vsrl.vv v9, v9, v11, v0.t
738; CHECK-NEXT:    vnot.v v10, v10, v0.t
739; CHECK-NEXT:    vand.vx v10, v10, a1, v0.t
740; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
741; CHECK-NEXT:    vsll.vv v8, v8, v10, v0.t
742; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
743; CHECK-NEXT:    ret
744  %res = call <vscale x 1 x i64> @llvm.vp.fshr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, <vscale x 1 x i64> %c, <vscale x 1 x i1> %m, i32 %evl)
745  ret <vscale x 1 x i64> %res
746}
747
748declare <vscale x 1 x i64> @llvm.vp.fshl.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i32)
749define <vscale x 1 x i64> @fshl_v1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, <vscale x 1 x i64> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
750; CHECK-LABEL: fshl_v1i64:
751; CHECK:       # %bb.0:
752; CHECK-NEXT:    li a1, 63
753; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
754; CHECK-NEXT:    vand.vx v11, v10, a1, v0.t
755; CHECK-NEXT:    vsll.vv v8, v8, v11, v0.t
756; CHECK-NEXT:    vnot.v v10, v10, v0.t
757; CHECK-NEXT:    vand.vx v10, v10, a1, v0.t
758; CHECK-NEXT:    vsrl.vi v9, v9, 1, v0.t
759; CHECK-NEXT:    vsrl.vv v9, v9, v10, v0.t
760; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
761; CHECK-NEXT:    ret
762  %res = call <vscale x 1 x i64> @llvm.vp.fshl.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, <vscale x 1 x i64> %c, <vscale x 1 x i1> %m, i32 %evl)
763  ret <vscale x 1 x i64> %res
764}
765
766declare <vscale x 2 x i64> @llvm.vp.fshr.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, i32)
767define <vscale x 2 x i64> @fshr_v2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {
768; CHECK-LABEL: fshr_v2i64:
769; CHECK:       # %bb.0:
770; CHECK-NEXT:    li a1, 63
771; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
772; CHECK-NEXT:    vand.vx v14, v12, a1, v0.t
773; CHECK-NEXT:    vsrl.vv v10, v10, v14, v0.t
774; CHECK-NEXT:    vnot.v v12, v12, v0.t
775; CHECK-NEXT:    vand.vx v12, v12, a1, v0.t
776; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
777; CHECK-NEXT:    vsll.vv v8, v8, v12, v0.t
778; CHECK-NEXT:    vor.vv v8, v8, v10, v0.t
779; CHECK-NEXT:    ret
780  %res = call <vscale x 2 x i64> @llvm.vp.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i1> %m, i32 %evl)
781  ret <vscale x 2 x i64> %res
782}
783
784declare <vscale x 2 x i64> @llvm.vp.fshl.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, i32)
785define <vscale x 2 x i64> @fshl_v2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {
786; CHECK-LABEL: fshl_v2i64:
787; CHECK:       # %bb.0:
788; CHECK-NEXT:    li a1, 63
789; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
790; CHECK-NEXT:    vand.vx v14, v12, a1, v0.t
791; CHECK-NEXT:    vsll.vv v8, v8, v14, v0.t
792; CHECK-NEXT:    vnot.v v12, v12, v0.t
793; CHECK-NEXT:    vand.vx v12, v12, a1, v0.t
794; CHECK-NEXT:    vsrl.vi v10, v10, 1, v0.t
795; CHECK-NEXT:    vsrl.vv v10, v10, v12, v0.t
796; CHECK-NEXT:    vor.vv v8, v8, v10, v0.t
797; CHECK-NEXT:    ret
798  %res = call <vscale x 2 x i64> @llvm.vp.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i1> %m, i32 %evl)
799  ret <vscale x 2 x i64> %res
800}
801
802declare <vscale x 4 x i64> @llvm.vp.fshr.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i1>, i32)
803define <vscale x 4 x i64> @fshr_v4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {
804; CHECK-LABEL: fshr_v4i64:
805; CHECK:       # %bb.0:
806; CHECK-NEXT:    li a1, 63
807; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
808; CHECK-NEXT:    vand.vx v20, v16, a1, v0.t
809; CHECK-NEXT:    vsrl.vv v12, v12, v20, v0.t
810; CHECK-NEXT:    vnot.v v16, v16, v0.t
811; CHECK-NEXT:    vand.vx v16, v16, a1, v0.t
812; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
813; CHECK-NEXT:    vsll.vv v8, v8, v16, v0.t
814; CHECK-NEXT:    vor.vv v8, v8, v12, v0.t
815; CHECK-NEXT:    ret
816  %res = call <vscale x 4 x i64> @llvm.vp.fshr.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c, <vscale x 4 x i1> %m, i32 %evl)
817  ret <vscale x 4 x i64> %res
818}
819
820declare <vscale x 4 x i64> @llvm.vp.fshl.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i1>, i32)
821define <vscale x 4 x i64> @fshl_v4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {
822; CHECK-LABEL: fshl_v4i64:
823; CHECK:       # %bb.0:
824; CHECK-NEXT:    li a1, 63
825; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
826; CHECK-NEXT:    vand.vx v20, v16, a1, v0.t
827; CHECK-NEXT:    vsll.vv v8, v8, v20, v0.t
828; CHECK-NEXT:    vnot.v v16, v16, v0.t
829; CHECK-NEXT:    vand.vx v16, v16, a1, v0.t
830; CHECK-NEXT:    vsrl.vi v12, v12, 1, v0.t
831; CHECK-NEXT:    vsrl.vv v12, v12, v16, v0.t
832; CHECK-NEXT:    vor.vv v8, v8, v12, v0.t
833; CHECK-NEXT:    ret
834  %res = call <vscale x 4 x i64> @llvm.vp.fshl.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c, <vscale x 4 x i1> %m, i32 %evl)
835  ret <vscale x 4 x i64> %res
836}
837
838declare <vscale x 7 x i64> @llvm.vp.fshr.nxv7i64(<vscale x 7 x i64>, <vscale x 7 x i64>, <vscale x 7 x i64>, <vscale x 7 x i1>, i32)
839define <vscale x 7 x i64> @fshr_v7i64(<vscale x 7 x i64> %a, <vscale x 7 x i64> %b, <vscale x 7 x i64> %c, <vscale x 7 x i1> %m, i32 zeroext %evl) {
840; CHECK-LABEL: fshr_v7i64:
841; CHECK:       # %bb.0:
842; CHECK-NEXT:    addi sp, sp, -16
843; CHECK-NEXT:    .cfi_def_cfa_offset 16
844; CHECK-NEXT:    csrr a2, vlenb
845; CHECK-NEXT:    slli a2, a2, 3
846; CHECK-NEXT:    sub sp, sp, a2
847; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
848; CHECK-NEXT:    addi a2, sp, 16
849; CHECK-NEXT:    vs8r.v v8, (a2) # Unknown-size Folded Spill
850; CHECK-NEXT:    vl8re64.v v24, (a0)
851; CHECK-NEXT:    li a0, 63
852; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
853; CHECK-NEXT:    vand.vx v8, v24, a0, v0.t
854; CHECK-NEXT:    vsrl.vv v16, v16, v8, v0.t
855; CHECK-NEXT:    vnot.v v8, v24, v0.t
856; CHECK-NEXT:    vand.vx v8, v8, a0, v0.t
857; CHECK-NEXT:    addi a0, sp, 16
858; CHECK-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
859; CHECK-NEXT:    vsll.vi v24, v24, 1, v0.t
860; CHECK-NEXT:    vsll.vv v8, v24, v8, v0.t
861; CHECK-NEXT:    vor.vv v8, v8, v16, v0.t
862; CHECK-NEXT:    csrr a0, vlenb
863; CHECK-NEXT:    slli a0, a0, 3
864; CHECK-NEXT:    add sp, sp, a0
865; CHECK-NEXT:    .cfi_def_cfa sp, 16
866; CHECK-NEXT:    addi sp, sp, 16
867; CHECK-NEXT:    .cfi_def_cfa_offset 0
868; CHECK-NEXT:    ret
869  %res = call <vscale x 7 x i64> @llvm.vp.fshr.nxv7i64(<vscale x 7 x i64> %a, <vscale x 7 x i64> %b, <vscale x 7 x i64> %c, <vscale x 7 x i1> %m, i32 %evl)
870  ret <vscale x 7 x i64> %res
871}
872
873declare <vscale x 7 x i64> @llvm.vp.fshl.nxv7i64(<vscale x 7 x i64>, <vscale x 7 x i64>, <vscale x 7 x i64>, <vscale x 7 x i1>, i32)
874define <vscale x 7 x i64> @fshl_v7i64(<vscale x 7 x i64> %a, <vscale x 7 x i64> %b, <vscale x 7 x i64> %c, <vscale x 7 x i1> %m, i32 zeroext %evl) {
875; CHECK-LABEL: fshl_v7i64:
876; CHECK:       # %bb.0:
877; CHECK-NEXT:    addi sp, sp, -16
878; CHECK-NEXT:    .cfi_def_cfa_offset 16
879; CHECK-NEXT:    csrr a2, vlenb
880; CHECK-NEXT:    slli a2, a2, 3
881; CHECK-NEXT:    sub sp, sp, a2
882; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
883; CHECK-NEXT:    addi a2, sp, 16
884; CHECK-NEXT:    vs8r.v v16, (a2) # Unknown-size Folded Spill
885; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
886; CHECK-NEXT:    vmv8r.v v16, v8
887; CHECK-NEXT:    vl8re64.v v24, (a0)
888; CHECK-NEXT:    li a0, 63
889; CHECK-NEXT:    vand.vx v8, v24, a0, v0.t
890; CHECK-NEXT:    vsll.vv v8, v16, v8, v0.t
891; CHECK-NEXT:    vnot.v v16, v24, v0.t
892; CHECK-NEXT:    vand.vx v16, v16, a0, v0.t
893; CHECK-NEXT:    addi a0, sp, 16
894; CHECK-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
895; CHECK-NEXT:    vsrl.vi v24, v24, 1, v0.t
896; CHECK-NEXT:    vsrl.vv v16, v24, v16, v0.t
897; CHECK-NEXT:    vor.vv v8, v8, v16, v0.t
898; CHECK-NEXT:    csrr a0, vlenb
899; CHECK-NEXT:    slli a0, a0, 3
900; CHECK-NEXT:    add sp, sp, a0
901; CHECK-NEXT:    .cfi_def_cfa sp, 16
902; CHECK-NEXT:    addi sp, sp, 16
903; CHECK-NEXT:    .cfi_def_cfa_offset 0
904; CHECK-NEXT:    ret
905  %res = call <vscale x 7 x i64> @llvm.vp.fshl.nxv7i64(<vscale x 7 x i64> %a, <vscale x 7 x i64> %b, <vscale x 7 x i64> %c, <vscale x 7 x i1> %m, i32 %evl)
906  ret <vscale x 7 x i64> %res
907}
908
909declare <vscale x 8 x i64> @llvm.vp.fshr.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i1>, i32)
910define <vscale x 8 x i64> @fshr_v8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, <vscale x 8 x i64> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {
911; CHECK-LABEL: fshr_v8i64:
912; CHECK:       # %bb.0:
913; CHECK-NEXT:    addi sp, sp, -16
914; CHECK-NEXT:    .cfi_def_cfa_offset 16
915; CHECK-NEXT:    csrr a2, vlenb
916; CHECK-NEXT:    slli a2, a2, 3
917; CHECK-NEXT:    sub sp, sp, a2
918; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
919; CHECK-NEXT:    addi a2, sp, 16
920; CHECK-NEXT:    vs8r.v v8, (a2) # Unknown-size Folded Spill
921; CHECK-NEXT:    vl8re64.v v24, (a0)
922; CHECK-NEXT:    li a0, 63
923; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
924; CHECK-NEXT:    vand.vx v8, v24, a0, v0.t
925; CHECK-NEXT:    vsrl.vv v16, v16, v8, v0.t
926; CHECK-NEXT:    vnot.v v8, v24, v0.t
927; CHECK-NEXT:    vand.vx v8, v8, a0, v0.t
928; CHECK-NEXT:    addi a0, sp, 16
929; CHECK-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
930; CHECK-NEXT:    vsll.vi v24, v24, 1, v0.t
931; CHECK-NEXT:    vsll.vv v8, v24, v8, v0.t
932; CHECK-NEXT:    vor.vv v8, v8, v16, v0.t
933; CHECK-NEXT:    csrr a0, vlenb
934; CHECK-NEXT:    slli a0, a0, 3
935; CHECK-NEXT:    add sp, sp, a0
936; CHECK-NEXT:    .cfi_def_cfa sp, 16
937; CHECK-NEXT:    addi sp, sp, 16
938; CHECK-NEXT:    .cfi_def_cfa_offset 0
939; CHECK-NEXT:    ret
940  %res = call <vscale x 8 x i64> @llvm.vp.fshr.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, <vscale x 8 x i64> %c, <vscale x 8 x i1> %m, i32 %evl)
941  ret <vscale x 8 x i64> %res
942}
943
944declare <vscale x 8 x i64> @llvm.vp.fshl.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i1>, i32)
945define <vscale x 8 x i64> @fshl_v8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, <vscale x 8 x i64> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {
946; CHECK-LABEL: fshl_v8i64:
947; CHECK:       # %bb.0:
948; CHECK-NEXT:    addi sp, sp, -16
949; CHECK-NEXT:    .cfi_def_cfa_offset 16
950; CHECK-NEXT:    csrr a2, vlenb
951; CHECK-NEXT:    slli a2, a2, 3
952; CHECK-NEXT:    sub sp, sp, a2
953; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
954; CHECK-NEXT:    addi a2, sp, 16
955; CHECK-NEXT:    vs8r.v v16, (a2) # Unknown-size Folded Spill
956; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
957; CHECK-NEXT:    vmv8r.v v16, v8
958; CHECK-NEXT:    vl8re64.v v24, (a0)
959; CHECK-NEXT:    li a0, 63
960; CHECK-NEXT:    vand.vx v8, v24, a0, v0.t
961; CHECK-NEXT:    vsll.vv v8, v16, v8, v0.t
962; CHECK-NEXT:    vnot.v v16, v24, v0.t
963; CHECK-NEXT:    vand.vx v16, v16, a0, v0.t
964; CHECK-NEXT:    addi a0, sp, 16
965; CHECK-NEXT:    vl8r.v v24, (a0) # Unknown-size Folded Reload
966; CHECK-NEXT:    vsrl.vi v24, v24, 1, v0.t
967; CHECK-NEXT:    vsrl.vv v16, v24, v16, v0.t
968; CHECK-NEXT:    vor.vv v8, v8, v16, v0.t
969; CHECK-NEXT:    csrr a0, vlenb
970; CHECK-NEXT:    slli a0, a0, 3
971; CHECK-NEXT:    add sp, sp, a0
972; CHECK-NEXT:    .cfi_def_cfa sp, 16
973; CHECK-NEXT:    addi sp, sp, 16
974; CHECK-NEXT:    .cfi_def_cfa_offset 0
975; CHECK-NEXT:    ret
976  %res = call <vscale x 8 x i64> @llvm.vp.fshl.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b, <vscale x 8 x i64> %c, <vscale x 8 x i1> %m, i32 %evl)
977  ret <vscale x 8 x i64> %res
978}
979
980declare <vscale x 16 x i64> @llvm.vp.fshr.nxv16i64(<vscale x 16 x i64>, <vscale x 16 x i64>, <vscale x 16 x i64>, <vscale x 16 x i1>, i32)
981define <vscale x 16 x i64> @fshr_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i64> %b, <vscale x 16 x i64> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {
982; CHECK-LABEL: fshr_v16i64:
983; CHECK:       # %bb.0:
984; CHECK-NEXT:    addi sp, sp, -16
985; CHECK-NEXT:    .cfi_def_cfa_offset 16
986; CHECK-NEXT:    csrr a1, vlenb
987; CHECK-NEXT:    li a3, 48
988; CHECK-NEXT:    mul a1, a1, a3
989; CHECK-NEXT:    sub sp, sp, a1
990; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb
991; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
992; CHECK-NEXT:    vmv1r.v v24, v0
993; CHECK-NEXT:    csrr a1, vlenb
994; CHECK-NEXT:    li a3, 24
995; CHECK-NEXT:    mul a1, a1, a3
996; CHECK-NEXT:    add a1, sp, a1
997; CHECK-NEXT:    addi a1, a1, 16
998; CHECK-NEXT:    vs8r.v v16, (a1) # Unknown-size Folded Spill
999; CHECK-NEXT:    csrr a1, vlenb
1000; CHECK-NEXT:    slli a1, a1, 5
1001; CHECK-NEXT:    add a1, sp, a1
1002; CHECK-NEXT:    addi a1, a1, 16
1003; CHECK-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
1004; CHECK-NEXT:    csrr a1, vlenb
1005; CHECK-NEXT:    slli a3, a1, 3
1006; CHECK-NEXT:    sub a5, a4, a1
1007; CHECK-NEXT:    add a6, a2, a3
1008; CHECK-NEXT:    vl8re64.v v8, (a6)
1009; CHECK-NEXT:    csrr a6, vlenb
1010; CHECK-NEXT:    li a7, 40
1011; CHECK-NEXT:    mul a6, a6, a7
1012; CHECK-NEXT:    add a6, sp, a6
1013; CHECK-NEXT:    addi a6, a6, 16
1014; CHECK-NEXT:    vs8r.v v8, (a6) # Unknown-size Folded Spill
1015; CHECK-NEXT:    sltu a6, a4, a5
1016; CHECK-NEXT:    addi a6, a6, -1
1017; CHECK-NEXT:    and a5, a6, a5
1018; CHECK-NEXT:    srli a6, a1, 3
1019; CHECK-NEXT:    add a3, a0, a3
1020; CHECK-NEXT:    vl8re64.v v16, (a3)
1021; CHECK-NEXT:    csrr a3, vlenb
1022; CHECK-NEXT:    slli a3, a3, 4
1023; CHECK-NEXT:    add a3, sp, a3
1024; CHECK-NEXT:    addi a3, a3, 16
1025; CHECK-NEXT:    vs8r.v v16, (a3) # Unknown-size Folded Spill
1026; CHECK-NEXT:    vslidedown.vx v0, v0, a6
1027; CHECK-NEXT:    li a3, 63
1028; CHECK-NEXT:    csrr a6, vlenb
1029; CHECK-NEXT:    li a7, 40
1030; CHECK-NEXT:    mul a6, a6, a7
1031; CHECK-NEXT:    add a6, sp, a6
1032; CHECK-NEXT:    addi a6, a6, 16
1033; CHECK-NEXT:    vl8r.v v8, (a6) # Unknown-size Folded Reload
1034; CHECK-NEXT:    vsetvli zero, a5, e64, m8, ta, ma
1035; CHECK-NEXT:    vand.vx v8, v8, a3, v0.t
1036; CHECK-NEXT:    csrr a5, vlenb
1037; CHECK-NEXT:    slli a5, a5, 3
1038; CHECK-NEXT:    add a5, sp, a5
1039; CHECK-NEXT:    addi a5, a5, 16
1040; CHECK-NEXT:    vs8r.v v8, (a5) # Unknown-size Folded Spill
1041; CHECK-NEXT:    csrr a5, vlenb
1042; CHECK-NEXT:    slli a5, a5, 4
1043; CHECK-NEXT:    add a5, sp, a5
1044; CHECK-NEXT:    addi a5, a5, 16
1045; CHECK-NEXT:    vl8r.v v16, (a5) # Unknown-size Folded Reload
1046; CHECK-NEXT:    csrr a5, vlenb
1047; CHECK-NEXT:    slli a5, a5, 3
1048; CHECK-NEXT:    add a5, sp, a5
1049; CHECK-NEXT:    addi a5, a5, 16
1050; CHECK-NEXT:    vl8r.v v8, (a5) # Unknown-size Folded Reload
1051; CHECK-NEXT:    vsrl.vv v16, v16, v8, v0.t
1052; CHECK-NEXT:    csrr a5, vlenb
1053; CHECK-NEXT:    slli a5, a5, 3
1054; CHECK-NEXT:    add a5, sp, a5
1055; CHECK-NEXT:    addi a5, a5, 16
1056; CHECK-NEXT:    vs8r.v v16, (a5) # Unknown-size Folded Spill
1057; CHECK-NEXT:    csrr a5, vlenb
1058; CHECK-NEXT:    li a6, 40
1059; CHECK-NEXT:    mul a5, a5, a6
1060; CHECK-NEXT:    add a5, sp, a5
1061; CHECK-NEXT:    addi a5, a5, 16
1062; CHECK-NEXT:    vl8r.v v8, (a5) # Unknown-size Folded Reload
1063; CHECK-NEXT:    vnot.v v8, v8, v0.t
1064; CHECK-NEXT:    vand.vx v8, v8, a3, v0.t
1065; CHECK-NEXT:    addi a5, sp, 16
1066; CHECK-NEXT:    vs8r.v v8, (a5) # Unknown-size Folded Spill
1067; CHECK-NEXT:    vl8re64.v v8, (a0)
1068; CHECK-NEXT:    csrr a0, vlenb
1069; CHECK-NEXT:    slli a0, a0, 4
1070; CHECK-NEXT:    add a0, sp, a0
1071; CHECK-NEXT:    addi a0, a0, 16
1072; CHECK-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
1073; CHECK-NEXT:    vl8re64.v v8, (a2)
1074; CHECK-NEXT:    csrr a0, vlenb
1075; CHECK-NEXT:    li a2, 40
1076; CHECK-NEXT:    mul a0, a0, a2
1077; CHECK-NEXT:    add a0, sp, a0
1078; CHECK-NEXT:    addi a0, a0, 16
1079; CHECK-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
1080; CHECK-NEXT:    csrr a0, vlenb
1081; CHECK-NEXT:    li a2, 24
1082; CHECK-NEXT:    mul a0, a0, a2
1083; CHECK-NEXT:    add a0, sp, a0
1084; CHECK-NEXT:    addi a0, a0, 16
1085; CHECK-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
1086; CHECK-NEXT:    vsll.vi v16, v8, 1, v0.t
1087; CHECK-NEXT:    addi a0, sp, 16
1088; CHECK-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
1089; CHECK-NEXT:    vsll.vv v16, v16, v8, v0.t
1090; CHECK-NEXT:    csrr a0, vlenb
1091; CHECK-NEXT:    slli a0, a0, 3
1092; CHECK-NEXT:    add a0, sp, a0
1093; CHECK-NEXT:    addi a0, a0, 16
1094; CHECK-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
1095; CHECK-NEXT:    vor.vv v8, v16, v8, v0.t
1096; CHECK-NEXT:    csrr a0, vlenb
1097; CHECK-NEXT:    li a2, 24
1098; CHECK-NEXT:    mul a0, a0, a2
1099; CHECK-NEXT:    add a0, sp, a0
1100; CHECK-NEXT:    addi a0, a0, 16
1101; CHECK-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
1102; CHECK-NEXT:    bltu a4, a1, .LBB46_2
1103; CHECK-NEXT:  # %bb.1:
1104; CHECK-NEXT:    mv a4, a1
1105; CHECK-NEXT:  .LBB46_2:
1106; CHECK-NEXT:    vmv1r.v v0, v24
1107; CHECK-NEXT:    csrr a0, vlenb
1108; CHECK-NEXT:    li a1, 40
1109; CHECK-NEXT:    mul a0, a0, a1
1110; CHECK-NEXT:    add a0, sp, a0
1111; CHECK-NEXT:    addi a0, a0, 16
1112; CHECK-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
1113; CHECK-NEXT:    vsetvli zero, a4, e64, m8, ta, ma
1114; CHECK-NEXT:    vand.vx v8, v16, a3, v0.t
1115; CHECK-NEXT:    csrr a0, vlenb
1116; CHECK-NEXT:    slli a0, a0, 4
1117; CHECK-NEXT:    add a0, sp, a0
1118; CHECK-NEXT:    addi a0, a0, 16
1119; CHECK-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
1120; CHECK-NEXT:    vsrl.vv v8, v16, v8, v0.t
1121; CHECK-NEXT:    csrr a0, vlenb
1122; CHECK-NEXT:    slli a0, a0, 4
1123; CHECK-NEXT:    add a0, sp, a0
1124; CHECK-NEXT:    addi a0, a0, 16
1125; CHECK-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
1126; CHECK-NEXT:    csrr a0, vlenb
1127; CHECK-NEXT:    li a1, 40
1128; CHECK-NEXT:    mul a0, a0, a1
1129; CHECK-NEXT:    add a0, sp, a0
1130; CHECK-NEXT:    addi a0, a0, 16
1131; CHECK-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
1132; CHECK-NEXT:    vnot.v v16, v8, v0.t
1133; CHECK-NEXT:    vand.vx v16, v16, a3, v0.t
1134; CHECK-NEXT:    csrr a0, vlenb
1135; CHECK-NEXT:    slli a0, a0, 5
1136; CHECK-NEXT:    add a0, sp, a0
1137; CHECK-NEXT:    addi a0, a0, 16
1138; CHECK-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
1139; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
1140; CHECK-NEXT:    vsll.vv v8, v8, v16, v0.t
1141; CHECK-NEXT:    csrr a0, vlenb
1142; CHECK-NEXT:    slli a0, a0, 4
1143; CHECK-NEXT:    add a0, sp, a0
1144; CHECK-NEXT:    addi a0, a0, 16
1145; CHECK-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
1146; CHECK-NEXT:    vor.vv v8, v8, v16, v0.t
1147; CHECK-NEXT:    csrr a0, vlenb
1148; CHECK-NEXT:    li a1, 24
1149; CHECK-NEXT:    mul a0, a0, a1
1150; CHECK-NEXT:    add a0, sp, a0
1151; CHECK-NEXT:    addi a0, a0, 16
1152; CHECK-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
1153; CHECK-NEXT:    csrr a0, vlenb
1154; CHECK-NEXT:    li a1, 48
1155; CHECK-NEXT:    mul a0, a0, a1
1156; CHECK-NEXT:    add sp, sp, a0
1157; CHECK-NEXT:    .cfi_def_cfa sp, 16
1158; CHECK-NEXT:    addi sp, sp, 16
1159; CHECK-NEXT:    .cfi_def_cfa_offset 0
1160; CHECK-NEXT:    ret
1161  %res = call <vscale x 16 x i64> @llvm.vp.fshr.nxv16i64(<vscale x 16 x i64> %a, <vscale x 16 x i64> %b, <vscale x 16 x i64> %c, <vscale x 16 x i1> %m, i32 %evl)
1162  ret <vscale x 16 x i64> %res
1163}
1164
1165declare <vscale x 16 x i64> @llvm.vp.fshl.nxv16i64(<vscale x 16 x i64>, <vscale x 16 x i64>, <vscale x 16 x i64>, <vscale x 16 x i1>, i32)
1166define <vscale x 16 x i64> @fshl_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i64> %b, <vscale x 16 x i64> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {
1167; CHECK-LABEL: fshl_v16i64:
1168; CHECK:       # %bb.0:
1169; CHECK-NEXT:    addi sp, sp, -16
1170; CHECK-NEXT:    .cfi_def_cfa_offset 16
1171; CHECK-NEXT:    csrr a1, vlenb
1172; CHECK-NEXT:    li a3, 40
1173; CHECK-NEXT:    mul a1, a1, a3
1174; CHECK-NEXT:    sub sp, sp, a1
1175; CHECK-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
1176; CHECK-NEXT:    vsetvli a1, zero, e8, mf4, ta, ma
1177; CHECK-NEXT:    vmv1r.v v24, v0
1178; CHECK-NEXT:    csrr a1, vlenb
1179; CHECK-NEXT:    slli a1, a1, 5
1180; CHECK-NEXT:    add a1, sp, a1
1181; CHECK-NEXT:    addi a1, a1, 16
1182; CHECK-NEXT:    vs8r.v v16, (a1) # Unknown-size Folded Spill
1183; CHECK-NEXT:    csrr a1, vlenb
1184; CHECK-NEXT:    li a3, 24
1185; CHECK-NEXT:    mul a1, a1, a3
1186; CHECK-NEXT:    add a1, sp, a1
1187; CHECK-NEXT:    addi a1, a1, 16
1188; CHECK-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
1189; CHECK-NEXT:    csrr a3, vlenb
1190; CHECK-NEXT:    slli a5, a3, 3
1191; CHECK-NEXT:    srli a1, a3, 3
1192; CHECK-NEXT:    sub a6, a4, a3
1193; CHECK-NEXT:    vslidedown.vx v0, v0, a1
1194; CHECK-NEXT:    add a1, a2, a5
1195; CHECK-NEXT:    vl8re64.v v8, (a1)
1196; CHECK-NEXT:    addi a1, sp, 16
1197; CHECK-NEXT:    vs8r.v v8, (a1) # Unknown-size Folded Spill
1198; CHECK-NEXT:    sltu a1, a4, a6
1199; CHECK-NEXT:    addi a1, a1, -1
1200; CHECK-NEXT:    and a6, a1, a6
1201; CHECK-NEXT:    li a1, 63
1202; CHECK-NEXT:    vsetvli zero, a6, e64, m8, ta, ma
1203; CHECK-NEXT:    vand.vx v8, v8, a1, v0.t
1204; CHECK-NEXT:    csrr a6, vlenb
1205; CHECK-NEXT:    slli a6, a6, 4
1206; CHECK-NEXT:    add a6, sp, a6
1207; CHECK-NEXT:    addi a6, a6, 16
1208; CHECK-NEXT:    vs8r.v v8, (a6) # Unknown-size Folded Spill
1209; CHECK-NEXT:    csrr a6, vlenb
1210; CHECK-NEXT:    slli a6, a6, 5
1211; CHECK-NEXT:    add a6, sp, a6
1212; CHECK-NEXT:    addi a6, a6, 16
1213; CHECK-NEXT:    vl8r.v v16, (a6) # Unknown-size Folded Reload
1214; CHECK-NEXT:    csrr a6, vlenb
1215; CHECK-NEXT:    slli a6, a6, 4
1216; CHECK-NEXT:    add a6, sp, a6
1217; CHECK-NEXT:    addi a6, a6, 16
1218; CHECK-NEXT:    vl8r.v v8, (a6) # Unknown-size Folded Reload
1219; CHECK-NEXT:    vsll.vv v16, v16, v8, v0.t
1220; CHECK-NEXT:    csrr a6, vlenb
1221; CHECK-NEXT:    slli a6, a6, 3
1222; CHECK-NEXT:    add a6, sp, a6
1223; CHECK-NEXT:    addi a6, a6, 16
1224; CHECK-NEXT:    vs8r.v v16, (a6) # Unknown-size Folded Spill
1225; CHECK-NEXT:    add a5, a0, a5
1226; CHECK-NEXT:    addi a6, sp, 16
1227; CHECK-NEXT:    vl8r.v v8, (a6) # Unknown-size Folded Reload
1228; CHECK-NEXT:    vnot.v v8, v8, v0.t
1229; CHECK-NEXT:    vl8re64.v v16, (a5)
1230; CHECK-NEXT:    vand.vx v8, v8, a1, v0.t
1231; CHECK-NEXT:    addi a5, sp, 16
1232; CHECK-NEXT:    vs8r.v v8, (a5) # Unknown-size Folded Spill
1233; CHECK-NEXT:    vl8re64.v v8, (a0)
1234; CHECK-NEXT:    csrr a0, vlenb
1235; CHECK-NEXT:    slli a0, a0, 4
1236; CHECK-NEXT:    add a0, sp, a0
1237; CHECK-NEXT:    addi a0, a0, 16
1238; CHECK-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
1239; CHECK-NEXT:    vl8re64.v v8, (a2)
1240; CHECK-NEXT:    csrr a0, vlenb
1241; CHECK-NEXT:    slli a0, a0, 5
1242; CHECK-NEXT:    add a0, sp, a0
1243; CHECK-NEXT:    addi a0, a0, 16
1244; CHECK-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
1245; CHECK-NEXT:    vsrl.vi v16, v16, 1, v0.t
1246; CHECK-NEXT:    addi a0, sp, 16
1247; CHECK-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
1248; CHECK-NEXT:    vsrl.vv v16, v16, v8, v0.t
1249; CHECK-NEXT:    csrr a0, vlenb
1250; CHECK-NEXT:    slli a0, a0, 3
1251; CHECK-NEXT:    add a0, sp, a0
1252; CHECK-NEXT:    addi a0, a0, 16
1253; CHECK-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
1254; CHECK-NEXT:    vor.vv v8, v8, v16, v0.t
1255; CHECK-NEXT:    csrr a0, vlenb
1256; CHECK-NEXT:    slli a0, a0, 3
1257; CHECK-NEXT:    add a0, sp, a0
1258; CHECK-NEXT:    addi a0, a0, 16
1259; CHECK-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
1260; CHECK-NEXT:    bltu a4, a3, .LBB47_2
1261; CHECK-NEXT:  # %bb.1:
1262; CHECK-NEXT:    mv a4, a3
1263; CHECK-NEXT:  .LBB47_2:
1264; CHECK-NEXT:    vmv1r.v v0, v24
1265; CHECK-NEXT:    csrr a0, vlenb
1266; CHECK-NEXT:    slli a0, a0, 5
1267; CHECK-NEXT:    add a0, sp, a0
1268; CHECK-NEXT:    addi a0, a0, 16
1269; CHECK-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
1270; CHECK-NEXT:    vsetvli zero, a4, e64, m8, ta, ma
1271; CHECK-NEXT:    vand.vx v8, v8, a1, v0.t
1272; CHECK-NEXT:    addi a0, sp, 16
1273; CHECK-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
1274; CHECK-NEXT:    csrr a0, vlenb
1275; CHECK-NEXT:    li a2, 24
1276; CHECK-NEXT:    mul a0, a0, a2
1277; CHECK-NEXT:    add a0, sp, a0
1278; CHECK-NEXT:    addi a0, a0, 16
1279; CHECK-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
1280; CHECK-NEXT:    addi a0, sp, 16
1281; CHECK-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
1282; CHECK-NEXT:    vsll.vv v8, v8, v16, v0.t
1283; CHECK-NEXT:    csrr a0, vlenb
1284; CHECK-NEXT:    li a2, 24
1285; CHECK-NEXT:    mul a0, a0, a2
1286; CHECK-NEXT:    add a0, sp, a0
1287; CHECK-NEXT:    addi a0, a0, 16
1288; CHECK-NEXT:    vs8r.v v8, (a0) # Unknown-size Folded Spill
1289; CHECK-NEXT:    csrr a0, vlenb
1290; CHECK-NEXT:    slli a0, a0, 5
1291; CHECK-NEXT:    add a0, sp, a0
1292; CHECK-NEXT:    addi a0, a0, 16
1293; CHECK-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
1294; CHECK-NEXT:    vnot.v v8, v8, v0.t
1295; CHECK-NEXT:    vand.vx v16, v8, a1, v0.t
1296; CHECK-NEXT:    csrr a0, vlenb
1297; CHECK-NEXT:    slli a0, a0, 4
1298; CHECK-NEXT:    add a0, sp, a0
1299; CHECK-NEXT:    addi a0, a0, 16
1300; CHECK-NEXT:    vl8r.v v8, (a0) # Unknown-size Folded Reload
1301; CHECK-NEXT:    vsrl.vi v8, v8, 1, v0.t
1302; CHECK-NEXT:    vsrl.vv v8, v8, v16, v0.t
1303; CHECK-NEXT:    csrr a0, vlenb
1304; CHECK-NEXT:    li a1, 24
1305; CHECK-NEXT:    mul a0, a0, a1
1306; CHECK-NEXT:    add a0, sp, a0
1307; CHECK-NEXT:    addi a0, a0, 16
1308; CHECK-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
1309; CHECK-NEXT:    vor.vv v8, v16, v8, v0.t
1310; CHECK-NEXT:    csrr a0, vlenb
1311; CHECK-NEXT:    slli a0, a0, 3
1312; CHECK-NEXT:    add a0, sp, a0
1313; CHECK-NEXT:    addi a0, a0, 16
1314; CHECK-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
1315; CHECK-NEXT:    csrr a0, vlenb
1316; CHECK-NEXT:    li a1, 40
1317; CHECK-NEXT:    mul a0, a0, a1
1318; CHECK-NEXT:    add sp, sp, a0
1319; CHECK-NEXT:    .cfi_def_cfa sp, 16
1320; CHECK-NEXT:    addi sp, sp, 16
1321; CHECK-NEXT:    .cfi_def_cfa_offset 0
1322; CHECK-NEXT:    ret
1323  %res = call <vscale x 16 x i64> @llvm.vp.fshl.nxv16i64(<vscale x 16 x i64> %a, <vscale x 16 x i64> %b, <vscale x 16 x i64> %c, <vscale x 16 x i1> %m, i32 %evl)
1324  ret <vscale x 16 x i64> %res
1325}
1326
1327; Test promotion.
1328declare <vscale x 1 x i9> @llvm.vp.fshr.nxv1i9(<vscale x 1 x i9>, <vscale x 1 x i9>, <vscale x 1 x i9>, <vscale x 1 x i1>, i32)
1329define <vscale x 1 x i9> @fshr_v1i9(<vscale x 1 x i9> %a, <vscale x 1 x i9> %b, <vscale x 1 x i9> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
1330; CHECK-LABEL: fshr_v1i9:
1331; CHECK:       # %bb.0:
1332; CHECK-NEXT:    li a1, 511
1333; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
1334; CHECK-NEXT:    vand.vx v10, v10, a1, v0.t
1335; CHECK-NEXT:    li a0, 9
1336; CHECK-NEXT:    vremu.vx v10, v10, a0, v0.t
1337; CHECK-NEXT:    vadd.vi v10, v10, 7, v0.t
1338; CHECK-NEXT:    vand.vi v11, v10, 15, v0.t
1339; CHECK-NEXT:    vsll.vi v9, v9, 7, v0.t
1340; CHECK-NEXT:    vsrl.vv v9, v9, v11, v0.t
1341; CHECK-NEXT:    vnot.v v10, v10, v0.t
1342; CHECK-NEXT:    vand.vi v10, v10, 15, v0.t
1343; CHECK-NEXT:    vsll.vi v8, v8, 1, v0.t
1344; CHECK-NEXT:    vsll.vv v8, v8, v10, v0.t
1345; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
1346; CHECK-NEXT:    ret
1347  %res = call <vscale x 1 x i9> @llvm.vp.fshr.nxv1i9(<vscale x 1 x i9> %a, <vscale x 1 x i9> %b, <vscale x 1 x i9> %c, <vscale x 1 x i1> %m, i32 %evl)
1348  ret <vscale x 1 x i9> %res
1349}
1350
1351declare <vscale x 1 x i9> @llvm.vp.fshl.nxv1i9(<vscale x 1 x i9>, <vscale x 1 x i9>, <vscale x 1 x i9>, <vscale x 1 x i1>, i32)
1352define <vscale x 1 x i9> @fshl_v1i9(<vscale x 1 x i9> %a, <vscale x 1 x i9> %b, <vscale x 1 x i9> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
1353; CHECK-LABEL: fshl_v1i9:
1354; CHECK:       # %bb.0:
1355; CHECK-NEXT:    li a1, 511
1356; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
1357; CHECK-NEXT:    vand.vx v10, v10, a1, v0.t
1358; CHECK-NEXT:    li a0, 9
1359; CHECK-NEXT:    vremu.vx v10, v10, a0, v0.t
1360; CHECK-NEXT:    vand.vi v11, v10, 15, v0.t
1361; CHECK-NEXT:    vsll.vv v8, v8, v11, v0.t
1362; CHECK-NEXT:    vnot.v v10, v10, v0.t
1363; CHECK-NEXT:    vand.vi v10, v10, 15, v0.t
1364; CHECK-NEXT:    vsll.vi v9, v9, 7, v0.t
1365; CHECK-NEXT:    vsrl.vi v9, v9, 1, v0.t
1366; CHECK-NEXT:    vsrl.vv v9, v9, v10, v0.t
1367; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
1368; CHECK-NEXT:    ret
1369  %res = call <vscale x 1 x i9> @llvm.vp.fshl.nxv1i9(<vscale x 1 x i9> %a, <vscale x 1 x i9> %b, <vscale x 1 x i9> %c, <vscale x 1 x i1> %m, i32 %evl)
1370  ret <vscale x 1 x i9> %res
1371}
1372
1373declare <vscale x 1 x i4> @llvm.vp.trunc.nxv1i4.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i1>, i32)
1374declare <vscale x 1 x i8> @llvm.vp.zext.nxv1i8.nxv1i4(<vscale x 1 x i4>, <vscale x 1 x i1>, i32)
1375declare <vscale x 1 x i4> @llvm.vp.fshr.nxv1i4(<vscale x 1 x i4>, <vscale x 1 x i4>, <vscale x 1 x i4>, <vscale x 1 x i1>, i32)
1376define <vscale x 1 x i8> @fshr_v1i4(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, <vscale x 1 x i8> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
1377; CHECK-LABEL: fshr_v1i4:
1378; CHECK:       # %bb.0:
1379; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
1380; CHECK-NEXT:    vand.vi v10, v10, 15, v0.t
1381; CHECK-NEXT:    li a0, 4
1382; CHECK-NEXT:    vand.vi v9, v9, 15, v0.t
1383; CHECK-NEXT:    vsll.vi v8, v8, 4, v0.t
1384; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
1385; CHECK-NEXT:    vremu.vx v9, v10, a0, v0.t
1386; CHECK-NEXT:    vsrl.vv v8, v8, v9, v0.t
1387; CHECK-NEXT:    vand.vi v8, v8, 15, v0.t
1388; CHECK-NEXT:    ret
1389  %trunca = call <vscale x 1 x i4> @llvm.vp.trunc.nxv1i4.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i1> %m, i32 zeroext %evl)
1390  %truncb = call <vscale x 1 x i4> @llvm.vp.trunc.nxv1i4.nxv1i8(<vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 zeroext %evl)
1391  %truncc = call <vscale x 1 x i4> @llvm.vp.trunc.nxv1i4.nxv1i8(<vscale x 1 x i8> %c, <vscale x 1 x i1> %m, i32 zeroext %evl)
1392  %fshr = call <vscale x 1 x i4> @llvm.vp.fshr.nxv1i4(<vscale x 1 x i4> %trunca, <vscale x 1 x i4> %truncb, <vscale x 1 x i4> %truncc, <vscale x 1 x i1> %m, i32 %evl)
1393  %res = call <vscale x 1 x i8> @llvm.vp.zext.nxv1i8.nxv1i4(<vscale x 1 x i4> %fshr, <vscale x 1 x i1> %m, i32 zeroext %evl)
1394  ret <vscale x 1 x i8> %res
1395}
1396
1397declare <vscale x 1 x i4> @llvm.vp.fshl.nxv1i4(<vscale x 1 x i4>, <vscale x 1 x i4>, <vscale x 1 x i4>, <vscale x 1 x i1>, i32)
1398define <vscale x 1 x i8> @fshl_v1i4(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b, <vscale x 1 x i8> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
1399; CHECK-LABEL: fshl_v1i4:
1400; CHECK:       # %bb.0:
1401; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
1402; CHECK-NEXT:    vand.vi v10, v10, 15, v0.t
1403; CHECK-NEXT:    li a0, 4
1404; CHECK-NEXT:    vand.vi v9, v9, 15, v0.t
1405; CHECK-NEXT:    vsll.vi v8, v8, 4, v0.t
1406; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
1407; CHECK-NEXT:    vremu.vx v9, v10, a0, v0.t
1408; CHECK-NEXT:    vsll.vv v8, v8, v9, v0.t
1409; CHECK-NEXT:    vsrl.vi v8, v8, 4, v0.t
1410; CHECK-NEXT:    vand.vi v8, v8, 15, v0.t
1411; CHECK-NEXT:    ret
1412  %trunca = call <vscale x 1 x i4> @llvm.vp.trunc.nxv1i4.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i1> %m, i32 zeroext %evl)
1413  %truncb = call <vscale x 1 x i4> @llvm.vp.trunc.nxv1i4.nxv1i8(<vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 zeroext %evl)
1414  %truncc = call <vscale x 1 x i4> @llvm.vp.trunc.nxv1i4.nxv1i8(<vscale x 1 x i8> %c, <vscale x 1 x i1> %m, i32 zeroext %evl)
1415  %fshl = call <vscale x 1 x i4> @llvm.vp.fshl.nxv1i4(<vscale x 1 x i4> %trunca, <vscale x 1 x i4> %truncb, <vscale x 1 x i4> %truncc, <vscale x 1 x i1> %m, i32 %evl)
1416  %res = call <vscale x 1 x i8> @llvm.vp.zext.nxv1i8.nxv1i4(<vscale x 1 x i4> %fshl, <vscale x 1 x i1> %m, i32 zeroext %evl)
1417  ret <vscale x 1 x i8> %res
1418}
1419