xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll (revision 1cb599835ccf7ee8b2d1d5a7f3107e19a26fc6f5) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK32
4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK64
6
7; Float
8
9declare <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f32.nxv2i32(<vscale x 2 x float>)
10declare <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f32.nxv4i32(<vscale x 4 x float>)
11declare <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f32.nxv8i32(<vscale x 8 x float>)
12declare <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f32.nxv4i16(<vscale x 4 x float>)
13declare <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f32.nxv8i16(<vscale x 8 x float>)
14declare <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f32.nxv2i64(<vscale x 2 x float>)
15declare <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f32.nxv4i64(<vscale x 4 x float>)
16
17define <vscale x 2 x i32> @test_signed_v2f32_v2i32(<vscale x 2 x float> %f) {
18; CHECK-LABEL: test_signed_v2f32_v2i32:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
21; CHECK-NEXT:    vmfne.vv v0, v8, v8
22; CHECK-NEXT:    vfcvt.rtz.xu.f.v v8, v8
23; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
24; CHECK-NEXT:    ret
25    %x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f32.nxv2i32(<vscale x 2 x float> %f)
26    ret <vscale x 2 x i32> %x
27}
28
29define <vscale x 4 x i32> @test_signed_v4f32_v4i32(<vscale x 4 x float> %f) {
30; CHECK-LABEL: test_signed_v4f32_v4i32:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
33; CHECK-NEXT:    vmfne.vv v0, v8, v8
34; CHECK-NEXT:    vfcvt.rtz.xu.f.v v8, v8
35; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
36; CHECK-NEXT:    ret
37    %x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f32.nxv4i32(<vscale x 4 x float> %f)
38    ret <vscale x 4 x i32> %x
39}
40
41define <vscale x 8 x i32> @test_signed_v8f32_v8i32(<vscale x 8 x float> %f) {
42; CHECK-LABEL: test_signed_v8f32_v8i32:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
45; CHECK-NEXT:    vmfne.vv v0, v8, v8
46; CHECK-NEXT:    vfcvt.rtz.xu.f.v v8, v8
47; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
48; CHECK-NEXT:    ret
49    %x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f32.nxv8i32(<vscale x 8 x float> %f)
50    ret <vscale x 8 x i32> %x
51}
52
53define <vscale x 4 x i16> @test_signed_v4f32_v4i16(<vscale x 4 x float> %f) {
54; CHECK-LABEL: test_signed_v4f32_v4i16:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
57; CHECK-NEXT:    vmfne.vv v0, v8, v8
58; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
59; CHECK-NEXT:    vfncvt.rtz.xu.f.w v10, v8
60; CHECK-NEXT:    vmerge.vim v8, v10, 0, v0
61; CHECK-NEXT:    ret
62    %x = call <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f32.nxv4i16(<vscale x 4 x float> %f)
63    ret <vscale x 4 x i16> %x
64}
65
66define <vscale x 8 x i16> @test_signed_v8f32_v8i16(<vscale x 8 x float> %f) {
67; CHECK-LABEL: test_signed_v8f32_v8i16:
68; CHECK:       # %bb.0:
69; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
70; CHECK-NEXT:    vmfne.vv v0, v8, v8
71; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
72; CHECK-NEXT:    vfncvt.rtz.xu.f.w v12, v8
73; CHECK-NEXT:    vmerge.vim v8, v12, 0, v0
74; CHECK-NEXT:    ret
75    %x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f32.nxv8i16(<vscale x 8 x float> %f)
76    ret <vscale x 8 x i16> %x
77}
78
79define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) {
80; CHECK-LABEL: test_signed_v2f32_v2i64:
81; CHECK:       # %bb.0:
82; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
83; CHECK-NEXT:    vmfne.vv v0, v8, v8
84; CHECK-NEXT:    vfwcvt.rtz.xu.f.v v10, v8
85; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
86; CHECK-NEXT:    vmerge.vim v8, v10, 0, v0
87; CHECK-NEXT:    ret
88    %x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f32.nxv2i64(<vscale x 2 x float> %f)
89    ret <vscale x 2 x i64> %x
90}
91
92define <vscale x 4 x i64> @test_signed_v4f32_v4i64(<vscale x 4 x float> %f) {
93; CHECK-LABEL: test_signed_v4f32_v4i64:
94; CHECK:       # %bb.0:
95; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
96; CHECK-NEXT:    vmfne.vv v0, v8, v8
97; CHECK-NEXT:    vfwcvt.rtz.xu.f.v v12, v8
98; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
99; CHECK-NEXT:    vmerge.vim v8, v12, 0, v0
100; CHECK-NEXT:    ret
101    %x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f32.nxv4i64(<vscale x 4 x float> %f)
102    ret <vscale x 4 x i64> %x
103}
104
105; Double
106
107declare <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f64.nxv2i32(<vscale x 2 x double>)
108declare <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f64.nxv4i32(<vscale x 4 x double>)
109declare <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f64.nxv8i32(<vscale x 8 x double>)
110declare <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f64.nxv4i16(<vscale x 4 x double>)
111declare <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f64.nxv8i16(<vscale x 8 x double>)
112declare <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f64.nxv2i64(<vscale x 2 x double>)
113declare <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f64.nxv4i64(<vscale x 4 x double>)
114
115define <vscale x 2 x i32> @test_signed_v2f64_v2i32(<vscale x 2 x double> %f) {
116; CHECK-LABEL: test_signed_v2f64_v2i32:
117; CHECK:       # %bb.0:
118; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
119; CHECK-NEXT:    vmfne.vv v0, v8, v8
120; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
121; CHECK-NEXT:    vfncvt.rtz.xu.f.w v10, v8
122; CHECK-NEXT:    vmerge.vim v8, v10, 0, v0
123; CHECK-NEXT:    ret
124    %x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f64.nxv2i32(<vscale x 2 x double> %f)
125    ret <vscale x 2 x i32> %x
126}
127
128define <vscale x 4 x i32> @test_signed_v4f64_v4i32(<vscale x 4 x double> %f) {
129; CHECK-LABEL: test_signed_v4f64_v4i32:
130; CHECK:       # %bb.0:
131; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
132; CHECK-NEXT:    vmfne.vv v0, v8, v8
133; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
134; CHECK-NEXT:    vfncvt.rtz.xu.f.w v12, v8
135; CHECK-NEXT:    vmerge.vim v8, v12, 0, v0
136; CHECK-NEXT:    ret
137    %x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f64.nxv4i32(<vscale x 4 x double> %f)
138    ret <vscale x 4 x i32> %x
139}
140
141define <vscale x 8 x i32> @test_signed_v8f64_v8i32(<vscale x 8 x double> %f) {
142; CHECK-LABEL: test_signed_v8f64_v8i32:
143; CHECK:       # %bb.0:
144; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
145; CHECK-NEXT:    vmfne.vv v0, v8, v8
146; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
147; CHECK-NEXT:    vfncvt.rtz.xu.f.w v16, v8
148; CHECK-NEXT:    vmerge.vim v8, v16, 0, v0
149; CHECK-NEXT:    ret
150    %x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f64.nxv8i32(<vscale x 8 x double> %f)
151    ret <vscale x 8 x i32> %x
152}
153
154define <vscale x 4 x i16> @test_signed_v4f64_v4i16(<vscale x 4 x double> %f) {
155; CHECK-LABEL: test_signed_v4f64_v4i16:
156; CHECK:       # %bb.0:
157; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
158; CHECK-NEXT:    vmfne.vv v0, v8, v8
159; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
160; CHECK-NEXT:    vfncvt.rtz.xu.f.w v12, v8
161; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
162; CHECK-NEXT:    vnclipu.wi v8, v12, 0
163; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
164; CHECK-NEXT:    ret
165    %x = call <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f64.nxv4i16(<vscale x 4 x double> %f)
166    ret <vscale x 4 x i16> %x
167}
168
169define <vscale x 8 x i16> @test_signed_v8f64_v8i16(<vscale x 8 x double> %f) {
170; CHECK-LABEL: test_signed_v8f64_v8i16:
171; CHECK:       # %bb.0:
172; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
173; CHECK-NEXT:    vmfne.vv v0, v8, v8
174; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
175; CHECK-NEXT:    vfncvt.rtz.xu.f.w v16, v8
176; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
177; CHECK-NEXT:    vnclipu.wi v8, v16, 0
178; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
179; CHECK-NEXT:    ret
180    %x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f64.nxv8i16(<vscale x 8 x double> %f)
181    ret <vscale x 8 x i16> %x
182}
183
184define <vscale x 2 x i64> @test_signed_v2f64_v2i64(<vscale x 2 x double> %f) {
185; CHECK-LABEL: test_signed_v2f64_v2i64:
186; CHECK:       # %bb.0:
187; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
188; CHECK-NEXT:    vmfne.vv v0, v8, v8
189; CHECK-NEXT:    vfcvt.rtz.xu.f.v v8, v8
190; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
191; CHECK-NEXT:    ret
192    %x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f64.nxv2i64(<vscale x 2 x double> %f)
193    ret <vscale x 2 x i64> %x
194}
195
196define <vscale x 4 x i64> @test_signed_v4f64_v4i64(<vscale x 4 x double> %f) {
197; CHECK-LABEL: test_signed_v4f64_v4i64:
198; CHECK:       # %bb.0:
199; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
200; CHECK-NEXT:    vmfne.vv v0, v8, v8
201; CHECK-NEXT:    vfcvt.rtz.xu.f.v v8, v8
202; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
203; CHECK-NEXT:    ret
204    %x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f64.nxv4i64(<vscale x 4 x double> %f)
205    ret <vscale x 4 x i64> %x
206}
207
208
209; half
210
211declare <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f16.nxv2i32(<vscale x 2 x half>)
212declare <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f16.nxv4i32(<vscale x 4 x half>)
213declare <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f16.nxv8i32(<vscale x 8 x half>)
214declare <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f16.nxv4i16(<vscale x 4 x half>)
215declare <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f16.nxv8i16(<vscale x 8 x half>)
216declare <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f16.nxv2i64(<vscale x 2 x half>)
217declare <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f16.nxv4i64(<vscale x 4 x half>)
218
219define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) {
220; CHECK-LABEL: test_signed_v2f16_v2i32:
221; CHECK:       # %bb.0:
222; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
223; CHECK-NEXT:    vmfne.vv v0, v8, v8
224; CHECK-NEXT:    vfwcvt.rtz.xu.f.v v9, v8
225; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
226; CHECK-NEXT:    vmerge.vim v8, v9, 0, v0
227; CHECK-NEXT:    ret
228    %x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f16.nxv2i32(<vscale x 2 x half> %f)
229    ret <vscale x 2 x i32> %x
230}
231
232define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {
233; CHECK-LABEL: test_signed_v4f16_v4i32:
234; CHECK:       # %bb.0:
235; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
236; CHECK-NEXT:    vmfne.vv v0, v8, v8
237; CHECK-NEXT:    vfwcvt.rtz.xu.f.v v10, v8
238; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
239; CHECK-NEXT:    vmerge.vim v8, v10, 0, v0
240; CHECK-NEXT:    ret
241    %x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f16.nxv4i32(<vscale x 4 x half> %f)
242    ret <vscale x 4 x i32> %x
243}
244
245define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) {
246; CHECK-LABEL: test_signed_v8f16_v8i32:
247; CHECK:       # %bb.0:
248; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
249; CHECK-NEXT:    vmfne.vv v0, v8, v8
250; CHECK-NEXT:    vfwcvt.rtz.xu.f.v v12, v8
251; CHECK-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
252; CHECK-NEXT:    vmerge.vim v8, v12, 0, v0
253; CHECK-NEXT:    ret
254    %x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f16.nxv8i32(<vscale x 8 x half> %f)
255    ret <vscale x 8 x i32> %x
256}
257
258define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) {
259; CHECK-LABEL: test_signed_v4f16_v4i16:
260; CHECK:       # %bb.0:
261; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
262; CHECK-NEXT:    vmfne.vv v0, v8, v8
263; CHECK-NEXT:    vfcvt.rtz.xu.f.v v8, v8
264; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
265; CHECK-NEXT:    ret
266    %x = call <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f16.nxv4i16(<vscale x 4 x half> %f)
267    ret <vscale x 4 x i16> %x
268}
269
270define <vscale x 8 x i16> @test_signed_v8f16_v8i16(<vscale x 8 x half> %f) {
271; CHECK-LABEL: test_signed_v8f16_v8i16:
272; CHECK:       # %bb.0:
273; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
274; CHECK-NEXT:    vmfne.vv v0, v8, v8
275; CHECK-NEXT:    vfcvt.rtz.xu.f.v v8, v8
276; CHECK-NEXT:    vmerge.vim v8, v8, 0, v0
277; CHECK-NEXT:    ret
278    %x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f16.nxv8i16(<vscale x 8 x half> %f)
279    ret <vscale x 8 x i16> %x
280}
281
282define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {
283; CHECK-LABEL: test_signed_v2f16_v2i64:
284; CHECK:       # %bb.0:
285; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
286; CHECK-NEXT:    vmfne.vv v0, v8, v8
287; CHECK-NEXT:    vfwcvt.f.f.v v9, v8
288; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
289; CHECK-NEXT:    vfwcvt.rtz.xu.f.v v10, v9
290; CHECK-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
291; CHECK-NEXT:    vmerge.vim v8, v10, 0, v0
292; CHECK-NEXT:    ret
293    %x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f16.nxv2i64(<vscale x 2 x half> %f)
294    ret <vscale x 2 x i64> %x
295}
296
297define <vscale x 4 x i64> @test_signed_v4f16_v4i64(<vscale x 4 x half> %f) {
298; CHECK-LABEL: test_signed_v4f16_v4i64:
299; CHECK:       # %bb.0:
300; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
301; CHECK-NEXT:    vmfne.vv v0, v8, v8
302; CHECK-NEXT:    vfwcvt.f.f.v v10, v8
303; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
304; CHECK-NEXT:    vfwcvt.rtz.xu.f.v v12, v10
305; CHECK-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
306; CHECK-NEXT:    vmerge.vim v8, v12, 0, v0
307; CHECK-NEXT:    ret
308    %x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f16.nxv4i64(<vscale x 4 x half> %f)
309    ret <vscale x 4 x i64> %x
310}
311;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
312; CHECK32: {{.*}}
313; CHECK64: {{.*}}
314