1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s 3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s 4 5; The following binop x, (zext i1) tests will be vector-legalized into a vselect 6; of two splat_vectors, but on RV64 the splat value will be implicitly 7; truncated: 8; 9; t15: nxv2i32 = splat_vector Constant:i64<1> 10; t13: nxv2i32 = splat_vector Constant:i64<0> 11; t16: nxv2i32 = vselect t2, t15, t13 12; t7: nxv2i32 = add t4, t16 13; 14; Make sure that foldSelectWithIdentityConstant in DAGCombiner.cpp handles the 15; truncating splat, so we pull the vselect back and fold it into a mask. 16 17define <vscale x 2 x i32> @i1_zext_add(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) { 18; CHECK-LABEL: i1_zext_add: 19; CHECK: # %bb.0: 20; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu 21; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t 22; CHECK-NEXT: ret 23 %zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32> 24 %add = add <vscale x 2 x i32> %b, %zext 25 ret <vscale x 2 x i32> %add 26} 27 28define <vscale x 2 x i32> @i1_zext_add_commuted(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) { 29; CHECK-LABEL: i1_zext_add_commuted: 30; CHECK: # %bb.0: 31; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu 32; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t 33; CHECK-NEXT: ret 34 %zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32> 35 %add = add <vscale x 2 x i32> %zext, %b 36 ret <vscale x 2 x i32> %add 37} 38 39define <vscale x 2 x i32> @i1_zext_sub(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) { 40; CHECK-LABEL: i1_zext_sub: 41; CHECK: # %bb.0: 42; CHECK-NEXT: li a0, 1 43; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu 44; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t 45; CHECK-NEXT: ret 46 %zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32> 47 %sub = sub <vscale x 2 x i32> %b, %zext 48 ret <vscale x 2 x i32> %sub 49} 50 51define <vscale x 2 x i32> @i1_zext_or(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b) { 52; CHECK-LABEL: i1_zext_or: 53; CHECK: # %bb.0: 54; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu 55; CHECK-NEXT: vor.vi v8, v8, 1, v0.t 56; CHECK-NEXT: ret 57 %zext = zext <vscale x 2 x i1> %a to <vscale x 2 x i32> 58 %or = or <vscale x 2 x i32> %b, %zext 59 ret <vscale x 2 x i32> %or 60} 61