xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll (revision 675e7bd1b94f78f0567b4327f187841c0cde36f9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+m,+v < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+m,+v < %s | FileCheck %s
4
5declare <4 x i16> @llvm.vp.zext.v4i16.v4i8(<4 x i8>, <4 x i1>, i32)
6
7define <4 x i16> @vzext_v4i16_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
8; CHECK-LABEL: vzext_v4i16_v4i8:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
11; CHECK-NEXT:    vzext.vf2 v9, v8, v0.t
12; CHECK-NEXT:    vmv1r.v v8, v9
13; CHECK-NEXT:    ret
14  %v = call <4 x i16> @llvm.vp.zext.v4i16.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)
15  ret <4 x i16> %v
16}
17
18define <4 x i16> @vzext_v4i16_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
19; CHECK-LABEL: vzext_v4i16_v4i8_unmasked:
20; CHECK:       # %bb.0:
21; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
22; CHECK-NEXT:    vzext.vf2 v9, v8
23; CHECK-NEXT:    vmv1r.v v8, v9
24; CHECK-NEXT:    ret
25  %v = call <4 x i16> @llvm.vp.zext.v4i16.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl)
26  ret <4 x i16> %v
27}
28
29declare <4 x i32> @llvm.vp.zext.v4i32.v4i8(<4 x i8>, <4 x i1>, i32)
30
31define <4 x i32> @vzext_v4i32_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
32; CHECK-LABEL: vzext_v4i32_v4i8:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
35; CHECK-NEXT:    vzext.vf4 v9, v8, v0.t
36; CHECK-NEXT:    vmv.v.v v8, v9
37; CHECK-NEXT:    ret
38  %v = call <4 x i32> @llvm.vp.zext.v4i32.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)
39  ret <4 x i32> %v
40}
41
42define <4 x i32> @vzext_v4i32_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
43; CHECK-LABEL: vzext_v4i32_v4i8_unmasked:
44; CHECK:       # %bb.0:
45; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
46; CHECK-NEXT:    vzext.vf4 v9, v8
47; CHECK-NEXT:    vmv.v.v v8, v9
48; CHECK-NEXT:    ret
49  %v = call <4 x i32> @llvm.vp.zext.v4i32.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl)
50  ret <4 x i32> %v
51}
52
53declare <4 x i64> @llvm.vp.zext.v4i64.v4i8(<4 x i8>, <4 x i1>, i32)
54
55define <4 x i64> @vzext_v4i64_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
56; CHECK-LABEL: vzext_v4i64_v4i8:
57; CHECK:       # %bb.0:
58; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
59; CHECK-NEXT:    vzext.vf8 v10, v8, v0.t
60; CHECK-NEXT:    vmv.v.v v8, v10
61; CHECK-NEXT:    ret
62  %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)
63  ret <4 x i64> %v
64}
65
66define <4 x i64> @vzext_v4i64_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
67; CHECK-LABEL: vzext_v4i64_v4i8_unmasked:
68; CHECK:       # %bb.0:
69; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
70; CHECK-NEXT:    vzext.vf8 v10, v8
71; CHECK-NEXT:    vmv.v.v v8, v10
72; CHECK-NEXT:    ret
73  %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl)
74  ret <4 x i64> %v
75}
76
77declare <4 x i32> @llvm.vp.zext.v4i32.v4i16(<4 x i16>, <4 x i1>, i32)
78
79define <4 x i32> @vzext_v4i32_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
80; CHECK-LABEL: vzext_v4i32_v4i16:
81; CHECK:       # %bb.0:
82; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
83; CHECK-NEXT:    vzext.vf2 v9, v8, v0.t
84; CHECK-NEXT:    vmv.v.v v8, v9
85; CHECK-NEXT:    ret
86  %v = call <4 x i32> @llvm.vp.zext.v4i32.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl)
87  ret <4 x i32> %v
88}
89
90define <4 x i32> @vzext_v4i32_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
91; CHECK-LABEL: vzext_v4i32_v4i16_unmasked:
92; CHECK:       # %bb.0:
93; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
94; CHECK-NEXT:    vzext.vf2 v9, v8
95; CHECK-NEXT:    vmv.v.v v8, v9
96; CHECK-NEXT:    ret
97  %v = call <4 x i32> @llvm.vp.zext.v4i32.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl)
98  ret <4 x i32> %v
99}
100
101declare <4 x i64> @llvm.vp.zext.v4i64.v4i16(<4 x i16>, <4 x i1>, i32)
102
103define <4 x i64> @vzext_v4i64_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
104; CHECK-LABEL: vzext_v4i64_v4i16:
105; CHECK:       # %bb.0:
106; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
107; CHECK-NEXT:    vzext.vf4 v10, v8, v0.t
108; CHECK-NEXT:    vmv.v.v v8, v10
109; CHECK-NEXT:    ret
110  %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl)
111  ret <4 x i64> %v
112}
113
114define <4 x i64> @vzext_v4i64_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
115; CHECK-LABEL: vzext_v4i64_v4i16_unmasked:
116; CHECK:       # %bb.0:
117; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
118; CHECK-NEXT:    vzext.vf4 v10, v8
119; CHECK-NEXT:    vmv.v.v v8, v10
120; CHECK-NEXT:    ret
121  %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl)
122  ret <4 x i64> %v
123}
124
125declare <4 x i64> @llvm.vp.zext.v4i64.v4i32(<4 x i32>, <4 x i1>, i32)
126
127define <4 x i64> @vzext_v4i64_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
128; CHECK-LABEL: vzext_v4i64_v4i32:
129; CHECK:       # %bb.0:
130; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
131; CHECK-NEXT:    vzext.vf2 v10, v8, v0.t
132; CHECK-NEXT:    vmv.v.v v8, v10
133; CHECK-NEXT:    ret
134  %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)
135  ret <4 x i64> %v
136}
137
138define <4 x i64> @vzext_v4i64_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
139; CHECK-LABEL: vzext_v4i64_v4i32_unmasked:
140; CHECK:       # %bb.0:
141; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
142; CHECK-NEXT:    vzext.vf2 v10, v8
143; CHECK-NEXT:    vmv.v.v v8, v10
144; CHECK-NEXT:    ret
145  %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl)
146  ret <4 x i64> %v
147}
148
149declare <32 x i64> @llvm.vp.zext.v32i64.v32i32(<32 x i32>, <32 x i1>, i32)
150
151define <32 x i64> @vzext_v32i64_v32i32(<32 x i32> %va, <32 x i1> %m, i32 zeroext %evl) {
152; CHECK-LABEL: vzext_v32i64_v32i32:
153; CHECK:       # %bb.0:
154; CHECK-NEXT:    li a2, 16
155; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
156; CHECK-NEXT:    vslidedown.vi v16, v0, 2
157; CHECK-NEXT:    mv a1, a0
158; CHECK-NEXT:    bltu a0, a2, .LBB12_2
159; CHECK-NEXT:  # %bb.1:
160; CHECK-NEXT:    li a1, 16
161; CHECK-NEXT:  .LBB12_2:
162; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
163; CHECK-NEXT:    vzext.vf2 v24, v8, v0.t
164; CHECK-NEXT:    addi a1, a0, -16
165; CHECK-NEXT:    sltu a0, a0, a1
166; CHECK-NEXT:    addi a0, a0, -1
167; CHECK-NEXT:    and a0, a0, a1
168; CHECK-NEXT:    vsetivli zero, 16, e32, m8, ta, ma
169; CHECK-NEXT:    vslidedown.vi v8, v8, 16
170; CHECK-NEXT:    vmv1r.v v0, v16
171; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
172; CHECK-NEXT:    vzext.vf2 v16, v8, v0.t
173; CHECK-NEXT:    vmv8r.v v8, v24
174; CHECK-NEXT:    ret
175  %v = call <32 x i64> @llvm.vp.zext.v32i64.v32i32(<32 x i32> %va, <32 x i1> %m, i32 %evl)
176  ret <32 x i64> %v
177}
178
179define <32 x i64> @vzext_v32i64_v32i32_unmasked(<32 x i32> %va, i32 zeroext %evl) {
180; CHECK-LABEL: vzext_v32i64_v32i32_unmasked:
181; CHECK:       # %bb.0:
182; CHECK-NEXT:    li a2, 16
183; CHECK-NEXT:    mv a1, a0
184; CHECK-NEXT:    bltu a0, a2, .LBB13_2
185; CHECK-NEXT:  # %bb.1:
186; CHECK-NEXT:    li a1, 16
187; CHECK-NEXT:  .LBB13_2:
188; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
189; CHECK-NEXT:    vzext.vf2 v24, v8
190; CHECK-NEXT:    addi a1, a0, -16
191; CHECK-NEXT:    sltu a0, a0, a1
192; CHECK-NEXT:    addi a0, a0, -1
193; CHECK-NEXT:    and a0, a0, a1
194; CHECK-NEXT:    vsetivli zero, 16, e32, m8, ta, ma
195; CHECK-NEXT:    vslidedown.vi v8, v8, 16
196; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
197; CHECK-NEXT:    vzext.vf2 v16, v8
198; CHECK-NEXT:    vmv8r.v v8, v24
199; CHECK-NEXT:    ret
200  %v = call <32 x i64> @llvm.vp.zext.v32i64.v32i32(<32 x i32> %va, <32 x i1> splat (i1 true), i32 %evl)
201  ret <32 x i64> %v
202}
203
204declare <4 x i16> @llvm.vp.zext.v4i16.v4i7(<4 x i7>, <4 x i1>, i32)
205
206define <4 x i16> @vzext_v4i16_v4i7(<4 x i7> %va, <4 x i1> %m, i32 zeroext %evl) {
207; CHECK-LABEL: vzext_v4i16_v4i7:
208; CHECK:       # %bb.0:
209; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
210; CHECK-NEXT:    vzext.vf2 v9, v8, v0.t
211; CHECK-NEXT:    li a0, 127
212; CHECK-NEXT:    vand.vx v8, v9, a0, v0.t
213; CHECK-NEXT:    ret
214  %v = call <4 x i16> @llvm.vp.zext.v4i16.v4i7(<4 x i7> %va, <4 x i1> %m, i32 %evl)
215  ret <4 x i16> %v
216}
217
218declare <4 x i8> @llvm.vp.zext.v4i8.v4i7(<4 x i7>, <4 x i1>, i32)
219
220define <4 x i8> @vzext_v4i8_v4i7(<4 x i7> %va, <4 x i1> %m, i32 zeroext %evl) {
221; CHECK-LABEL: vzext_v4i8_v4i7:
222; CHECK:       # %bb.0:
223; CHECK-NEXT:    li a1, 127
224; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
225; CHECK-NEXT:    vand.vx v8, v8, a1, v0.t
226; CHECK-NEXT:    ret
227  %v = call <4 x i8> @llvm.vp.zext.v4i8.v4i7(<4 x i7> %va, <4 x i1> %m, i32 %evl)
228  ret <4 x i8> %v
229}
230
231declare <4 x i15> @llvm.vp.zext.v4i15.v4i8(<4 x i8>, <4 x i1>, i32)
232
233define <4 x i15> @vzext_v4i15_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
234; CHECK-LABEL: vzext_v4i15_v4i8:
235; CHECK:       # %bb.0:
236; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
237; CHECK-NEXT:    vzext.vf2 v9, v8, v0.t
238; CHECK-NEXT:    vmv1r.v v8, v9
239; CHECK-NEXT:    ret
240  %v = call <4 x i15> @llvm.vp.zext.v4i15.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl)
241  ret <4 x i15> %v
242}
243
244declare <4 x i15> @llvm.vp.zext.v4i15.v4i9(<4 x i9>, <4 x i1>, i32)
245
246define <4 x i15> @vzext_v4i15_v4i9(<4 x i9> %va, <4 x i1> %m, i32 zeroext %evl) {
247; CHECK-LABEL: vzext_v4i15_v4i9:
248; CHECK:       # %bb.0:
249; CHECK-NEXT:    li a1, 511
250; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
251; CHECK-NEXT:    vand.vx v8, v8, a1, v0.t
252; CHECK-NEXT:    ret
253  %v = call <4 x i15> @llvm.vp.zext.v4i15.v4i9(<4 x i9> %va, <4 x i1> %m, i32 %evl)
254  ret <4 x i15> %v
255}
256