xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp-mask.ll (revision d8d131dfa99762ccdd2116661980b7d0493cd7b5) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+m,+v < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+m,+v < %s | FileCheck %s
4
5declare <4 x i16> @llvm.vp.zext.v4i16.v4i1(<4 x i1>, <4 x i1>, i32)
6
7define <4 x i16> @vzext_v4i16_v4i1(<4 x i1> %va, <4 x i1> %m, i32 zeroext %evl) {
8; CHECK-LABEL: vzext_v4i16_v4i1:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
11; CHECK-NEXT:    vmv.v.i v8, 0
12; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
13; CHECK-NEXT:    ret
14  %v = call <4 x i16> @llvm.vp.zext.v4i16.v4i1(<4 x i1> %va, <4 x i1> %m, i32 %evl)
15  ret <4 x i16> %v
16}
17
18define <4 x i16> @vzext_v4i16_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) {
19; CHECK-LABEL: vzext_v4i16_v4i1_unmasked:
20; CHECK:       # %bb.0:
21; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
22; CHECK-NEXT:    vmv.v.i v8, 0
23; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
24; CHECK-NEXT:    ret
25  %v = call <4 x i16> @llvm.vp.zext.v4i16.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl)
26  ret <4 x i16> %v
27}
28
29declare <4 x i32> @llvm.vp.zext.v4i32.v4i1(<4 x i1>, <4 x i1>, i32)
30
31define <4 x i32> @vzext_v4i32_v4i1(<4 x i1> %va, <4 x i1> %m, i32 zeroext %evl) {
32; CHECK-LABEL: vzext_v4i32_v4i1:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
35; CHECK-NEXT:    vmv.v.i v8, 0
36; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
37; CHECK-NEXT:    ret
38  %v = call <4 x i32> @llvm.vp.zext.v4i32.v4i1(<4 x i1> %va, <4 x i1> %m, i32 %evl)
39  ret <4 x i32> %v
40}
41
42define <4 x i32> @vzext_v4i32_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) {
43; CHECK-LABEL: vzext_v4i32_v4i1_unmasked:
44; CHECK:       # %bb.0:
45; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
46; CHECK-NEXT:    vmv.v.i v8, 0
47; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
48; CHECK-NEXT:    ret
49  %v = call <4 x i32> @llvm.vp.zext.v4i32.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl)
50  ret <4 x i32> %v
51}
52
53declare <4 x i64> @llvm.vp.zext.v4i64.v4i1(<4 x i1>, <4 x i1>, i32)
54
55define <4 x i64> @vzext_v4i64_v4i1(<4 x i1> %va, <4 x i1> %m, i32 zeroext %evl) {
56; CHECK-LABEL: vzext_v4i64_v4i1:
57; CHECK:       # %bb.0:
58; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
59; CHECK-NEXT:    vmv.v.i v8, 0
60; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
61; CHECK-NEXT:    ret
62  %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i1(<4 x i1> %va, <4 x i1> %m, i32 %evl)
63  ret <4 x i64> %v
64}
65
66define <4 x i64> @vzext_v4i64_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) {
67; CHECK-LABEL: vzext_v4i64_v4i1_unmasked:
68; CHECK:       # %bb.0:
69; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
70; CHECK-NEXT:    vmv.v.i v8, 0
71; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
72; CHECK-NEXT:    ret
73  %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl)
74  ret <4 x i64> %v
75}
76