1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh,+xsfvcp \ 3; RUN: -verify-machineinstrs | FileCheck %s 4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh,+xsfvcp \ 5; RUN: -verify-machineinstrs | FileCheck %s 6 7define void @test_sf_vc_vvv_se_e8mf8(<1 x i8> %vd, <1 x i8> %vs2, <1 x i8> %vs1, iXLen %vl) { 8; CHECK-LABEL: test_sf_vc_vvv_se_e8mf8: 9; CHECK: # %bb.0: # %entry 10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma 11; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 12; CHECK-NEXT: ret 13entry: 14 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1i8.nxv1i8.iXLen(iXLen 3, <1 x i8> %vd, <1 x i8> %vs2, <1 x i8> %vs1, iXLen %vl) 15 ret void 16} 17 18declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1i8.nxv1i8.iXLen(iXLen, <1 x i8>, <1 x i8>, <1 x i8>, iXLen) 19 20define void @test_sf_vc_vvv_se_e8mf4(<2 x i8> %vd, <2 x i8> %vs2, <2 x i8> %vs1, iXLen %vl) { 21; CHECK-LABEL: test_sf_vc_vvv_se_e8mf4: 22; CHECK: # %bb.0: # %entry 23; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma 24; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 25; CHECK-NEXT: ret 26entry: 27 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2i8.nxv2i8.iXLen(iXLen 3, <2 x i8> %vd, <2 x i8> %vs2, <2 x i8> %vs1, iXLen %vl) 28 ret void 29} 30 31declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2i8.nxv2i8.iXLen(iXLen, <2 x i8>, <2 x i8>, <2 x i8>, iXLen) 32 33define void @test_sf_vc_vvv_se_e8mf2(<4 x i8> %vd, <4 x i8> %vs2, <4 x i8> %vs1, iXLen %vl) { 34; CHECK-LABEL: test_sf_vc_vvv_se_e8mf2: 35; CHECK: # %bb.0: # %entry 36; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma 37; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 38; CHECK-NEXT: ret 39entry: 40 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4i8.nxv4i8.iXLen(iXLen 3, <4 x i8> %vd, <4 x i8> %vs2, <4 x i8> %vs1, iXLen %vl) 41 ret void 42} 43 44declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4i8.nxv4i8.iXLen(iXLen, <4 x i8>, <4 x i8>, <4 x i8>, iXLen) 45 46define void @test_sf_vc_vvv_se_e8m1(<8 x i8> %vd, <8 x i8> %vs2, <8 x i8> %vs1, iXLen %vl) { 47; CHECK-LABEL: test_sf_vc_vvv_se_e8m1: 48; CHECK: # %bb.0: # %entry 49; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 50; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 51; CHECK-NEXT: ret 52entry: 53 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8i8.nxv8i8.iXLen(iXLen 3, <8 x i8> %vd, <8 x i8> %vs2, <8 x i8> %vs1, iXLen %vl) 54 ret void 55} 56 57declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8i8.nxv8i8.iXLen(iXLen, <8 x i8>, <8 x i8>, <8 x i8>, iXLen) 58 59define void @test_sf_vc_vvv_se_e8m2(<16 x i8> %vd, <16 x i8> %vs2, <16 x i8> %vs1, iXLen %vl) { 60; CHECK-LABEL: test_sf_vc_vvv_se_e8m2: 61; CHECK: # %bb.0: # %entry 62; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma 63; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 64; CHECK-NEXT: ret 65entry: 66 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv16i8.nxv16i8.iXLen(iXLen 3, <16 x i8> %vd, <16 x i8> %vs2, <16 x i8> %vs1, iXLen %vl) 67 ret void 68} 69 70declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv16i8.nxv16i8.iXLen(iXLen, <16 x i8>, <16 x i8>, <16 x i8>, iXLen) 71 72define void @test_sf_vc_vvv_se_e8m4(<32 x i8> %vd, <32 x i8> %vs2, <32 x i8> %vs1, iXLen %vl) { 73; CHECK-LABEL: test_sf_vc_vvv_se_e8m4: 74; CHECK: # %bb.0: # %entry 75; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma 76; CHECK-NEXT: sf.vc.vvv 3, v8, v10, v12 77; CHECK-NEXT: ret 78entry: 79 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv32i8.nxv32i8.iXLen(iXLen 3, <32 x i8> %vd, <32 x i8> %vs2, <32 x i8> %vs1, iXLen %vl) 80 ret void 81} 82 83declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv32i8.nxv32i8.iXLen(iXLen, <32 x i8>, <32 x i8>, <32 x i8>, iXLen) 84 85define void @test_sf_vc_vvv_se_e8m8(<64 x i8> %vd, <64 x i8> %vs2, <64 x i8> %vs1, iXLen %vl) { 86; CHECK-LABEL: test_sf_vc_vvv_se_e8m8: 87; CHECK: # %bb.0: # %entry 88; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma 89; CHECK-NEXT: sf.vc.vvv 3, v8, v12, v16 90; CHECK-NEXT: ret 91entry: 92 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv64i8.nxv64i8.iXLen(iXLen 3, <64 x i8> %vd, <64 x i8> %vs2, <64 x i8> %vs1, iXLen %vl) 93 ret void 94} 95 96declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv64i8.nxv64i8.iXLen(iXLen, <64 x i8>, <64 x i8>, <64 x i8>, iXLen) 97 98define void @test_sf_vc_vvv_se_e16mf4(<1 x i16> %vd, <1 x i16> %vs2, <1 x i16> %vs1, iXLen %vl) { 99; CHECK-LABEL: test_sf_vc_vvv_se_e16mf4: 100; CHECK: # %bb.0: # %entry 101; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma 102; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 103; CHECK-NEXT: ret 104entry: 105 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1i16.nxv1i16.iXLen(iXLen 3, <1 x i16> %vd, <1 x i16> %vs2, <1 x i16> %vs1, iXLen %vl) 106 ret void 107} 108 109declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1i16.nxv1i16.iXLen(iXLen, <1 x i16>, <1 x i16>, <1 x i16>, iXLen) 110 111define void @test_sf_vc_vvv_se_e16mf2(<2 x i16> %vd, <2 x i16> %vs2, <2 x i16> %vs1, iXLen %vl) { 112; CHECK-LABEL: test_sf_vc_vvv_se_e16mf2: 113; CHECK: # %bb.0: # %entry 114; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma 115; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 116; CHECK-NEXT: ret 117entry: 118 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2i16.nxv2i16.iXLen(iXLen 3, <2 x i16> %vd, <2 x i16> %vs2, <2 x i16> %vs1, iXLen %vl) 119 ret void 120} 121 122declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2i16.nxv2i16.iXLen(iXLen, <2 x i16>, <2 x i16>, <2 x i16>, iXLen) 123 124define void @test_sf_vc_vvv_se_e16m1(<4 x i16> %vd, <4 x i16> %vs2, <4 x i16> %vs1, iXLen %vl) { 125; CHECK-LABEL: test_sf_vc_vvv_se_e16m1: 126; CHECK: # %bb.0: # %entry 127; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 128; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 129; CHECK-NEXT: ret 130entry: 131 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4i16.nxv4i16.iXLen(iXLen 3, <4 x i16> %vd, <4 x i16> %vs2, <4 x i16> %vs1, iXLen %vl) 132 ret void 133} 134 135declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4i16.nxv4i16.iXLen(iXLen, <4 x i16>, <4 x i16>, <4 x i16>, iXLen) 136 137define void @test_sf_vc_vvv_se_e16m2(<8 x i16> %vd, <8 x i16> %vs2, <8 x i16> %vs1, iXLen %vl) { 138; CHECK-LABEL: test_sf_vc_vvv_se_e16m2: 139; CHECK: # %bb.0: # %entry 140; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma 141; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 142; CHECK-NEXT: ret 143entry: 144 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8i16.nxv8i16.iXLen(iXLen 3, <8 x i16> %vd, <8 x i16> %vs2, <8 x i16> %vs1, iXLen %vl) 145 ret void 146} 147 148declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8i16.nxv8i16.iXLen(iXLen, <8 x i16>, <8 x i16>, <8 x i16>, iXLen) 149 150define void @test_sf_vc_vvv_se_e16m4(<16 x i16> %vd, <16 x i16> %vs2, <16 x i16> %vs1, iXLen %vl) { 151; CHECK-LABEL: test_sf_vc_vvv_se_e16m4: 152; CHECK: # %bb.0: # %entry 153; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma 154; CHECK-NEXT: sf.vc.vvv 3, v8, v10, v12 155; CHECK-NEXT: ret 156entry: 157 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv16i16.nxv16i16.iXLen(iXLen 3, <16 x i16> %vd, <16 x i16> %vs2, <16 x i16> %vs1, iXLen %vl) 158 ret void 159} 160 161declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv16i16.nxv16i16.iXLen(iXLen, <16 x i16>, <16 x i16>, <16 x i16>, iXLen) 162 163define void @test_sf_vc_vvv_se_e16m8(<32 x i16> %vd, <32 x i16> %vs2, <32 x i16> %vs1, iXLen %vl) { 164; CHECK-LABEL: test_sf_vc_vvv_se_e16m8: 165; CHECK: # %bb.0: # %entry 166; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma 167; CHECK-NEXT: sf.vc.vvv 3, v8, v12, v16 168; CHECK-NEXT: ret 169entry: 170 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv32i16.nxv32i16.iXLen(iXLen 3, <32 x i16> %vd, <32 x i16> %vs2, <32 x i16> %vs1, iXLen %vl) 171 ret void 172} 173 174declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv32i16.nxv32i16.iXLen(iXLen, <32 x i16>, <32 x i16>, <32 x i16>, iXLen) 175 176define void @test_sf_vc_vvv_se_e32mf2(<1 x i32> %vd, <1 x i32> %vs2, <1 x i32> %vs1, iXLen %vl) { 177; CHECK-LABEL: test_sf_vc_vvv_se_e32mf2: 178; CHECK: # %bb.0: # %entry 179; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma 180; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 181; CHECK-NEXT: ret 182entry: 183 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1i32.nxv1i32.iXLen(iXLen 3, <1 x i32> %vd, <1 x i32> %vs2, <1 x i32> %vs1, iXLen %vl) 184 ret void 185} 186 187declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1i32.nxv1i32.iXLen(iXLen, <1 x i32>, <1 x i32>, <1 x i32>, iXLen) 188 189define void @test_sf_vc_vvv_se_e32m1(<2 x i32> %vd, <2 x i32> %vs2, <2 x i32> %vs1, iXLen %vl) { 190; CHECK-LABEL: test_sf_vc_vvv_se_e32m1: 191; CHECK: # %bb.0: # %entry 192; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma 193; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 194; CHECK-NEXT: ret 195entry: 196 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2i32.nxv2i32.iXLen(iXLen 3, <2 x i32> %vd, <2 x i32> %vs2, <2 x i32> %vs1, iXLen %vl) 197 ret void 198} 199 200declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2i32.nxv2i32.iXLen(iXLen, <2 x i32>, <2 x i32>, <2 x i32>, iXLen) 201 202define void @test_sf_vc_vvv_se_e32m2(<4 x i32> %vd, <4 x i32> %vs2, <4 x i32> %vs1, iXLen %vl) { 203; CHECK-LABEL: test_sf_vc_vvv_se_e32m2: 204; CHECK: # %bb.0: # %entry 205; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 206; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 207; CHECK-NEXT: ret 208entry: 209 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4i32.nxv4i32.iXLen(iXLen 3, <4 x i32> %vd, <4 x i32> %vs2, <4 x i32> %vs1, iXLen %vl) 210 ret void 211} 212 213declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4i32.nxv4i32.iXLen(iXLen, <4 x i32>, <4 x i32>, <4 x i32>, iXLen) 214 215define void @test_sf_vc_vvv_se_e32m4(<8 x i32> %vd, <8 x i32> %vs2, <8 x i32> %vs1, iXLen %vl) { 216; CHECK-LABEL: test_sf_vc_vvv_se_e32m4: 217; CHECK: # %bb.0: # %entry 218; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma 219; CHECK-NEXT: sf.vc.vvv 3, v8, v10, v12 220; CHECK-NEXT: ret 221entry: 222 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8i32.nxv8i32.iXLen(iXLen 3, <8 x i32> %vd, <8 x i32> %vs2, <8 x i32> %vs1, iXLen %vl) 223 ret void 224} 225 226declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8i32.nxv8i32.iXLen(iXLen, <8 x i32>, <8 x i32>, <8 x i32>, iXLen) 227 228define void @test_sf_vc_vvv_se_e32m8(<16 x i32> %vd, <16 x i32> %vs2, <16 x i32> %vs1, iXLen %vl) { 229; CHECK-LABEL: test_sf_vc_vvv_se_e32m8: 230; CHECK: # %bb.0: # %entry 231; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma 232; CHECK-NEXT: sf.vc.vvv 3, v8, v12, v16 233; CHECK-NEXT: ret 234entry: 235 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv16i32.nxv16i32.iXLen(iXLen 3, <16 x i32> %vd, <16 x i32> %vs2, <16 x i32> %vs1, iXLen %vl) 236 ret void 237} 238 239declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv16i32.nxv16i32.iXLen(iXLen, <16 x i32>, <16 x i32>, <16 x i32>, iXLen) 240 241define void @test_sf_vc_vvv_se_e64m1(<1 x i64> %vd, <1 x i64> %vs2, <1 x i64> %vs1, iXLen %vl) { 242; CHECK-LABEL: test_sf_vc_vvv_se_e64m1: 243; CHECK: # %bb.0: # %entry 244; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma 245; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 246; CHECK-NEXT: ret 247entry: 248 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1i64.nxv1i64.iXLen(iXLen 3, <1 x i64> %vd, <1 x i64> %vs2, <1 x i64> %vs1, iXLen %vl) 249 ret void 250} 251 252declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1i64.nxv1i64.iXLen(iXLen, <1 x i64>, <1 x i64>, <1 x i64>, iXLen) 253 254define void @test_sf_vc_vvv_se_e64m2(<2 x i64> %vd, <2 x i64> %vs2, <2 x i64> %vs1, iXLen %vl) { 255; CHECK-LABEL: test_sf_vc_vvv_se_e64m2: 256; CHECK: # %bb.0: # %entry 257; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma 258; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 259; CHECK-NEXT: ret 260entry: 261 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2i64.nxv2i64.iXLen(iXLen 3, <2 x i64> %vd, <2 x i64> %vs2, <2 x i64> %vs1, iXLen %vl) 262 ret void 263} 264 265declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2i64.nxv2i64.iXLen(iXLen, <2 x i64>, <2 x i64>, <2 x i64>, iXLen) 266 267define void @test_sf_vc_vvv_se_e64m4(<4 x i64> %vd, <4 x i64> %vs2, <4 x i64> %vs1, iXLen %vl) { 268; CHECK-LABEL: test_sf_vc_vvv_se_e64m4: 269; CHECK: # %bb.0: # %entry 270; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma 271; CHECK-NEXT: sf.vc.vvv 3, v8, v10, v12 272; CHECK-NEXT: ret 273entry: 274 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4i64.nxv4i64.iXLen(iXLen 3, <4 x i64> %vd, <4 x i64> %vs2, <4 x i64> %vs1, iXLen %vl) 275 ret void 276} 277 278declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4i64.nxv4i64.iXLen(iXLen, <4 x i64>, <4 x i64>, <4 x i64>, iXLen) 279 280define void @test_sf_vc_vvv_se_e64m8(<8 x i64> %vd, <8 x i64> %vs2, <8 x i64> %vs1, iXLen %vl) { 281; CHECK-LABEL: test_sf_vc_vvv_se_e64m8: 282; CHECK: # %bb.0: # %entry 283; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma 284; CHECK-NEXT: sf.vc.vvv 3, v8, v12, v16 285; CHECK-NEXT: ret 286entry: 287 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8i64.nxv8i64.iXLen(iXLen 3, <8 x i64> %vd, <8 x i64> %vs2, <8 x i64> %vs1, iXLen %vl) 288 ret void 289} 290 291declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8i64.nxv8i64.iXLen(iXLen, <8 x i64>, <8 x i64>, <8 x i64>, iXLen) 292 293define <1 x i8> @test_sf_vc_v_vvv_se_e8mf8(<1 x i8> %vd, <1 x i8> %vs2, <1 x i8> %vs1, iXLen %vl) { 294; CHECK-LABEL: test_sf_vc_v_vvv_se_e8mf8: 295; CHECK: # %bb.0: # %entry 296; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma 297; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 298; CHECK-NEXT: ret 299entry: 300 %0 = tail call <1 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv1i8.iXLen.nxv1i8.iXLen(iXLen 3, <1 x i8> %vd, <1 x i8> %vs2, <1 x i8> %vs1, iXLen %vl) 301 ret <1 x i8> %0 302} 303 304declare <1 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv1i8.iXLen.nxv1i8.iXLen(iXLen, <1 x i8>, <1 x i8>, <1 x i8>, iXLen) 305 306define <2 x i8> @test_sf_vc_v_vvv_se_e8mf4(<2 x i8> %vd, <2 x i8> %vs2, <2 x i8> %vs1, iXLen %vl) { 307; CHECK-LABEL: test_sf_vc_v_vvv_se_e8mf4: 308; CHECK: # %bb.0: # %entry 309; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma 310; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 311; CHECK-NEXT: ret 312entry: 313 %0 = tail call <2 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv2i8.iXLen.nxv2i8.iXLen(iXLen 3, <2 x i8> %vd, <2 x i8> %vs2, <2 x i8> %vs1, iXLen %vl) 314 ret <2 x i8> %0 315} 316 317declare <2 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv2i8.iXLen.nxv2i8.iXLen(iXLen, <2 x i8>, <2 x i8>, <2 x i8>, iXLen) 318 319define <4 x i8> @test_sf_vc_v_vvv_se_e8mf2(<4 x i8> %vd, <4 x i8> %vs2, <4 x i8> %vs1, iXLen %vl) { 320; CHECK-LABEL: test_sf_vc_v_vvv_se_e8mf2: 321; CHECK: # %bb.0: # %entry 322; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma 323; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 324; CHECK-NEXT: ret 325entry: 326 %0 = tail call <4 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv4i8.iXLen.nxv4i8.iXLen(iXLen 3, <4 x i8> %vd, <4 x i8> %vs2, <4 x i8> %vs1, iXLen %vl) 327 ret <4 x i8> %0 328} 329 330declare <4 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv4i8.iXLen.nxv4i8.iXLen(iXLen, <4 x i8>, <4 x i8>, <4 x i8>, iXLen) 331 332define <8 x i8> @test_sf_vc_v_vvv_se_e8m1(<8 x i8> %vd, <8 x i8> %vs2, <8 x i8> %vs1, iXLen %vl) { 333; CHECK-LABEL: test_sf_vc_v_vvv_se_e8m1: 334; CHECK: # %bb.0: # %entry 335; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma 336; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 337; CHECK-NEXT: ret 338entry: 339 %0 = tail call <8 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv8i8.iXLen.nxv8i8.iXLen(iXLen 3, <8 x i8> %vd, <8 x i8> %vs2, <8 x i8> %vs1, iXLen %vl) 340 ret <8 x i8> %0 341} 342 343declare <8 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv8i8.iXLen.nxv8i8.iXLen(iXLen, <8 x i8>, <8 x i8>, <8 x i8>, iXLen) 344 345define <16 x i8> @test_sf_vc_v_vvv_se_e8m2(<16 x i8> %vd, <16 x i8> %vs2, <16 x i8> %vs1, iXLen %vl) { 346; CHECK-LABEL: test_sf_vc_v_vvv_se_e8m2: 347; CHECK: # %bb.0: # %entry 348; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma 349; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 350; CHECK-NEXT: ret 351entry: 352 %0 = tail call <16 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv16i8.iXLen.nxv16i8.iXLen(iXLen 3, <16 x i8> %vd, <16 x i8> %vs2, <16 x i8> %vs1, iXLen %vl) 353 ret <16 x i8> %0 354} 355 356declare <16 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv16i8.iXLen.nxv16i8.iXLen(iXLen, <16 x i8>, <16 x i8>, <16 x i8>, iXLen) 357 358define <32 x i8> @test_sf_vc_v_vvv_se_e8m4(<32 x i8> %vd, <32 x i8> %vs2, <32 x i8> %vs1, iXLen %vl) { 359; CHECK-LABEL: test_sf_vc_v_vvv_se_e8m4: 360; CHECK: # %bb.0: # %entry 361; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma 362; CHECK-NEXT: sf.vc.v.vvv 3, v8, v10, v12 363; CHECK-NEXT: ret 364entry: 365 %0 = tail call <32 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv32i8.iXLen.nxv32i8.iXLen(iXLen 3, <32 x i8> %vd, <32 x i8> %vs2, <32 x i8> %vs1, iXLen %vl) 366 ret <32 x i8> %0 367} 368 369declare <32 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv32i8.iXLen.nxv32i8.iXLen(iXLen, <32 x i8>, <32 x i8>, <32 x i8>, iXLen) 370 371define <64 x i8> @test_sf_vc_v_vvv_se_e8m8(<64 x i8> %vd, <64 x i8> %vs2, <64 x i8> %vs1, iXLen %vl) { 372; CHECK-LABEL: test_sf_vc_v_vvv_se_e8m8: 373; CHECK: # %bb.0: # %entry 374; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma 375; CHECK-NEXT: sf.vc.v.vvv 3, v8, v12, v16 376; CHECK-NEXT: ret 377entry: 378 %0 = tail call <64 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv64i8.iXLen.nxv64i8.iXLen(iXLen 3, <64 x i8> %vd, <64 x i8> %vs2, <64 x i8> %vs1, iXLen %vl) 379 ret <64 x i8> %0 380} 381 382declare <64 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv64i8.iXLen.nxv64i8.iXLen(iXLen, <64 x i8>, <64 x i8>, <64 x i8>, iXLen) 383 384define <1 x i16> @test_sf_vc_v_vvv_se_e16mf4(<1 x i16> %vd, <1 x i16> %vs2, <1 x i16> %vs1, iXLen %vl) { 385; CHECK-LABEL: test_sf_vc_v_vvv_se_e16mf4: 386; CHECK: # %bb.0: # %entry 387; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma 388; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 389; CHECK-NEXT: ret 390entry: 391 %0 = tail call <1 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv1i16.iXLen.nxv1i16.iXLen(iXLen 3, <1 x i16> %vd, <1 x i16> %vs2, <1 x i16> %vs1, iXLen %vl) 392 ret <1 x i16> %0 393} 394 395declare <1 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv1i16.iXLen.nxv1i16.iXLen(iXLen, <1 x i16>, <1 x i16>, <1 x i16>, iXLen) 396 397define <2 x i16> @test_sf_vc_v_vvv_se_e16mf2(<2 x i16> %vd, <2 x i16> %vs2, <2 x i16> %vs1, iXLen %vl) { 398; CHECK-LABEL: test_sf_vc_v_vvv_se_e16mf2: 399; CHECK: # %bb.0: # %entry 400; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma 401; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 402; CHECK-NEXT: ret 403entry: 404 %0 = tail call <2 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv2i16.iXLen.nxv2i16.iXLen(iXLen 3, <2 x i16> %vd, <2 x i16> %vs2, <2 x i16> %vs1, iXLen %vl) 405 ret <2 x i16> %0 406} 407 408declare <2 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv2i16.iXLen.nxv2i16.iXLen(iXLen, <2 x i16>, <2 x i16>, <2 x i16>, iXLen) 409 410define <4 x i16> @test_sf_vc_v_vvv_se_e16m1(<4 x i16> %vd, <4 x i16> %vs2, <4 x i16> %vs1, iXLen %vl) { 411; CHECK-LABEL: test_sf_vc_v_vvv_se_e16m1: 412; CHECK: # %bb.0: # %entry 413; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma 414; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 415; CHECK-NEXT: ret 416entry: 417 %0 = tail call <4 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv4i16.iXLen.nxv4i16.iXLen(iXLen 3, <4 x i16> %vd, <4 x i16> %vs2, <4 x i16> %vs1, iXLen %vl) 418 ret <4 x i16> %0 419} 420 421declare <4 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv4i16.iXLen.nxv4i16.iXLen(iXLen, <4 x i16>, <4 x i16>, <4 x i16>, iXLen) 422 423define <8 x i16> @test_sf_vc_v_vvv_se_e16m2(<8 x i16> %vd, <8 x i16> %vs2, <8 x i16> %vs1, iXLen %vl) { 424; CHECK-LABEL: test_sf_vc_v_vvv_se_e16m2: 425; CHECK: # %bb.0: # %entry 426; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma 427; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 428; CHECK-NEXT: ret 429entry: 430 %0 = tail call <8 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv8i16.iXLen.nxv8i16.iXLen(iXLen 3, <8 x i16> %vd, <8 x i16> %vs2, <8 x i16> %vs1, iXLen %vl) 431 ret <8 x i16> %0 432} 433 434declare <8 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv8i16.iXLen.nxv8i16.iXLen(iXLen, <8 x i16>, <8 x i16>, <8 x i16>, iXLen) 435 436define <16 x i16> @test_sf_vc_v_vvv_se_e16m4(<16 x i16> %vd, <16 x i16> %vs2, <16 x i16> %vs1, iXLen %vl) { 437; CHECK-LABEL: test_sf_vc_v_vvv_se_e16m4: 438; CHECK: # %bb.0: # %entry 439; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma 440; CHECK-NEXT: sf.vc.v.vvv 3, v8, v10, v12 441; CHECK-NEXT: ret 442entry: 443 %0 = tail call <16 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv16i16.iXLen.nxv16i16.iXLen(iXLen 3, <16 x i16> %vd, <16 x i16> %vs2, <16 x i16> %vs1, iXLen %vl) 444 ret <16 x i16> %0 445} 446 447declare <16 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv16i16.iXLen.nxv16i16.iXLen(iXLen, <16 x i16>, <16 x i16>, <16 x i16>, iXLen) 448 449define <32 x i16> @test_sf_vc_v_vvv_se_e16m8(<32 x i16> %vd, <32 x i16> %vs2, <32 x i16> %vs1, iXLen %vl) { 450; CHECK-LABEL: test_sf_vc_v_vvv_se_e16m8: 451; CHECK: # %bb.0: # %entry 452; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma 453; CHECK-NEXT: sf.vc.v.vvv 3, v8, v12, v16 454; CHECK-NEXT: ret 455entry: 456 %0 = tail call <32 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv32i16.iXLen.nxv32i16.iXLen(iXLen 3, <32 x i16> %vd, <32 x i16> %vs2, <32 x i16> %vs1, iXLen %vl) 457 ret <32 x i16> %0 458} 459 460declare <32 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv32i16.iXLen.nxv32i16.iXLen(iXLen, <32 x i16>, <32 x i16>, <32 x i16>, iXLen) 461 462define <1 x i32> @test_sf_vc_v_vvv_se_e32mf2(<1 x i32> %vd, <1 x i32> %vs2, <1 x i32> %vs1, iXLen %vl) { 463; CHECK-LABEL: test_sf_vc_v_vvv_se_e32mf2: 464; CHECK: # %bb.0: # %entry 465; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma 466; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 467; CHECK-NEXT: ret 468entry: 469 %0 = tail call <1 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv1i32.iXLen.nxv1i32.iXLen(iXLen 3, <1 x i32> %vd, <1 x i32> %vs2, <1 x i32> %vs1, iXLen %vl) 470 ret <1 x i32> %0 471} 472 473declare <1 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv1i32.iXLen.nxv1i32.iXLen(iXLen, <1 x i32>, <1 x i32>, <1 x i32>, iXLen) 474 475define <2 x i32> @test_sf_vc_v_vvv_se_e32m1(<2 x i32> %vd, <2 x i32> %vs2, <2 x i32> %vs1, iXLen %vl) { 476; CHECK-LABEL: test_sf_vc_v_vvv_se_e32m1: 477; CHECK: # %bb.0: # %entry 478; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma 479; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 480; CHECK-NEXT: ret 481entry: 482 %0 = tail call <2 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv2i32.iXLen.nxv2i32.iXLen(iXLen 3, <2 x i32> %vd, <2 x i32> %vs2, <2 x i32> %vs1, iXLen %vl) 483 ret <2 x i32> %0 484} 485 486declare <2 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv2i32.iXLen.nxv2i32.iXLen(iXLen, <2 x i32>, <2 x i32>, <2 x i32>, iXLen) 487 488define <4 x i32> @test_sf_vc_v_vvv_se_e32m2(<4 x i32> %vd, <4 x i32> %vs2, <4 x i32> %vs1, iXLen %vl) { 489; CHECK-LABEL: test_sf_vc_v_vvv_se_e32m2: 490; CHECK: # %bb.0: # %entry 491; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma 492; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 493; CHECK-NEXT: ret 494entry: 495 %0 = tail call <4 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv4i32.iXLen.nxv4i32.iXLen(iXLen 3, <4 x i32> %vd, <4 x i32> %vs2, <4 x i32> %vs1, iXLen %vl) 496 ret <4 x i32> %0 497} 498 499declare <4 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv4i32.iXLen.nxv4i32.iXLen(iXLen, <4 x i32>, <4 x i32>, <4 x i32>, iXLen) 500 501define <8 x i32> @test_sf_vc_v_vvv_se_e32m4(<8 x i32> %vd, <8 x i32> %vs2, <8 x i32> %vs1, iXLen %vl) { 502; CHECK-LABEL: test_sf_vc_v_vvv_se_e32m4: 503; CHECK: # %bb.0: # %entry 504; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma 505; CHECK-NEXT: sf.vc.v.vvv 3, v8, v10, v12 506; CHECK-NEXT: ret 507entry: 508 %0 = tail call <8 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv8i32.iXLen.nxv8i32.iXLen(iXLen 3, <8 x i32> %vd, <8 x i32> %vs2, <8 x i32> %vs1, iXLen %vl) 509 ret <8 x i32> %0 510} 511 512declare <8 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv8i32.iXLen.nxv8i32.iXLen(iXLen, <8 x i32>, <8 x i32>, <8 x i32>, iXLen) 513 514define <16 x i32> @test_sf_vc_v_vvv_se_e32m8(<16 x i32> %vd, <16 x i32> %vs2, <16 x i32> %vs1, iXLen %vl) { 515; CHECK-LABEL: test_sf_vc_v_vvv_se_e32m8: 516; CHECK: # %bb.0: # %entry 517; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma 518; CHECK-NEXT: sf.vc.v.vvv 3, v8, v12, v16 519; CHECK-NEXT: ret 520entry: 521 %0 = tail call <16 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv16i32.iXLen.nxv16i32.iXLen(iXLen 3, <16 x i32> %vd, <16 x i32> %vs2, <16 x i32> %vs1, iXLen %vl) 522 ret <16 x i32> %0 523} 524 525declare <16 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv16i32.iXLen.nxv16i32.iXLen(iXLen, <16 x i32>, <16 x i32>, <16 x i32>, iXLen) 526 527define <1 x i64> @test_sf_vc_v_vvv_se_e64m1(<1 x i64> %vd, <1 x i64> %vs2, <1 x i64> %vs1, iXLen %vl) { 528; CHECK-LABEL: test_sf_vc_v_vvv_se_e64m1: 529; CHECK: # %bb.0: # %entry 530; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma 531; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 532; CHECK-NEXT: ret 533entry: 534 %0 = tail call <1 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv1i64.iXLen.nxv1i64.iXLen(iXLen 3, <1 x i64> %vd, <1 x i64> %vs2, <1 x i64> %vs1, iXLen %vl) 535 ret <1 x i64> %0 536} 537 538declare <1 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv1i64.iXLen.nxv1i64.iXLen(iXLen, <1 x i64>, <1 x i64>, <1 x i64>, iXLen) 539 540define <2 x i64> @test_sf_vc_v_vvv_se_e64m2(<2 x i64> %vd, <2 x i64> %vs2, <2 x i64> %vs1, iXLen %vl) { 541; CHECK-LABEL: test_sf_vc_v_vvv_se_e64m2: 542; CHECK: # %bb.0: # %entry 543; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma 544; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 545; CHECK-NEXT: ret 546entry: 547 %0 = tail call <2 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv2i64.iXLen.nxv2i64.iXLen(iXLen 3, <2 x i64> %vd, <2 x i64> %vs2, <2 x i64> %vs1, iXLen %vl) 548 ret <2 x i64> %0 549} 550 551declare <2 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv2i64.iXLen.nxv2i64.iXLen(iXLen, <2 x i64>, <2 x i64>, <2 x i64>, iXLen) 552 553define <4 x i64> @test_sf_vc_v_vvv_se_e64m4(<4 x i64> %vd, <4 x i64> %vs2, <4 x i64> %vs1, iXLen %vl) { 554; CHECK-LABEL: test_sf_vc_v_vvv_se_e64m4: 555; CHECK: # %bb.0: # %entry 556; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma 557; CHECK-NEXT: sf.vc.v.vvv 3, v8, v10, v12 558; CHECK-NEXT: ret 559entry: 560 %0 = tail call <4 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv4i64.iXLen.nxv4i64.iXLen(iXLen 3, <4 x i64> %vd, <4 x i64> %vs2, <4 x i64> %vs1, iXLen %vl) 561 ret <4 x i64> %0 562} 563 564declare <4 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv4i64.iXLen.nxv4i64.iXLen(iXLen, <4 x i64>, <4 x i64>, <4 x i64>, iXLen) 565 566define <8 x i64> @test_sf_vc_v_vvv_se_e64m8(<8 x i64> %vd, <8 x i64> %vs2, <8 x i64> %vs1, iXLen %vl) { 567; CHECK-LABEL: test_sf_vc_v_vvv_se_e64m8: 568; CHECK: # %bb.0: # %entry 569; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma 570; CHECK-NEXT: sf.vc.v.vvv 3, v8, v12, v16 571; CHECK-NEXT: ret 572entry: 573 %0 = tail call <8 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv8i64.iXLen.nxv8i64.iXLen(iXLen 3, <8 x i64> %vd, <8 x i64> %vs2, <8 x i64> %vs1, iXLen %vl) 574 ret <8 x i64> %0 575} 576 577declare <8 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv8i64.iXLen.nxv8i64.iXLen(iXLen, <8 x i64>, <8 x i64>, <8 x i64>, iXLen) 578 579define <1 x i8> @test_sf_vc_v_vvv_e8mf8(<1 x i8> %vd, <1 x i8> %vs2, <1 x i8> %vs1, iXLen %vl) { 580; CHECK-LABEL: test_sf_vc_v_vvv_e8mf8: 581; CHECK: # %bb.0: # %entry 582; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma 583; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 584; CHECK-NEXT: ret 585entry: 586 %0 = tail call <1 x i8> @llvm.riscv.sf.vc.v.vvv.nxv1i8.iXLen.nxv1i8.iXLen(iXLen 3, <1 x i8> %vd, <1 x i8> %vs2, <1 x i8> %vs1, iXLen %vl) 587 ret <1 x i8> %0 588} 589 590declare <1 x i8> @llvm.riscv.sf.vc.v.vvv.nxv1i8.iXLen.nxv1i8.iXLen(iXLen, <1 x i8>, <1 x i8>, <1 x i8>, iXLen) 591 592define <2 x i8> @test_sf_vc_v_vvv_e8mf4(<2 x i8> %vd, <2 x i8> %vs2, <2 x i8> %vs1, iXLen %vl) { 593; CHECK-LABEL: test_sf_vc_v_vvv_e8mf4: 594; CHECK: # %bb.0: # %entry 595; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma 596; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 597; CHECK-NEXT: ret 598entry: 599 %0 = tail call <2 x i8> @llvm.riscv.sf.vc.v.vvv.nxv2i8.iXLen.nxv2i8.iXLen(iXLen 3, <2 x i8> %vd, <2 x i8> %vs2, <2 x i8> %vs1, iXLen %vl) 600 ret <2 x i8> %0 601} 602 603declare <2 x i8> @llvm.riscv.sf.vc.v.vvv.nxv2i8.iXLen.nxv2i8.iXLen(iXLen, <2 x i8>, <2 x i8>, <2 x i8>, iXLen) 604 605define <4 x i8> @test_sf_vc_v_vvv_e8mf2(<4 x i8> %vd, <4 x i8> %vs2, <4 x i8> %vs1, iXLen %vl) { 606; CHECK-LABEL: test_sf_vc_v_vvv_e8mf2: 607; CHECK: # %bb.0: # %entry 608; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma 609; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 610; CHECK-NEXT: ret 611entry: 612 %0 = tail call <4 x i8> @llvm.riscv.sf.vc.v.vvv.nxv4i8.iXLen.nxv4i8.iXLen(iXLen 3, <4 x i8> %vd, <4 x i8> %vs2, <4 x i8> %vs1, iXLen %vl) 613 ret <4 x i8> %0 614} 615 616declare <4 x i8> @llvm.riscv.sf.vc.v.vvv.nxv4i8.iXLen.nxv4i8.iXLen(iXLen, <4 x i8>, <4 x i8>, <4 x i8>, iXLen) 617 618define <8 x i8> @test_sf_vc_v_vvv_e8m1(<8 x i8> %vd, <8 x i8> %vs2, <8 x i8> %vs1, iXLen %vl) { 619; CHECK-LABEL: test_sf_vc_v_vvv_e8m1: 620; CHECK: # %bb.0: # %entry 621; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma 622; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 623; CHECK-NEXT: ret 624entry: 625 %0 = tail call <8 x i8> @llvm.riscv.sf.vc.v.vvv.nxv8i8.iXLen.nxv8i8.iXLen(iXLen 3, <8 x i8> %vd, <8 x i8> %vs2, <8 x i8> %vs1, iXLen %vl) 626 ret <8 x i8> %0 627} 628 629declare <8 x i8> @llvm.riscv.sf.vc.v.vvv.nxv8i8.iXLen.nxv8i8.iXLen(iXLen, <8 x i8>, <8 x i8>, <8 x i8>, iXLen) 630 631define <16 x i8> @test_sf_vc_v_vvv_e8m2(<16 x i8> %vd, <16 x i8> %vs2, <16 x i8> %vs1, iXLen %vl) { 632; CHECK-LABEL: test_sf_vc_v_vvv_e8m2: 633; CHECK: # %bb.0: # %entry 634; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma 635; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 636; CHECK-NEXT: ret 637entry: 638 %0 = tail call <16 x i8> @llvm.riscv.sf.vc.v.vvv.nxv16i8.iXLen.nxv16i8.iXLen(iXLen 3, <16 x i8> %vd, <16 x i8> %vs2, <16 x i8> %vs1, iXLen %vl) 639 ret <16 x i8> %0 640} 641 642declare <16 x i8> @llvm.riscv.sf.vc.v.vvv.nxv16i8.iXLen.nxv16i8.iXLen(iXLen, <16 x i8>, <16 x i8>, <16 x i8>, iXLen) 643 644define <32 x i8> @test_sf_vc_v_vvv_e8m4(<32 x i8> %vd, <32 x i8> %vs2, <32 x i8> %vs1, iXLen %vl) { 645; CHECK-LABEL: test_sf_vc_v_vvv_e8m4: 646; CHECK: # %bb.0: # %entry 647; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma 648; CHECK-NEXT: sf.vc.v.vvv 3, v8, v10, v12 649; CHECK-NEXT: ret 650entry: 651 %0 = tail call <32 x i8> @llvm.riscv.sf.vc.v.vvv.nxv32i8.iXLen.nxv32i8.iXLen(iXLen 3, <32 x i8> %vd, <32 x i8> %vs2, <32 x i8> %vs1, iXLen %vl) 652 ret <32 x i8> %0 653} 654 655declare <32 x i8> @llvm.riscv.sf.vc.v.vvv.nxv32i8.iXLen.nxv32i8.iXLen(iXLen, <32 x i8>, <32 x i8>, <32 x i8>, iXLen) 656 657define <64 x i8> @test_sf_vc_v_vvv_e8m8(<64 x i8> %vd, <64 x i8> %vs2, <64 x i8> %vs1, iXLen %vl) { 658; CHECK-LABEL: test_sf_vc_v_vvv_e8m8: 659; CHECK: # %bb.0: # %entry 660; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma 661; CHECK-NEXT: sf.vc.v.vvv 3, v8, v12, v16 662; CHECK-NEXT: ret 663entry: 664 %0 = tail call <64 x i8> @llvm.riscv.sf.vc.v.vvv.nxv64i8.iXLen.nxv64i8.iXLen(iXLen 3, <64 x i8> %vd, <64 x i8> %vs2, <64 x i8> %vs1, iXLen %vl) 665 ret <64 x i8> %0 666} 667 668declare <64 x i8> @llvm.riscv.sf.vc.v.vvv.nxv64i8.iXLen.nxv64i8.iXLen(iXLen, <64 x i8>, <64 x i8>, <64 x i8>, iXLen) 669 670define <1 x i16> @test_sf_vc_v_vvv_e16mf4(<1 x i16> %vd, <1 x i16> %vs2, <1 x i16> %vs1, iXLen %vl) { 671; CHECK-LABEL: test_sf_vc_v_vvv_e16mf4: 672; CHECK: # %bb.0: # %entry 673; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma 674; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 675; CHECK-NEXT: ret 676entry: 677 %0 = tail call <1 x i16> @llvm.riscv.sf.vc.v.vvv.nxv1i16.iXLen.nxv1i16.iXLen(iXLen 3, <1 x i16> %vd, <1 x i16> %vs2, <1 x i16> %vs1, iXLen %vl) 678 ret <1 x i16> %0 679} 680 681declare <1 x i16> @llvm.riscv.sf.vc.v.vvv.nxv1i16.iXLen.nxv1i16.iXLen(iXLen, <1 x i16>, <1 x i16>, <1 x i16>, iXLen) 682 683define <2 x i16> @test_sf_vc_v_vvv_e16mf2(<2 x i16> %vd, <2 x i16> %vs2, <2 x i16> %vs1, iXLen %vl) { 684; CHECK-LABEL: test_sf_vc_v_vvv_e16mf2: 685; CHECK: # %bb.0: # %entry 686; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma 687; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 688; CHECK-NEXT: ret 689entry: 690 %0 = tail call <2 x i16> @llvm.riscv.sf.vc.v.vvv.nxv2i16.iXLen.nxv2i16.iXLen(iXLen 3, <2 x i16> %vd, <2 x i16> %vs2, <2 x i16> %vs1, iXLen %vl) 691 ret <2 x i16> %0 692} 693 694declare <2 x i16> @llvm.riscv.sf.vc.v.vvv.nxv2i16.iXLen.nxv2i16.iXLen(iXLen, <2 x i16>, <2 x i16>, <2 x i16>, iXLen) 695 696define <4 x i16> @test_sf_vc_v_vvv_e16m1(<4 x i16> %vd, <4 x i16> %vs2, <4 x i16> %vs1, iXLen %vl) { 697; CHECK-LABEL: test_sf_vc_v_vvv_e16m1: 698; CHECK: # %bb.0: # %entry 699; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma 700; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 701; CHECK-NEXT: ret 702entry: 703 %0 = tail call <4 x i16> @llvm.riscv.sf.vc.v.vvv.nxv4i16.iXLen.nxv4i16.iXLen(iXLen 3, <4 x i16> %vd, <4 x i16> %vs2, <4 x i16> %vs1, iXLen %vl) 704 ret <4 x i16> %0 705} 706 707declare <4 x i16> @llvm.riscv.sf.vc.v.vvv.nxv4i16.iXLen.nxv4i16.iXLen(iXLen, <4 x i16>, <4 x i16>, <4 x i16>, iXLen) 708 709define <8 x i16> @test_sf_vc_v_vvv_e16m2(<8 x i16> %vd, <8 x i16> %vs2, <8 x i16> %vs1, iXLen %vl) { 710; CHECK-LABEL: test_sf_vc_v_vvv_e16m2: 711; CHECK: # %bb.0: # %entry 712; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma 713; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 714; CHECK-NEXT: ret 715entry: 716 %0 = tail call <8 x i16> @llvm.riscv.sf.vc.v.vvv.nxv8i16.iXLen.nxv8i16.iXLen(iXLen 3, <8 x i16> %vd, <8 x i16> %vs2, <8 x i16> %vs1, iXLen %vl) 717 ret <8 x i16> %0 718} 719 720declare <8 x i16> @llvm.riscv.sf.vc.v.vvv.nxv8i16.iXLen.nxv8i16.iXLen(iXLen, <8 x i16>, <8 x i16>, <8 x i16>, iXLen) 721 722define <16 x i16> @test_sf_vc_v_vvv_e16m4(<16 x i16> %vd, <16 x i16> %vs2, <16 x i16> %vs1, iXLen %vl) { 723; CHECK-LABEL: test_sf_vc_v_vvv_e16m4: 724; CHECK: # %bb.0: # %entry 725; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma 726; CHECK-NEXT: sf.vc.v.vvv 3, v8, v10, v12 727; CHECK-NEXT: ret 728entry: 729 %0 = tail call <16 x i16> @llvm.riscv.sf.vc.v.vvv.nxv16i16.iXLen.nxv16i16.iXLen(iXLen 3, <16 x i16> %vd, <16 x i16> %vs2, <16 x i16> %vs1, iXLen %vl) 730 ret <16 x i16> %0 731} 732 733declare <16 x i16> @llvm.riscv.sf.vc.v.vvv.nxv16i16.iXLen.nxv16i16.iXLen(iXLen, <16 x i16>, <16 x i16>, <16 x i16>, iXLen) 734 735define <32 x i16> @test_sf_vc_v_vvv_e16m8(<32 x i16> %vd, <32 x i16> %vs2, <32 x i16> %vs1, iXLen %vl) { 736; CHECK-LABEL: test_sf_vc_v_vvv_e16m8: 737; CHECK: # %bb.0: # %entry 738; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma 739; CHECK-NEXT: sf.vc.v.vvv 3, v8, v12, v16 740; CHECK-NEXT: ret 741entry: 742 %0 = tail call <32 x i16> @llvm.riscv.sf.vc.v.vvv.nxv32i16.iXLen.nxv32i16.iXLen(iXLen 3, <32 x i16> %vd, <32 x i16> %vs2, <32 x i16> %vs1, iXLen %vl) 743 ret <32 x i16> %0 744} 745 746declare <32 x i16> @llvm.riscv.sf.vc.v.vvv.nxv32i16.iXLen.nxv32i16.iXLen(iXLen, <32 x i16>, <32 x i16>, <32 x i16>, iXLen) 747 748define <1 x i32> @test_sf_vc_v_vvv_e32mf2(<1 x i32> %vd, <1 x i32> %vs2, <1 x i32> %vs1, iXLen %vl) { 749; CHECK-LABEL: test_sf_vc_v_vvv_e32mf2: 750; CHECK: # %bb.0: # %entry 751; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma 752; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 753; CHECK-NEXT: ret 754entry: 755 %0 = tail call <1 x i32> @llvm.riscv.sf.vc.v.vvv.nxv1i32.iXLen.nxv1i32.iXLen(iXLen 3, <1 x i32> %vd, <1 x i32> %vs2, <1 x i32> %vs1, iXLen %vl) 756 ret <1 x i32> %0 757} 758 759declare <1 x i32> @llvm.riscv.sf.vc.v.vvv.nxv1i32.iXLen.nxv1i32.iXLen(iXLen, <1 x i32>, <1 x i32>, <1 x i32>, iXLen) 760 761define <2 x i32> @test_sf_vc_v_vvv_e32m1(<2 x i32> %vd, <2 x i32> %vs2, <2 x i32> %vs1, iXLen %vl) { 762; CHECK-LABEL: test_sf_vc_v_vvv_e32m1: 763; CHECK: # %bb.0: # %entry 764; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma 765; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 766; CHECK-NEXT: ret 767entry: 768 %0 = tail call <2 x i32> @llvm.riscv.sf.vc.v.vvv.nxv2i32.iXLen.nxv2i32.iXLen(iXLen 3, <2 x i32> %vd, <2 x i32> %vs2, <2 x i32> %vs1, iXLen %vl) 769 ret <2 x i32> %0 770} 771 772declare <2 x i32> @llvm.riscv.sf.vc.v.vvv.nxv2i32.iXLen.nxv2i32.iXLen(iXLen, <2 x i32>, <2 x i32>, <2 x i32>, iXLen) 773 774define <4 x i32> @test_sf_vc_v_vvv_e32m2(<4 x i32> %vd, <4 x i32> %vs2, <4 x i32> %vs1, iXLen %vl) { 775; CHECK-LABEL: test_sf_vc_v_vvv_e32m2: 776; CHECK: # %bb.0: # %entry 777; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma 778; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 779; CHECK-NEXT: ret 780entry: 781 %0 = tail call <4 x i32> @llvm.riscv.sf.vc.v.vvv.nxv4i32.iXLen.nxv4i32.iXLen(iXLen 3, <4 x i32> %vd, <4 x i32> %vs2, <4 x i32> %vs1, iXLen %vl) 782 ret <4 x i32> %0 783} 784 785declare <4 x i32> @llvm.riscv.sf.vc.v.vvv.nxv4i32.iXLen.nxv4i32.iXLen(iXLen, <4 x i32>, <4 x i32>, <4 x i32>, iXLen) 786 787define <8 x i32> @test_sf_vc_v_vvv_e32m4(<8 x i32> %vd, <8 x i32> %vs2, <8 x i32> %vs1, iXLen %vl) { 788; CHECK-LABEL: test_sf_vc_v_vvv_e32m4: 789; CHECK: # %bb.0: # %entry 790; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma 791; CHECK-NEXT: sf.vc.v.vvv 3, v8, v10, v12 792; CHECK-NEXT: ret 793entry: 794 %0 = tail call <8 x i32> @llvm.riscv.sf.vc.v.vvv.nxv8i32.iXLen.nxv8i32.iXLen(iXLen 3, <8 x i32> %vd, <8 x i32> %vs2, <8 x i32> %vs1, iXLen %vl) 795 ret <8 x i32> %0 796} 797 798declare <8 x i32> @llvm.riscv.sf.vc.v.vvv.nxv8i32.iXLen.nxv8i32.iXLen(iXLen, <8 x i32>, <8 x i32>, <8 x i32>, iXLen) 799 800define <16 x i32> @test_sf_vc_v_vvv_e32m8(<16 x i32> %vd, <16 x i32> %vs2, <16 x i32> %vs1, iXLen %vl) { 801; CHECK-LABEL: test_sf_vc_v_vvv_e32m8: 802; CHECK: # %bb.0: # %entry 803; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma 804; CHECK-NEXT: sf.vc.v.vvv 3, v8, v12, v16 805; CHECK-NEXT: ret 806entry: 807 %0 = tail call <16 x i32> @llvm.riscv.sf.vc.v.vvv.nxv16i32.iXLen.nxv16i32.iXLen(iXLen 3, <16 x i32> %vd, <16 x i32> %vs2, <16 x i32> %vs1, iXLen %vl) 808 ret <16 x i32> %0 809} 810 811declare <16 x i32> @llvm.riscv.sf.vc.v.vvv.nxv16i32.iXLen.nxv16i32.iXLen(iXLen, <16 x i32>, <16 x i32>, <16 x i32>, iXLen) 812 813define <1 x i64> @test_sf_vc_v_vvv_e64m1(<1 x i64> %vd, <1 x i64> %vs2, <1 x i64> %vs1, iXLen %vl) { 814; CHECK-LABEL: test_sf_vc_v_vvv_e64m1: 815; CHECK: # %bb.0: # %entry 816; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma 817; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 818; CHECK-NEXT: ret 819entry: 820 %0 = tail call <1 x i64> @llvm.riscv.sf.vc.v.vvv.nxv1i64.iXLen.nxv1i64.iXLen(iXLen 3, <1 x i64> %vd, <1 x i64> %vs2, <1 x i64> %vs1, iXLen %vl) 821 ret <1 x i64> %0 822} 823 824declare <1 x i64> @llvm.riscv.sf.vc.v.vvv.nxv1i64.iXLen.nxv1i64.iXLen(iXLen, <1 x i64>, <1 x i64>, <1 x i64>, iXLen) 825 826define <2 x i64> @test_sf_vc_v_vvv_e64m2(<2 x i64> %vd, <2 x i64> %vs2, <2 x i64> %vs1, iXLen %vl) { 827; CHECK-LABEL: test_sf_vc_v_vvv_e64m2: 828; CHECK: # %bb.0: # %entry 829; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma 830; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 831; CHECK-NEXT: ret 832entry: 833 %0 = tail call <2 x i64> @llvm.riscv.sf.vc.v.vvv.nxv2i64.iXLen.nxv2i64.iXLen(iXLen 3, <2 x i64> %vd, <2 x i64> %vs2, <2 x i64> %vs1, iXLen %vl) 834 ret <2 x i64> %0 835} 836 837declare <2 x i64> @llvm.riscv.sf.vc.v.vvv.nxv2i64.iXLen.nxv2i64.iXLen(iXLen, <2 x i64>, <2 x i64>, <2 x i64>, iXLen) 838 839define <4 x i64> @test_sf_vc_v_vvv_e64m4(<4 x i64> %vd, <4 x i64> %vs2, <4 x i64> %vs1, iXLen %vl) { 840; CHECK-LABEL: test_sf_vc_v_vvv_e64m4: 841; CHECK: # %bb.0: # %entry 842; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma 843; CHECK-NEXT: sf.vc.v.vvv 3, v8, v10, v12 844; CHECK-NEXT: ret 845entry: 846 %0 = tail call <4 x i64> @llvm.riscv.sf.vc.v.vvv.nxv4i64.iXLen.nxv4i64.iXLen(iXLen 3, <4 x i64> %vd, <4 x i64> %vs2, <4 x i64> %vs1, iXLen %vl) 847 ret <4 x i64> %0 848} 849 850declare <4 x i64> @llvm.riscv.sf.vc.v.vvv.nxv4i64.iXLen.nxv4i64.iXLen(iXLen, <4 x i64>, <4 x i64>, <4 x i64>, iXLen) 851 852define <8 x i64> @test_sf_vc_v_vvv_e64m8(<8 x i64> %vd, <8 x i64> %vs2, <8 x i64> %vs1, iXLen %vl) { 853; CHECK-LABEL: test_sf_vc_v_vvv_e64m8: 854; CHECK: # %bb.0: # %entry 855; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma 856; CHECK-NEXT: sf.vc.v.vvv 3, v8, v12, v16 857; CHECK-NEXT: ret 858entry: 859 %0 = tail call <8 x i64> @llvm.riscv.sf.vc.v.vvv.nxv8i64.iXLen.nxv8i64.iXLen(iXLen 3, <8 x i64> %vd, <8 x i64> %vs2, <8 x i64> %vs1, iXLen %vl) 860 ret <8 x i64> %0 861} 862 863declare <8 x i64> @llvm.riscv.sf.vc.v.vvv.nxv8i64.iXLen.nxv8i64.iXLen(iXLen, <8 x i64>, <8 x i64>, <8 x i64>, iXLen) 864 865define void @test_sf_vc_xvv_se_e8mf8(<1 x i8> %vd, <1 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 866; CHECK-LABEL: test_sf_vc_xvv_se_e8mf8: 867; CHECK: # %bb.0: # %entry 868; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma 869; CHECK-NEXT: sf.vc.xvv 3, v8, v9, a0 870; CHECK-NEXT: ret 871entry: 872 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv1i8.i8.iXLen(iXLen 3, <1 x i8> %vd, <1 x i8> %vs2, i8 %rs1, iXLen %vl) 873 ret void 874} 875 876declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv1i8.i8.iXLen(iXLen, <1 x i8>, <1 x i8>, i8, iXLen) 877 878define void @test_sf_vc_xvv_se_e8mf4(<2 x i8> %vd, <2 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 879; CHECK-LABEL: test_sf_vc_xvv_se_e8mf4: 880; CHECK: # %bb.0: # %entry 881; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma 882; CHECK-NEXT: sf.vc.xvv 3, v8, v9, a0 883; CHECK-NEXT: ret 884entry: 885 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv2i8.i8.iXLen(iXLen 3, <2 x i8> %vd, <2 x i8> %vs2, i8 %rs1, iXLen %vl) 886 ret void 887} 888 889declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv2i8.i8.iXLen(iXLen, <2 x i8>, <2 x i8>, i8, iXLen) 890 891define void @test_sf_vc_xvv_se_e8mf2(<4 x i8> %vd, <4 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 892; CHECK-LABEL: test_sf_vc_xvv_se_e8mf2: 893; CHECK: # %bb.0: # %entry 894; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma 895; CHECK-NEXT: sf.vc.xvv 3, v8, v9, a0 896; CHECK-NEXT: ret 897entry: 898 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv4i8.i8.iXLen(iXLen 3, <4 x i8> %vd, <4 x i8> %vs2, i8 %rs1, iXLen %vl) 899 ret void 900} 901 902declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv4i8.i8.iXLen(iXLen, <4 x i8>, <4 x i8>, i8, iXLen) 903 904define void @test_sf_vc_xvv_se_e8m1(<8 x i8> %vd, <8 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 905; CHECK-LABEL: test_sf_vc_xvv_se_e8m1: 906; CHECK: # %bb.0: # %entry 907; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma 908; CHECK-NEXT: sf.vc.xvv 3, v8, v9, a0 909; CHECK-NEXT: ret 910entry: 911 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv8i8.i8.iXLen(iXLen 3, <8 x i8> %vd, <8 x i8> %vs2, i8 %rs1, iXLen %vl) 912 ret void 913} 914 915declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv8i8.i8.iXLen(iXLen, <8 x i8>, <8 x i8>, i8, iXLen) 916 917define void @test_sf_vc_xvv_se_e8m2(<16 x i8> %vd, <16 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 918; CHECK-LABEL: test_sf_vc_xvv_se_e8m2: 919; CHECK: # %bb.0: # %entry 920; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma 921; CHECK-NEXT: sf.vc.xvv 3, v8, v9, a0 922; CHECK-NEXT: ret 923entry: 924 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv16i8.i8.iXLen(iXLen 3, <16 x i8> %vd, <16 x i8> %vs2, i8 %rs1, iXLen %vl) 925 ret void 926} 927 928declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv16i8.i8.iXLen(iXLen, <16 x i8>, <16 x i8>, i8, iXLen) 929 930define void @test_sf_vc_xvv_se_e8m4(<32 x i8> %vd, <32 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 931; CHECK-LABEL: test_sf_vc_xvv_se_e8m4: 932; CHECK: # %bb.0: # %entry 933; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma 934; CHECK-NEXT: sf.vc.xvv 3, v8, v10, a0 935; CHECK-NEXT: ret 936entry: 937 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv32i8.i8.iXLen(iXLen 3, <32 x i8> %vd, <32 x i8> %vs2, i8 %rs1, iXLen %vl) 938 ret void 939} 940 941declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv32i8.i8.iXLen(iXLen, <32 x i8>, <32 x i8>, i8, iXLen) 942 943define void @test_sf_vc_xvv_se_e8m8(<64 x i8> %vd, <64 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 944; CHECK-LABEL: test_sf_vc_xvv_se_e8m8: 945; CHECK: # %bb.0: # %entry 946; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma 947; CHECK-NEXT: sf.vc.xvv 3, v8, v12, a0 948; CHECK-NEXT: ret 949entry: 950 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv64i8.i8.iXLen(iXLen 3, <64 x i8> %vd, <64 x i8> %vs2, i8 %rs1, iXLen %vl) 951 ret void 952} 953 954declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv64i8.i8.iXLen(iXLen, <64 x i8>, <64 x i8>, i8, iXLen) 955 956define void @test_sf_vc_xvv_se_e16mf4(<1 x i16> %vd, <1 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) { 957; CHECK-LABEL: test_sf_vc_xvv_se_e16mf4: 958; CHECK: # %bb.0: # %entry 959; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma 960; CHECK-NEXT: sf.vc.xvv 3, v8, v9, a0 961; CHECK-NEXT: ret 962entry: 963 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv1i16.i16.iXLen(iXLen 3, <1 x i16> %vd, <1 x i16> %vs2, i16 %rs1, iXLen %vl) 964 ret void 965} 966 967declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv1i16.i16.iXLen(iXLen, <1 x i16>, <1 x i16>, i16, iXLen) 968 969define void @test_sf_vc_xvv_se_e16mf2(<2 x i16> %vd, <2 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) { 970; CHECK-LABEL: test_sf_vc_xvv_se_e16mf2: 971; CHECK: # %bb.0: # %entry 972; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma 973; CHECK-NEXT: sf.vc.xvv 3, v8, v9, a0 974; CHECK-NEXT: ret 975entry: 976 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv2i16.i16.iXLen(iXLen 3, <2 x i16> %vd, <2 x i16> %vs2, i16 %rs1, iXLen %vl) 977 ret void 978} 979 980declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv2i16.i16.iXLen(iXLen, <2 x i16>, <2 x i16>, i16, iXLen) 981 982define void @test_sf_vc_xvv_se_e16m1(<4 x i16> %vd, <4 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) { 983; CHECK-LABEL: test_sf_vc_xvv_se_e16m1: 984; CHECK: # %bb.0: # %entry 985; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma 986; CHECK-NEXT: sf.vc.xvv 3, v8, v9, a0 987; CHECK-NEXT: ret 988entry: 989 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv4i16.i16.iXLen(iXLen 3, <4 x i16> %vd, <4 x i16> %vs2, i16 %rs1, iXLen %vl) 990 ret void 991} 992 993declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv4i16.i16.iXLen(iXLen, <4 x i16>, <4 x i16>, i16, iXLen) 994 995define void @test_sf_vc_xvv_se_e16m2(<8 x i16> %vd, <8 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) { 996; CHECK-LABEL: test_sf_vc_xvv_se_e16m2: 997; CHECK: # %bb.0: # %entry 998; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma 999; CHECK-NEXT: sf.vc.xvv 3, v8, v9, a0 1000; CHECK-NEXT: ret 1001entry: 1002 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv8i16.i16.iXLen(iXLen 3, <8 x i16> %vd, <8 x i16> %vs2, i16 %rs1, iXLen %vl) 1003 ret void 1004} 1005 1006declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv8i16.i16.iXLen(iXLen, <8 x i16>, <8 x i16>, i16, iXLen) 1007 1008define void @test_sf_vc_xvv_se_e16m4(<16 x i16> %vd, <16 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) { 1009; CHECK-LABEL: test_sf_vc_xvv_se_e16m4: 1010; CHECK: # %bb.0: # %entry 1011; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma 1012; CHECK-NEXT: sf.vc.xvv 3, v8, v10, a0 1013; CHECK-NEXT: ret 1014entry: 1015 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv16i16.i16.iXLen(iXLen 3, <16 x i16> %vd, <16 x i16> %vs2, i16 %rs1, iXLen %vl) 1016 ret void 1017} 1018 1019declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv16i16.i16.iXLen(iXLen, <16 x i16>, <16 x i16>, i16, iXLen) 1020 1021define void @test_sf_vc_xvv_se_e16m8(<32 x i16> %vd, <32 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) { 1022; CHECK-LABEL: test_sf_vc_xvv_se_e16m8: 1023; CHECK: # %bb.0: # %entry 1024; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma 1025; CHECK-NEXT: sf.vc.xvv 3, v8, v12, a0 1026; CHECK-NEXT: ret 1027entry: 1028 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv32i16.i16.iXLen(iXLen 3, <32 x i16> %vd, <32 x i16> %vs2, i16 %rs1, iXLen %vl) 1029 ret void 1030} 1031 1032declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv32i16.i16.iXLen(iXLen, <32 x i16>, <32 x i16>, i16, iXLen) 1033 1034define void @test_sf_vc_xvv_se_e32mf2(<1 x i32> %vd, <1 x i32> %vs2, i32 signext %rs1, iXLen %vl) { 1035; CHECK-LABEL: test_sf_vc_xvv_se_e32mf2: 1036; CHECK: # %bb.0: # %entry 1037; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma 1038; CHECK-NEXT: sf.vc.xvv 3, v8, v9, a0 1039; CHECK-NEXT: ret 1040entry: 1041 tail call void @llvm.riscv.sf.vc.xvv.se.i32.nxv1i32.iXLen.iXLen(iXLen 3, <1 x i32> %vd, <1 x i32> %vs2, i32 %rs1, iXLen %vl) 1042 ret void 1043} 1044 1045declare void @llvm.riscv.sf.vc.xvv.se.i32.nxv1i32.iXLen.iXLen(iXLen, <1 x i32>, <1 x i32>, i32, iXLen) 1046 1047define void @test_sf_vc_xvv_se_e32m1(<2 x i32> %vd, <2 x i32> %vs2, i32 signext %rs1, iXLen %vl) { 1048; CHECK-LABEL: test_sf_vc_xvv_se_e32m1: 1049; CHECK: # %bb.0: # %entry 1050; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma 1051; CHECK-NEXT: sf.vc.xvv 3, v8, v9, a0 1052; CHECK-NEXT: ret 1053entry: 1054 tail call void @llvm.riscv.sf.vc.xvv.se.i32.nxv2i32.iXLen.iXLen(iXLen 3, <2 x i32> %vd, <2 x i32> %vs2, i32 %rs1, iXLen %vl) 1055 ret void 1056} 1057 1058declare void @llvm.riscv.sf.vc.xvv.se.i32.nxv2i32.iXLen.iXLen(iXLen, <2 x i32>, <2 x i32>, i32, iXLen) 1059 1060define void @test_sf_vc_xvv_se_e32m2(<4 x i32> %vd, <4 x i32> %vs2, i32 signext %rs1, iXLen %vl) { 1061; CHECK-LABEL: test_sf_vc_xvv_se_e32m2: 1062; CHECK: # %bb.0: # %entry 1063; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma 1064; CHECK-NEXT: sf.vc.xvv 3, v8, v9, a0 1065; CHECK-NEXT: ret 1066entry: 1067 tail call void @llvm.riscv.sf.vc.xvv.se.i32.nxv4i32.iXLen.iXLen(iXLen 3, <4 x i32> %vd, <4 x i32> %vs2, i32 %rs1, iXLen %vl) 1068 ret void 1069} 1070 1071declare void @llvm.riscv.sf.vc.xvv.se.i32.nxv4i32.iXLen.iXLen(iXLen, <4 x i32>, <4 x i32>, i32, iXLen) 1072 1073define void @test_sf_vc_xvv_se_e32m4(<8 x i32> %vd, <8 x i32> %vs2, i32 signext %rs1, iXLen %vl) { 1074; CHECK-LABEL: test_sf_vc_xvv_se_e32m4: 1075; CHECK: # %bb.0: # %entry 1076; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma 1077; CHECK-NEXT: sf.vc.xvv 3, v8, v10, a0 1078; CHECK-NEXT: ret 1079entry: 1080 tail call void @llvm.riscv.sf.vc.xvv.se.i32.nxv8i32.iXLen.iXLen(iXLen 3, <8 x i32> %vd, <8 x i32> %vs2, i32 %rs1, iXLen %vl) 1081 ret void 1082} 1083 1084declare void @llvm.riscv.sf.vc.xvv.se.i32.nxv8i32.iXLen.iXLen(iXLen, <8 x i32>, <8 x i32>, i32, iXLen) 1085 1086define void @test_sf_vc_xvv_se_e32m8(<16 x i32> %vd, <16 x i32> %vs2, i32 signext %rs1, iXLen %vl) { 1087; CHECK-LABEL: test_sf_vc_xvv_se_e32m8: 1088; CHECK: # %bb.0: # %entry 1089; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma 1090; CHECK-NEXT: sf.vc.xvv 3, v8, v12, a0 1091; CHECK-NEXT: ret 1092entry: 1093 tail call void @llvm.riscv.sf.vc.xvv.se.i32.nxv16i32.iXLen.iXLen(iXLen 3, <16 x i32> %vd, <16 x i32> %vs2, i32 %rs1, iXLen %vl) 1094 ret void 1095} 1096 1097declare void @llvm.riscv.sf.vc.xvv.se.i32.nxv16i32.iXLen.iXLen(iXLen, <16 x i32>, <16 x i32>, i32, iXLen) 1098 1099define <1 x i8> @test_sf_vc_v_xvv_se_e8mf8(<1 x i8> %vd, <1 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 1100; CHECK-LABEL: test_sf_vc_v_xvv_se_e8mf8: 1101; CHECK: # %bb.0: # %entry 1102; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, ma 1103; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1104; CHECK-NEXT: ret 1105entry: 1106 %0 = tail call <1 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv1i8.iXLen.i8.iXLen(iXLen 3, <1 x i8> %vd, <1 x i8> %vs2, i8 %rs1, iXLen %vl) 1107 ret <1 x i8> %0 1108} 1109 1110declare <1 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv1i8.iXLen.i8.iXLen(iXLen, <1 x i8>, <1 x i8>, i8, iXLen) 1111 1112define <2 x i8> @test_sf_vc_v_xvv_se_e8mf4(<2 x i8> %vd, <2 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 1113; CHECK-LABEL: test_sf_vc_v_xvv_se_e8mf4: 1114; CHECK: # %bb.0: # %entry 1115; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, ma 1116; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1117; CHECK-NEXT: ret 1118entry: 1119 %0 = tail call <2 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv2i8.iXLen.i8.iXLen(iXLen 3, <2 x i8> %vd, <2 x i8> %vs2, i8 %rs1, iXLen %vl) 1120 ret <2 x i8> %0 1121} 1122 1123declare <2 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv2i8.iXLen.i8.iXLen(iXLen, <2 x i8>, <2 x i8>, i8, iXLen) 1124 1125define <4 x i8> @test_sf_vc_v_xvv_se_e8mf2(<4 x i8> %vd, <4 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 1126; CHECK-LABEL: test_sf_vc_v_xvv_se_e8mf2: 1127; CHECK: # %bb.0: # %entry 1128; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, ma 1129; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1130; CHECK-NEXT: ret 1131entry: 1132 %0 = tail call <4 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv4i8.iXLen.i8.iXLen(iXLen 3, <4 x i8> %vd, <4 x i8> %vs2, i8 %rs1, iXLen %vl) 1133 ret <4 x i8> %0 1134} 1135 1136declare <4 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv4i8.iXLen.i8.iXLen(iXLen, <4 x i8>, <4 x i8>, i8, iXLen) 1137 1138define <8 x i8> @test_sf_vc_v_xvv_se_e8m1(<8 x i8> %vd, <8 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 1139; CHECK-LABEL: test_sf_vc_v_xvv_se_e8m1: 1140; CHECK: # %bb.0: # %entry 1141; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma 1142; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1143; CHECK-NEXT: ret 1144entry: 1145 %0 = tail call <8 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv8i8.iXLen.i8.iXLen(iXLen 3, <8 x i8> %vd, <8 x i8> %vs2, i8 %rs1, iXLen %vl) 1146 ret <8 x i8> %0 1147} 1148 1149declare <8 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv8i8.iXLen.i8.iXLen(iXLen, <8 x i8>, <8 x i8>, i8, iXLen) 1150 1151define <16 x i8> @test_sf_vc_v_xvv_se_e8m2(<16 x i8> %vd, <16 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 1152; CHECK-LABEL: test_sf_vc_v_xvv_se_e8m2: 1153; CHECK: # %bb.0: # %entry 1154; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma 1155; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1156; CHECK-NEXT: ret 1157entry: 1158 %0 = tail call <16 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv16i8.iXLen.i8.iXLen(iXLen 3, <16 x i8> %vd, <16 x i8> %vs2, i8 %rs1, iXLen %vl) 1159 ret <16 x i8> %0 1160} 1161 1162declare <16 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv16i8.iXLen.i8.iXLen(iXLen, <16 x i8>, <16 x i8>, i8, iXLen) 1163 1164define <32 x i8> @test_sf_vc_v_xvv_se_e8m4(<32 x i8> %vd, <32 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 1165; CHECK-LABEL: test_sf_vc_v_xvv_se_e8m4: 1166; CHECK: # %bb.0: # %entry 1167; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, ma 1168; CHECK-NEXT: sf.vc.v.xvv 3, v8, v10, a0 1169; CHECK-NEXT: ret 1170entry: 1171 %0 = tail call <32 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv32i8.iXLen.i8.iXLen(iXLen 3, <32 x i8> %vd, <32 x i8> %vs2, i8 %rs1, iXLen %vl) 1172 ret <32 x i8> %0 1173} 1174 1175declare <32 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv32i8.iXLen.i8.iXLen(iXLen, <32 x i8>, <32 x i8>, i8, iXLen) 1176 1177define <64 x i8> @test_sf_vc_v_xvv_se_e8m8(<64 x i8> %vd, <64 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 1178; CHECK-LABEL: test_sf_vc_v_xvv_se_e8m8: 1179; CHECK: # %bb.0: # %entry 1180; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, ma 1181; CHECK-NEXT: sf.vc.v.xvv 3, v8, v12, a0 1182; CHECK-NEXT: ret 1183entry: 1184 %0 = tail call <64 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv64i8.iXLen.i8.iXLen(iXLen 3, <64 x i8> %vd, <64 x i8> %vs2, i8 %rs1, iXLen %vl) 1185 ret <64 x i8> %0 1186} 1187 1188declare <64 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv64i8.iXLen.i8.iXLen(iXLen, <64 x i8>, <64 x i8>, i8, iXLen) 1189 1190define <1 x i16> @test_sf_vc_v_xvv_se_e16mf4(<1 x i16> %vd, <1 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) { 1191; CHECK-LABEL: test_sf_vc_v_xvv_se_e16mf4: 1192; CHECK: # %bb.0: # %entry 1193; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, ma 1194; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1195; CHECK-NEXT: ret 1196entry: 1197 %0 = tail call <1 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv1i16.iXLen.i16.iXLen(iXLen 3, <1 x i16> %vd, <1 x i16> %vs2, i16 %rs1, iXLen %vl) 1198 ret <1 x i16> %0 1199} 1200 1201declare <1 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv1i16.iXLen.i16.iXLen(iXLen, <1 x i16>, <1 x i16>, i16, iXLen) 1202 1203define <2 x i16> @test_sf_vc_v_xvv_se_e16mf2(<2 x i16> %vd, <2 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) { 1204; CHECK-LABEL: test_sf_vc_v_xvv_se_e16mf2: 1205; CHECK: # %bb.0: # %entry 1206; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, ma 1207; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1208; CHECK-NEXT: ret 1209entry: 1210 %0 = tail call <2 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv2i16.iXLen.i16.iXLen(iXLen 3, <2 x i16> %vd, <2 x i16> %vs2, i16 %rs1, iXLen %vl) 1211 ret <2 x i16> %0 1212} 1213 1214declare <2 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv2i16.iXLen.i16.iXLen(iXLen, <2 x i16>, <2 x i16>, i16, iXLen) 1215 1216define <4 x i16> @test_sf_vc_v_xvv_se_e16m1(<4 x i16> %vd, <4 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) { 1217; CHECK-LABEL: test_sf_vc_v_xvv_se_e16m1: 1218; CHECK: # %bb.0: # %entry 1219; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, ma 1220; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1221; CHECK-NEXT: ret 1222entry: 1223 %0 = tail call <4 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv4i16.iXLen.i16.iXLen(iXLen 3, <4 x i16> %vd, <4 x i16> %vs2, i16 %rs1, iXLen %vl) 1224 ret <4 x i16> %0 1225} 1226 1227declare <4 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv4i16.iXLen.i16.iXLen(iXLen, <4 x i16>, <4 x i16>, i16, iXLen) 1228 1229define <8 x i16> @test_sf_vc_v_xvv_se_e16m2(<8 x i16> %vd, <8 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) { 1230; CHECK-LABEL: test_sf_vc_v_xvv_se_e16m2: 1231; CHECK: # %bb.0: # %entry 1232; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma 1233; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1234; CHECK-NEXT: ret 1235entry: 1236 %0 = tail call <8 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv8i16.iXLen.i16.iXLen(iXLen 3, <8 x i16> %vd, <8 x i16> %vs2, i16 %rs1, iXLen %vl) 1237 ret <8 x i16> %0 1238} 1239 1240declare <8 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv8i16.iXLen.i16.iXLen(iXLen, <8 x i16>, <8 x i16>, i16, iXLen) 1241 1242define <16 x i16> @test_sf_vc_v_xvv_se_e16m4(<16 x i16> %vd, <16 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) { 1243; CHECK-LABEL: test_sf_vc_v_xvv_se_e16m4: 1244; CHECK: # %bb.0: # %entry 1245; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, ma 1246; CHECK-NEXT: sf.vc.v.xvv 3, v8, v10, a0 1247; CHECK-NEXT: ret 1248entry: 1249 %0 = tail call <16 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv16i16.iXLen.i16.iXLen(iXLen 3, <16 x i16> %vd, <16 x i16> %vs2, i16 %rs1, iXLen %vl) 1250 ret <16 x i16> %0 1251} 1252 1253declare <16 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv16i16.iXLen.i16.iXLen(iXLen, <16 x i16>, <16 x i16>, i16, iXLen) 1254 1255define <32 x i16> @test_sf_vc_v_xvv_se_e16m8(<32 x i16> %vd, <32 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) { 1256; CHECK-LABEL: test_sf_vc_v_xvv_se_e16m8: 1257; CHECK: # %bb.0: # %entry 1258; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, ma 1259; CHECK-NEXT: sf.vc.v.xvv 3, v8, v12, a0 1260; CHECK-NEXT: ret 1261entry: 1262 %0 = tail call <32 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv32i16.iXLen.i16.iXLen(iXLen 3, <32 x i16> %vd, <32 x i16> %vs2, i16 %rs1, iXLen %vl) 1263 ret <32 x i16> %0 1264} 1265 1266declare <32 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv32i16.iXLen.i16.iXLen(iXLen, <32 x i16>, <32 x i16>, i16, iXLen) 1267 1268define <1 x i32> @test_sf_vc_v_xvv_se_e32mf2(<1 x i32> %vd, <1 x i32> %vs2, i32 signext %rs1, iXLen %vl) { 1269; CHECK-LABEL: test_sf_vc_v_xvv_se_e32mf2: 1270; CHECK: # %bb.0: # %entry 1271; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma 1272; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1273; CHECK-NEXT: ret 1274entry: 1275 %0 = tail call <1 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv1i32.iXLen.i32.iXLen(iXLen 3, <1 x i32> %vd, <1 x i32> %vs2, i32 %rs1, iXLen %vl) 1276 ret <1 x i32> %0 1277} 1278 1279declare <1 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv1i32.iXLen.i32.iXLen(iXLen, <1 x i32>, <1 x i32>, i32, iXLen) 1280 1281define <2 x i32> @test_sf_vc_v_xvv_se_e32m1(<2 x i32> %vd, <2 x i32> %vs2, i32 signext %rs1, iXLen %vl) { 1282; CHECK-LABEL: test_sf_vc_v_xvv_se_e32m1: 1283; CHECK: # %bb.0: # %entry 1284; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma 1285; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1286; CHECK-NEXT: ret 1287entry: 1288 %0 = tail call <2 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv2i32.iXLen.i32.iXLen(iXLen 3, <2 x i32> %vd, <2 x i32> %vs2, i32 %rs1, iXLen %vl) 1289 ret <2 x i32> %0 1290} 1291 1292declare <2 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv2i32.iXLen.i32.iXLen(iXLen, <2 x i32>, <2 x i32>, i32, iXLen) 1293 1294define <4 x i32> @test_sf_vc_v_xvv_se_e32m2(<4 x i32> %vd, <4 x i32> %vs2, i32 signext %rs1, iXLen %vl) { 1295; CHECK-LABEL: test_sf_vc_v_xvv_se_e32m2: 1296; CHECK: # %bb.0: # %entry 1297; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma 1298; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1299; CHECK-NEXT: ret 1300entry: 1301 %0 = tail call <4 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv4i32.iXLen.i32.iXLen(iXLen 3, <4 x i32> %vd, <4 x i32> %vs2, i32 %rs1, iXLen %vl) 1302 ret <4 x i32> %0 1303} 1304 1305declare <4 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv4i32.iXLen.i32.iXLen(iXLen, <4 x i32>, <4 x i32>, i32, iXLen) 1306 1307define <8 x i32> @test_sf_vc_v_xvv_se_e32m4(<8 x i32> %vd, <8 x i32> %vs2, i32 signext %rs1, iXLen %vl) { 1308; CHECK-LABEL: test_sf_vc_v_xvv_se_e32m4: 1309; CHECK: # %bb.0: # %entry 1310; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma 1311; CHECK-NEXT: sf.vc.v.xvv 3, v8, v10, a0 1312; CHECK-NEXT: ret 1313entry: 1314 %0 = tail call <8 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv8i32.iXLen.i32.iXLen(iXLen 3, <8 x i32> %vd, <8 x i32> %vs2, i32 %rs1, iXLen %vl) 1315 ret <8 x i32> %0 1316} 1317 1318declare <8 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv8i32.iXLen.i32.iXLen(iXLen, <8 x i32>, <8 x i32>, i32, iXLen) 1319 1320define <16 x i32> @test_sf_vc_v_xvv_se_e32m8(<16 x i32> %vd, <16 x i32> %vs2, i32 signext %rs1, iXLen %vl) { 1321; CHECK-LABEL: test_sf_vc_v_xvv_se_e32m8: 1322; CHECK: # %bb.0: # %entry 1323; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma 1324; CHECK-NEXT: sf.vc.v.xvv 3, v8, v12, a0 1325; CHECK-NEXT: ret 1326entry: 1327 %0 = tail call <16 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv16i32.iXLen.i32.iXLen(iXLen 3, <16 x i32> %vd, <16 x i32> %vs2, i32 %rs1, iXLen %vl) 1328 ret <16 x i32> %0 1329} 1330 1331declare <16 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv16i32.iXLen.i32.iXLen(iXLen, <16 x i32>, <16 x i32>, i32, iXLen) 1332 1333define <1 x i8> @test_sf_vc_v_xvv_e8mf8(<1 x i8> %vd, <1 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 1334; CHECK-LABEL: test_sf_vc_v_xvv_e8mf8: 1335; CHECK: # %bb.0: # %entry 1336; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, ma 1337; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1338; CHECK-NEXT: ret 1339entry: 1340 %0 = tail call <1 x i8> @llvm.riscv.sf.vc.v.xvv.nxv1i8.iXLen.i8.iXLen(iXLen 3, <1 x i8> %vd, <1 x i8> %vs2, i8 %rs1, iXLen %vl) 1341 ret <1 x i8> %0 1342} 1343 1344declare <1 x i8> @llvm.riscv.sf.vc.v.xvv.nxv1i8.iXLen.i8.iXLen(iXLen, <1 x i8>, <1 x i8>, i8, iXLen) 1345 1346define <2 x i8> @test_sf_vc_v_xvv_e8mf4(<2 x i8> %vd, <2 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 1347; CHECK-LABEL: test_sf_vc_v_xvv_e8mf4: 1348; CHECK: # %bb.0: # %entry 1349; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, ma 1350; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1351; CHECK-NEXT: ret 1352entry: 1353 %0 = tail call <2 x i8> @llvm.riscv.sf.vc.v.xvv.nxv2i8.iXLen.i8.iXLen(iXLen 3, <2 x i8> %vd, <2 x i8> %vs2, i8 %rs1, iXLen %vl) 1354 ret <2 x i8> %0 1355} 1356 1357declare <2 x i8> @llvm.riscv.sf.vc.v.xvv.nxv2i8.iXLen.i8.iXLen(iXLen, <2 x i8>, <2 x i8>, i8, iXLen) 1358 1359define <4 x i8> @test_sf_vc_v_xvv_e8mf2(<4 x i8> %vd, <4 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 1360; CHECK-LABEL: test_sf_vc_v_xvv_e8mf2: 1361; CHECK: # %bb.0: # %entry 1362; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, ma 1363; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1364; CHECK-NEXT: ret 1365entry: 1366 %0 = tail call <4 x i8> @llvm.riscv.sf.vc.v.xvv.nxv4i8.iXLen.i8.iXLen(iXLen 3, <4 x i8> %vd, <4 x i8> %vs2, i8 %rs1, iXLen %vl) 1367 ret <4 x i8> %0 1368} 1369 1370declare <4 x i8> @llvm.riscv.sf.vc.v.xvv.nxv4i8.iXLen.i8.iXLen(iXLen, <4 x i8>, <4 x i8>, i8, iXLen) 1371 1372define <8 x i8> @test_sf_vc_v_xvv_e8m1(<8 x i8> %vd, <8 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 1373; CHECK-LABEL: test_sf_vc_v_xvv_e8m1: 1374; CHECK: # %bb.0: # %entry 1375; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma 1376; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1377; CHECK-NEXT: ret 1378entry: 1379 %0 = tail call <8 x i8> @llvm.riscv.sf.vc.v.xvv.nxv8i8.iXLen.i8.iXLen(iXLen 3, <8 x i8> %vd, <8 x i8> %vs2, i8 %rs1, iXLen %vl) 1380 ret <8 x i8> %0 1381} 1382 1383declare <8 x i8> @llvm.riscv.sf.vc.v.xvv.nxv8i8.iXLen.i8.iXLen(iXLen, <8 x i8>, <8 x i8>, i8, iXLen) 1384 1385define <16 x i8> @test_sf_vc_v_xvv_e8m2(<16 x i8> %vd, <16 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 1386; CHECK-LABEL: test_sf_vc_v_xvv_e8m2: 1387; CHECK: # %bb.0: # %entry 1388; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma 1389; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1390; CHECK-NEXT: ret 1391entry: 1392 %0 = tail call <16 x i8> @llvm.riscv.sf.vc.v.xvv.nxv16i8.iXLen.i8.iXLen(iXLen 3, <16 x i8> %vd, <16 x i8> %vs2, i8 %rs1, iXLen %vl) 1393 ret <16 x i8> %0 1394} 1395 1396declare <16 x i8> @llvm.riscv.sf.vc.v.xvv.nxv16i8.iXLen.i8.iXLen(iXLen, <16 x i8>, <16 x i8>, i8, iXLen) 1397 1398define <32 x i8> @test_sf_vc_v_xvv_e8m4(<32 x i8> %vd, <32 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 1399; CHECK-LABEL: test_sf_vc_v_xvv_e8m4: 1400; CHECK: # %bb.0: # %entry 1401; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, ma 1402; CHECK-NEXT: sf.vc.v.xvv 3, v8, v10, a0 1403; CHECK-NEXT: ret 1404entry: 1405 %0 = tail call <32 x i8> @llvm.riscv.sf.vc.v.xvv.nxv32i8.iXLen.i8.iXLen(iXLen 3, <32 x i8> %vd, <32 x i8> %vs2, i8 %rs1, iXLen %vl) 1406 ret <32 x i8> %0 1407} 1408 1409declare <32 x i8> @llvm.riscv.sf.vc.v.xvv.nxv32i8.iXLen.i8.iXLen(iXLen, <32 x i8>, <32 x i8>, i8, iXLen) 1410 1411define <64 x i8> @test_sf_vc_v_xvv_e8m8(<64 x i8> %vd, <64 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) { 1412; CHECK-LABEL: test_sf_vc_v_xvv_e8m8: 1413; CHECK: # %bb.0: # %entry 1414; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, ma 1415; CHECK-NEXT: sf.vc.v.xvv 3, v8, v12, a0 1416; CHECK-NEXT: ret 1417entry: 1418 %0 = tail call <64 x i8> @llvm.riscv.sf.vc.v.xvv.nxv64i8.iXLen.i8.iXLen(iXLen 3, <64 x i8> %vd, <64 x i8> %vs2, i8 %rs1, iXLen %vl) 1419 ret <64 x i8> %0 1420} 1421 1422declare <64 x i8> @llvm.riscv.sf.vc.v.xvv.nxv64i8.iXLen.i8.iXLen(iXLen, <64 x i8>, <64 x i8>, i8, iXLen) 1423 1424define <1 x i16> @test_sf_vc_v_xvv_e16mf4(<1 x i16> %vd, <1 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) { 1425; CHECK-LABEL: test_sf_vc_v_xvv_e16mf4: 1426; CHECK: # %bb.0: # %entry 1427; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, ma 1428; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1429; CHECK-NEXT: ret 1430entry: 1431 %0 = tail call <1 x i16> @llvm.riscv.sf.vc.v.xvv.nxv1i16.iXLen.i16.iXLen(iXLen 3, <1 x i16> %vd, <1 x i16> %vs2, i16 %rs1, iXLen %vl) 1432 ret <1 x i16> %0 1433} 1434 1435declare <1 x i16> @llvm.riscv.sf.vc.v.xvv.nxv1i16.iXLen.i16.iXLen(iXLen, <1 x i16>, <1 x i16>, i16, iXLen) 1436 1437define <2 x i16> @test_sf_vc_v_xvv_e16mf2(<2 x i16> %vd, <2 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) { 1438; CHECK-LABEL: test_sf_vc_v_xvv_e16mf2: 1439; CHECK: # %bb.0: # %entry 1440; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, ma 1441; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1442; CHECK-NEXT: ret 1443entry: 1444 %0 = tail call <2 x i16> @llvm.riscv.sf.vc.v.xvv.nxv2i16.iXLen.i16.iXLen(iXLen 3, <2 x i16> %vd, <2 x i16> %vs2, i16 %rs1, iXLen %vl) 1445 ret <2 x i16> %0 1446} 1447 1448declare <2 x i16> @llvm.riscv.sf.vc.v.xvv.nxv2i16.iXLen.i16.iXLen(iXLen, <2 x i16>, <2 x i16>, i16, iXLen) 1449 1450define <4 x i16> @test_sf_vc_v_xvv_e16m1(<4 x i16> %vd, <4 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) { 1451; CHECK-LABEL: test_sf_vc_v_xvv_e16m1: 1452; CHECK: # %bb.0: # %entry 1453; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, ma 1454; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1455; CHECK-NEXT: ret 1456entry: 1457 %0 = tail call <4 x i16> @llvm.riscv.sf.vc.v.xvv.nxv4i16.iXLen.i16.iXLen(iXLen 3, <4 x i16> %vd, <4 x i16> %vs2, i16 %rs1, iXLen %vl) 1458 ret <4 x i16> %0 1459} 1460 1461declare <4 x i16> @llvm.riscv.sf.vc.v.xvv.nxv4i16.iXLen.i16.iXLen(iXLen, <4 x i16>, <4 x i16>, i16, iXLen) 1462 1463define <8 x i16> @test_sf_vc_v_xvv_e16m2(<8 x i16> %vd, <8 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) { 1464; CHECK-LABEL: test_sf_vc_v_xvv_e16m2: 1465; CHECK: # %bb.0: # %entry 1466; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma 1467; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1468; CHECK-NEXT: ret 1469entry: 1470 %0 = tail call <8 x i16> @llvm.riscv.sf.vc.v.xvv.nxv8i16.iXLen.i16.iXLen(iXLen 3, <8 x i16> %vd, <8 x i16> %vs2, i16 %rs1, iXLen %vl) 1471 ret <8 x i16> %0 1472} 1473 1474declare <8 x i16> @llvm.riscv.sf.vc.v.xvv.nxv8i16.iXLen.i16.iXLen(iXLen, <8 x i16>, <8 x i16>, i16, iXLen) 1475 1476define <16 x i16> @test_sf_vc_v_xvv_e16m4(<16 x i16> %vd, <16 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) { 1477; CHECK-LABEL: test_sf_vc_v_xvv_e16m4: 1478; CHECK: # %bb.0: # %entry 1479; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, ma 1480; CHECK-NEXT: sf.vc.v.xvv 3, v8, v10, a0 1481; CHECK-NEXT: ret 1482entry: 1483 %0 = tail call <16 x i16> @llvm.riscv.sf.vc.v.xvv.nxv16i16.iXLen.i16.iXLen(iXLen 3, <16 x i16> %vd, <16 x i16> %vs2, i16 %rs1, iXLen %vl) 1484 ret <16 x i16> %0 1485} 1486 1487declare <16 x i16> @llvm.riscv.sf.vc.v.xvv.nxv16i16.iXLen.i16.iXLen(iXLen, <16 x i16>, <16 x i16>, i16, iXLen) 1488 1489define <32 x i16> @test_sf_vc_v_xvv_e16m8(<32 x i16> %vd, <32 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) { 1490; CHECK-LABEL: test_sf_vc_v_xvv_e16m8: 1491; CHECK: # %bb.0: # %entry 1492; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, ma 1493; CHECK-NEXT: sf.vc.v.xvv 3, v8, v12, a0 1494; CHECK-NEXT: ret 1495entry: 1496 %0 = tail call <32 x i16> @llvm.riscv.sf.vc.v.xvv.nxv32i16.iXLen.i16.iXLen(iXLen 3, <32 x i16> %vd, <32 x i16> %vs2, i16 %rs1, iXLen %vl) 1497 ret <32 x i16> %0 1498} 1499 1500declare <32 x i16> @llvm.riscv.sf.vc.v.xvv.nxv32i16.iXLen.i16.iXLen(iXLen, <32 x i16>, <32 x i16>, i16, iXLen) 1501 1502define <1 x i32> @test_sf_vc_v_xvv_e32mf2(<1 x i32> %vd, <1 x i32> %vs2, i32 signext %rs1, iXLen %vl) { 1503; CHECK-LABEL: test_sf_vc_v_xvv_e32mf2: 1504; CHECK: # %bb.0: # %entry 1505; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma 1506; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1507; CHECK-NEXT: ret 1508entry: 1509 %0 = tail call <1 x i32> @llvm.riscv.sf.vc.v.xvv.nxv1i32.iXLen.i32.iXLen(iXLen 3, <1 x i32> %vd, <1 x i32> %vs2, i32 %rs1, iXLen %vl) 1510 ret <1 x i32> %0 1511} 1512 1513declare <1 x i32> @llvm.riscv.sf.vc.v.xvv.nxv1i32.iXLen.i32.iXLen(iXLen, <1 x i32>, <1 x i32>, i32, iXLen) 1514 1515define <2 x i32> @test_sf_vc_v_xvv_e32m1(<2 x i32> %vd, <2 x i32> %vs2, i32 signext %rs1, iXLen %vl) { 1516; CHECK-LABEL: test_sf_vc_v_xvv_e32m1: 1517; CHECK: # %bb.0: # %entry 1518; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma 1519; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1520; CHECK-NEXT: ret 1521entry: 1522 %0 = tail call <2 x i32> @llvm.riscv.sf.vc.v.xvv.nxv2i32.iXLen.i32.iXLen(iXLen 3, <2 x i32> %vd, <2 x i32> %vs2, i32 %rs1, iXLen %vl) 1523 ret <2 x i32> %0 1524} 1525 1526declare <2 x i32> @llvm.riscv.sf.vc.v.xvv.nxv2i32.iXLen.i32.iXLen(iXLen, <2 x i32>, <2 x i32>, i32, iXLen) 1527 1528define <4 x i32> @test_sf_vc_v_xvv_e32m2(<4 x i32> %vd, <4 x i32> %vs2, i32 signext %rs1, iXLen %vl) { 1529; CHECK-LABEL: test_sf_vc_v_xvv_e32m2: 1530; CHECK: # %bb.0: # %entry 1531; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma 1532; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 1533; CHECK-NEXT: ret 1534entry: 1535 %0 = tail call <4 x i32> @llvm.riscv.sf.vc.v.xvv.nxv4i32.iXLen.i32.iXLen(iXLen 3, <4 x i32> %vd, <4 x i32> %vs2, i32 %rs1, iXLen %vl) 1536 ret <4 x i32> %0 1537} 1538 1539declare <4 x i32> @llvm.riscv.sf.vc.v.xvv.nxv4i32.iXLen.i32.iXLen(iXLen, <4 x i32>, <4 x i32>, i32, iXLen) 1540 1541define <8 x i32> @test_sf_vc_v_xvv_e32m4(<8 x i32> %vd, <8 x i32> %vs2, i32 signext %rs1, iXLen %vl) { 1542; CHECK-LABEL: test_sf_vc_v_xvv_e32m4: 1543; CHECK: # %bb.0: # %entry 1544; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma 1545; CHECK-NEXT: sf.vc.v.xvv 3, v8, v10, a0 1546; CHECK-NEXT: ret 1547entry: 1548 %0 = tail call <8 x i32> @llvm.riscv.sf.vc.v.xvv.nxv8i32.iXLen.i32.iXLen(iXLen 3, <8 x i32> %vd, <8 x i32> %vs2, i32 %rs1, iXLen %vl) 1549 ret <8 x i32> %0 1550} 1551 1552declare <8 x i32> @llvm.riscv.sf.vc.v.xvv.nxv8i32.iXLen.i32.iXLen(iXLen, <8 x i32>, <8 x i32>, i32, iXLen) 1553 1554define <16 x i32> @test_sf_vc_v_xvv_e32m8(<16 x i32> %vd, <16 x i32> %vs2, i32 signext %rs1, iXLen %vl) { 1555; CHECK-LABEL: test_sf_vc_v_xvv_e32m8: 1556; CHECK: # %bb.0: # %entry 1557; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma 1558; CHECK-NEXT: sf.vc.v.xvv 3, v8, v12, a0 1559; CHECK-NEXT: ret 1560entry: 1561 %0 = tail call <16 x i32> @llvm.riscv.sf.vc.v.xvv.nxv16i32.iXLen.i32.iXLen(iXLen 3, <16 x i32> %vd, <16 x i32> %vs2, i32 %rs1, iXLen %vl) 1562 ret <16 x i32> %0 1563} 1564 1565declare <16 x i32> @llvm.riscv.sf.vc.v.xvv.nxv16i32.iXLen.i32.iXLen(iXLen, <16 x i32>, <16 x i32>, i32, iXLen) 1566 1567define void @test_sf_vc_ivv_se_e8mf8(<1 x i8> %vd, <1 x i8> %vs2, iXLen %vl) { 1568; CHECK-LABEL: test_sf_vc_ivv_se_e8mf8: 1569; CHECK: # %bb.0: # %entry 1570; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma 1571; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 10 1572; CHECK-NEXT: ret 1573entry: 1574 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv1i8.iXLen.iXLen(iXLen 3, <1 x i8> %vd, <1 x i8> %vs2, iXLen 10, iXLen %vl) 1575 ret void 1576} 1577 1578declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv1i8.iXLen.iXLen(iXLen, <1 x i8>, <1 x i8>, iXLen, iXLen) 1579 1580define void @test_sf_vc_ivv_se_e8mf4(<2 x i8> %vd, <2 x i8> %vs2, iXLen %vl) { 1581; CHECK-LABEL: test_sf_vc_ivv_se_e8mf4: 1582; CHECK: # %bb.0: # %entry 1583; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma 1584; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 10 1585; CHECK-NEXT: ret 1586entry: 1587 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv2i8.iXLen.iXLen(iXLen 3, <2 x i8> %vd, <2 x i8> %vs2, iXLen 10, iXLen %vl) 1588 ret void 1589} 1590 1591declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv2i8.iXLen.iXLen(iXLen, <2 x i8>, <2 x i8>, iXLen, iXLen) 1592 1593define void @test_sf_vc_ivv_se_e8mf2(<4 x i8> %vd, <4 x i8> %vs2, iXLen %vl) { 1594; CHECK-LABEL: test_sf_vc_ivv_se_e8mf2: 1595; CHECK: # %bb.0: # %entry 1596; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma 1597; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 10 1598; CHECK-NEXT: ret 1599entry: 1600 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv4i8.iXLen.iXLen(iXLen 3, <4 x i8> %vd, <4 x i8> %vs2, iXLen 10, iXLen %vl) 1601 ret void 1602} 1603 1604declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv4i8.iXLen.iXLen(iXLen, <4 x i8>, <4 x i8>, iXLen, iXLen) 1605 1606define void @test_sf_vc_ivv_se_e8m1(<8 x i8> %vd, <8 x i8> %vs2, iXLen %vl) { 1607; CHECK-LABEL: test_sf_vc_ivv_se_e8m1: 1608; CHECK: # %bb.0: # %entry 1609; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma 1610; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 10 1611; CHECK-NEXT: ret 1612entry: 1613 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv8i8.iXLen.iXLen(iXLen 3, <8 x i8> %vd, <8 x i8> %vs2, iXLen 10, iXLen %vl) 1614 ret void 1615} 1616 1617declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv8i8.iXLen.iXLen(iXLen, <8 x i8>, <8 x i8>, iXLen, iXLen) 1618 1619define void @test_sf_vc_ivv_se_e8m2(<16 x i8> %vd, <16 x i8> %vs2, iXLen %vl) { 1620; CHECK-LABEL: test_sf_vc_ivv_se_e8m2: 1621; CHECK: # %bb.0: # %entry 1622; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma 1623; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 10 1624; CHECK-NEXT: ret 1625entry: 1626 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv16i8.iXLen.iXLen(iXLen 3, <16 x i8> %vd, <16 x i8> %vs2, iXLen 10, iXLen %vl) 1627 ret void 1628} 1629 1630declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv16i8.iXLen.iXLen(iXLen, <16 x i8>, <16 x i8>, iXLen, iXLen) 1631 1632define void @test_sf_vc_ivv_se_e8m4(<32 x i8> %vd, <32 x i8> %vs2, iXLen %vl) { 1633; CHECK-LABEL: test_sf_vc_ivv_se_e8m4: 1634; CHECK: # %bb.0: # %entry 1635; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma 1636; CHECK-NEXT: sf.vc.ivv 3, v8, v10, 10 1637; CHECK-NEXT: ret 1638entry: 1639 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv32i8.iXLen.iXLen(iXLen 3, <32 x i8> %vd, <32 x i8> %vs2, iXLen 10, iXLen %vl) 1640 ret void 1641} 1642 1643declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv32i8.iXLen.iXLen(iXLen, <32 x i8>, <32 x i8>, iXLen, iXLen) 1644 1645define void @test_sf_vc_ivv_se_e8m8(<64 x i8> %vd, <64 x i8> %vs2, iXLen %vl) { 1646; CHECK-LABEL: test_sf_vc_ivv_se_e8m8: 1647; CHECK: # %bb.0: # %entry 1648; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma 1649; CHECK-NEXT: sf.vc.ivv 3, v8, v12, 10 1650; CHECK-NEXT: ret 1651entry: 1652 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv64i8.iXLen.iXLen(iXLen 3, <64 x i8> %vd, <64 x i8> %vs2, iXLen 10, iXLen %vl) 1653 ret void 1654} 1655 1656declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv64i8.iXLen.iXLen(iXLen, <64 x i8>, <64 x i8>, iXLen, iXLen) 1657 1658define void @test_sf_vc_ivv_se_e16mf4(<1 x i16> %vd, <1 x i16> %vs2, iXLen %vl) { 1659; CHECK-LABEL: test_sf_vc_ivv_se_e16mf4: 1660; CHECK: # %bb.0: # %entry 1661; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma 1662; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 10 1663; CHECK-NEXT: ret 1664entry: 1665 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv1i16.iXLen.iXLen(iXLen 3, <1 x i16> %vd, <1 x i16> %vs2, iXLen 10, iXLen %vl) 1666 ret void 1667} 1668 1669declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv1i16.iXLen.iXLen(iXLen, <1 x i16>, <1 x i16>, iXLen, iXLen) 1670 1671define void @test_sf_vc_ivv_se_e16mf2(<2 x i16> %vd, <2 x i16> %vs2, iXLen %vl) { 1672; CHECK-LABEL: test_sf_vc_ivv_se_e16mf2: 1673; CHECK: # %bb.0: # %entry 1674; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma 1675; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 10 1676; CHECK-NEXT: ret 1677entry: 1678 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv2i16.iXLen.iXLen(iXLen 3, <2 x i16> %vd, <2 x i16> %vs2, iXLen 10, iXLen %vl) 1679 ret void 1680} 1681 1682declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv2i16.iXLen.iXLen(iXLen, <2 x i16>, <2 x i16>, iXLen, iXLen) 1683 1684define void @test_sf_vc_ivv_se_e16m1(<4 x i16> %vd, <4 x i16> %vs2, iXLen %vl) { 1685; CHECK-LABEL: test_sf_vc_ivv_se_e16m1: 1686; CHECK: # %bb.0: # %entry 1687; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 1688; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 10 1689; CHECK-NEXT: ret 1690entry: 1691 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv4i16.iXLen.iXLen(iXLen 3, <4 x i16> %vd, <4 x i16> %vs2, iXLen 10, iXLen %vl) 1692 ret void 1693} 1694 1695declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv4i16.iXLen.iXLen(iXLen, <4 x i16>, <4 x i16>, iXLen, iXLen) 1696 1697define void @test_sf_vc_ivv_se_e16m2(<8 x i16> %vd, <8 x i16> %vs2, iXLen %vl) { 1698; CHECK-LABEL: test_sf_vc_ivv_se_e16m2: 1699; CHECK: # %bb.0: # %entry 1700; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma 1701; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 10 1702; CHECK-NEXT: ret 1703entry: 1704 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv8i16.iXLen.iXLen(iXLen 3, <8 x i16> %vd, <8 x i16> %vs2, iXLen 10, iXLen %vl) 1705 ret void 1706} 1707 1708declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv8i16.iXLen.iXLen(iXLen, <8 x i16>, <8 x i16>, iXLen, iXLen) 1709 1710define void @test_sf_vc_ivv_se_e16m4(<16 x i16> %vd, <16 x i16> %vs2, iXLen %vl) { 1711; CHECK-LABEL: test_sf_vc_ivv_se_e16m4: 1712; CHECK: # %bb.0: # %entry 1713; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma 1714; CHECK-NEXT: sf.vc.ivv 3, v8, v10, 10 1715; CHECK-NEXT: ret 1716entry: 1717 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv16i16.iXLen.iXLen(iXLen 3, <16 x i16> %vd, <16 x i16> %vs2, iXLen 10, iXLen %vl) 1718 ret void 1719} 1720 1721declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv16i16.iXLen.iXLen(iXLen, <16 x i16>, <16 x i16>, iXLen, iXLen) 1722 1723define void @test_sf_vc_ivv_se_e16m8(<32 x i16> %vd, <32 x i16> %vs2, iXLen %vl) { 1724; CHECK-LABEL: test_sf_vc_ivv_se_e16m8: 1725; CHECK: # %bb.0: # %entry 1726; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma 1727; CHECK-NEXT: sf.vc.ivv 3, v8, v12, 10 1728; CHECK-NEXT: ret 1729entry: 1730 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv32i16.iXLen.iXLen(iXLen 3, <32 x i16> %vd, <32 x i16> %vs2, iXLen 10, iXLen %vl) 1731 ret void 1732} 1733 1734declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv32i16.iXLen.iXLen(iXLen, <32 x i16>, <32 x i16>, iXLen, iXLen) 1735 1736define void @test_sf_vc_ivv_se_e32mf2(<1 x i32> %vd, <1 x i32> %vs2, iXLen %vl) { 1737; CHECK-LABEL: test_sf_vc_ivv_se_e32mf2: 1738; CHECK: # %bb.0: # %entry 1739; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma 1740; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 10 1741; CHECK-NEXT: ret 1742entry: 1743 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv1i32.iXLen.iXLen(iXLen 3, <1 x i32> %vd, <1 x i32> %vs2, iXLen 10, iXLen %vl) 1744 ret void 1745} 1746 1747declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv1i32.iXLen.iXLen(iXLen, <1 x i32>, <1 x i32>, iXLen, iXLen) 1748 1749define void @test_sf_vc_ivv_se_e32m1(<2 x i32> %vd, <2 x i32> %vs2, iXLen %vl) { 1750; CHECK-LABEL: test_sf_vc_ivv_se_e32m1: 1751; CHECK: # %bb.0: # %entry 1752; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma 1753; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 10 1754; CHECK-NEXT: ret 1755entry: 1756 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv2i32.iXLen.iXLen(iXLen 3, <2 x i32> %vd, <2 x i32> %vs2, iXLen 10, iXLen %vl) 1757 ret void 1758} 1759 1760declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv2i32.iXLen.iXLen(iXLen, <2 x i32>, <2 x i32>, iXLen, iXLen) 1761 1762define void @test_sf_vc_ivv_se_e32m2(<4 x i32> %vd, <4 x i32> %vs2, iXLen %vl) { 1763; CHECK-LABEL: test_sf_vc_ivv_se_e32m2: 1764; CHECK: # %bb.0: # %entry 1765; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 1766; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 10 1767; CHECK-NEXT: ret 1768entry: 1769 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv4i32.iXLen.iXLen(iXLen 3, <4 x i32> %vd, <4 x i32> %vs2, iXLen 10, iXLen %vl) 1770 ret void 1771} 1772 1773declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv4i32.iXLen.iXLen(iXLen, <4 x i32>, <4 x i32>, iXLen, iXLen) 1774 1775define void @test_sf_vc_ivv_se_e32m4(<8 x i32> %vd, <8 x i32> %vs2, iXLen %vl) { 1776; CHECK-LABEL: test_sf_vc_ivv_se_e32m4: 1777; CHECK: # %bb.0: # %entry 1778; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma 1779; CHECK-NEXT: sf.vc.ivv 3, v8, v10, 10 1780; CHECK-NEXT: ret 1781entry: 1782 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv8i32.iXLen.iXLen(iXLen 3, <8 x i32> %vd, <8 x i32> %vs2, iXLen 10, iXLen %vl) 1783 ret void 1784} 1785 1786declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv8i32.iXLen.iXLen(iXLen, <8 x i32>, <8 x i32>, iXLen, iXLen) 1787 1788define void @test_sf_vc_ivv_se_e32m8(<16 x i32> %vd, <16 x i32> %vs2, iXLen %vl) { 1789; CHECK-LABEL: test_sf_vc_ivv_se_e32m8: 1790; CHECK: # %bb.0: # %entry 1791; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma 1792; CHECK-NEXT: sf.vc.ivv 3, v8, v12, 10 1793; CHECK-NEXT: ret 1794entry: 1795 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv16i32.iXLen.iXLen(iXLen 3, <16 x i32> %vd, <16 x i32> %vs2, iXLen 10, iXLen %vl) 1796 ret void 1797} 1798 1799declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv16i32.iXLen.iXLen(iXLen, <16 x i32>, <16 x i32>, iXLen, iXLen) 1800 1801define void @test_sf_vc_ivv_se_e64m1(<1 x i64> %vd, <1 x i64> %vs2, iXLen %vl) { 1802; CHECK-LABEL: test_sf_vc_ivv_se_e64m1: 1803; CHECK: # %bb.0: # %entry 1804; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma 1805; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 10 1806; CHECK-NEXT: ret 1807entry: 1808 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv1i64.iXLen.iXLen(iXLen 3, <1 x i64> %vd, <1 x i64> %vs2, iXLen 10, iXLen %vl) 1809 ret void 1810} 1811 1812declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv1i64.iXLen.iXLen(iXLen, <1 x i64>, <1 x i64>, iXLen, iXLen) 1813 1814define void @test_sf_vc_ivv_se_e64m2(<2 x i64> %vd, <2 x i64> %vs2, iXLen %vl) { 1815; CHECK-LABEL: test_sf_vc_ivv_se_e64m2: 1816; CHECK: # %bb.0: # %entry 1817; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma 1818; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 10 1819; CHECK-NEXT: ret 1820entry: 1821 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv2i64.iXLen.iXLen(iXLen 3, <2 x i64> %vd, <2 x i64> %vs2, iXLen 10, iXLen %vl) 1822 ret void 1823} 1824 1825declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv2i64.iXLen.iXLen(iXLen, <2 x i64>, <2 x i64>, iXLen, iXLen) 1826 1827define void @test_sf_vc_ivv_se_e64m4(<4 x i64> %vd, <4 x i64> %vs2, iXLen %vl) { 1828; CHECK-LABEL: test_sf_vc_ivv_se_e64m4: 1829; CHECK: # %bb.0: # %entry 1830; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma 1831; CHECK-NEXT: sf.vc.ivv 3, v8, v10, 10 1832; CHECK-NEXT: ret 1833entry: 1834 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv4i64.iXLen.iXLen(iXLen 3, <4 x i64> %vd, <4 x i64> %vs2, iXLen 10, iXLen %vl) 1835 ret void 1836} 1837 1838declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv4i64.iXLen.iXLen(iXLen, <4 x i64>, <4 x i64>, iXLen, iXLen) 1839 1840define void @test_sf_vc_ivv_se_e64m8(<8 x i64> %vd, <8 x i64> %vs2, iXLen %vl) { 1841; CHECK-LABEL: test_sf_vc_ivv_se_e64m8: 1842; CHECK: # %bb.0: # %entry 1843; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma 1844; CHECK-NEXT: sf.vc.ivv 3, v8, v12, 10 1845; CHECK-NEXT: ret 1846entry: 1847 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv8i64.iXLen.iXLen(iXLen 3, <8 x i64> %vd, <8 x i64> %vs2, iXLen 10, iXLen %vl) 1848 ret void 1849} 1850 1851declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv8i64.iXLen.iXLen(iXLen, <8 x i64>, <8 x i64>, iXLen, iXLen) 1852 1853define <1 x i8> @test_sf_vc_v_ivv_se_e8mf8(<1 x i8> %vd, <1 x i8> %vs2, iXLen %vl) { 1854; CHECK-LABEL: test_sf_vc_v_ivv_se_e8mf8: 1855; CHECK: # %bb.0: # %entry 1856; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma 1857; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 1858; CHECK-NEXT: ret 1859entry: 1860 %0 = tail call <1 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv1i8.iXLen.iXLen.iXLen(iXLen 3, <1 x i8> %vd, <1 x i8> %vs2, iXLen 10, iXLen %vl) 1861 ret <1 x i8> %0 1862} 1863 1864declare <1 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv1i8.iXLen.iXLen.iXLen(iXLen, <1 x i8>, <1 x i8>, iXLen, iXLen) 1865 1866define <2 x i8> @test_sf_vc_v_ivv_se_e8mf4(<2 x i8> %vd, <2 x i8> %vs2, iXLen %vl) { 1867; CHECK-LABEL: test_sf_vc_v_ivv_se_e8mf4: 1868; CHECK: # %bb.0: # %entry 1869; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma 1870; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 1871; CHECK-NEXT: ret 1872entry: 1873 %0 = tail call <2 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv2i8.iXLen.iXLen.iXLen(iXLen 3, <2 x i8> %vd, <2 x i8> %vs2, iXLen 10, iXLen %vl) 1874 ret <2 x i8> %0 1875} 1876 1877declare <2 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv2i8.iXLen.iXLen.iXLen(iXLen, <2 x i8>, <2 x i8>, iXLen, iXLen) 1878 1879define <4 x i8> @test_sf_vc_v_ivv_se_e8mf2(<4 x i8> %vd, <4 x i8> %vs2, iXLen %vl) { 1880; CHECK-LABEL: test_sf_vc_v_ivv_se_e8mf2: 1881; CHECK: # %bb.0: # %entry 1882; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma 1883; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 1884; CHECK-NEXT: ret 1885entry: 1886 %0 = tail call <4 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv4i8.iXLen.iXLen.iXLen(iXLen 3, <4 x i8> %vd, <4 x i8> %vs2, iXLen 10, iXLen %vl) 1887 ret <4 x i8> %0 1888} 1889 1890declare <4 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv4i8.iXLen.iXLen.iXLen(iXLen, <4 x i8>, <4 x i8>, iXLen, iXLen) 1891 1892define <8 x i8> @test_sf_vc_v_ivv_se_e8m1(<8 x i8> %vd, <8 x i8> %vs2, iXLen %vl) { 1893; CHECK-LABEL: test_sf_vc_v_ivv_se_e8m1: 1894; CHECK: # %bb.0: # %entry 1895; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma 1896; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 1897; CHECK-NEXT: ret 1898entry: 1899 %0 = tail call <8 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv8i8.iXLen.iXLen.iXLen(iXLen 3, <8 x i8> %vd, <8 x i8> %vs2, iXLen 10, iXLen %vl) 1900 ret <8 x i8> %0 1901} 1902 1903declare <8 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv8i8.iXLen.iXLen.iXLen(iXLen, <8 x i8>, <8 x i8>, iXLen, iXLen) 1904 1905define <16 x i8> @test_sf_vc_v_ivv_se_e8m2(<16 x i8> %vd, <16 x i8> %vs2, iXLen %vl) { 1906; CHECK-LABEL: test_sf_vc_v_ivv_se_e8m2: 1907; CHECK: # %bb.0: # %entry 1908; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma 1909; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 1910; CHECK-NEXT: ret 1911entry: 1912 %0 = tail call <16 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv16i8.iXLen.iXLen.iXLen(iXLen 3, <16 x i8> %vd, <16 x i8> %vs2, iXLen 10, iXLen %vl) 1913 ret <16 x i8> %0 1914} 1915 1916declare <16 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv16i8.iXLen.iXLen.iXLen(iXLen, <16 x i8>, <16 x i8>, iXLen, iXLen) 1917 1918define <32 x i8> @test_sf_vc_v_ivv_se_e8m4(<32 x i8> %vd, <32 x i8> %vs2, iXLen %vl) { 1919; CHECK-LABEL: test_sf_vc_v_ivv_se_e8m4: 1920; CHECK: # %bb.0: # %entry 1921; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma 1922; CHECK-NEXT: sf.vc.v.ivv 3, v8, v10, 10 1923; CHECK-NEXT: ret 1924entry: 1925 %0 = tail call <32 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv32i8.iXLen.iXLen.iXLen(iXLen 3, <32 x i8> %vd, <32 x i8> %vs2, iXLen 10, iXLen %vl) 1926 ret <32 x i8> %0 1927} 1928 1929declare <32 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv32i8.iXLen.iXLen.iXLen(iXLen, <32 x i8>, <32 x i8>, iXLen, iXLen) 1930 1931define <64 x i8> @test_sf_vc_v_ivv_se_e8m8(<64 x i8> %vd, <64 x i8> %vs2, iXLen %vl) { 1932; CHECK-LABEL: test_sf_vc_v_ivv_se_e8m8: 1933; CHECK: # %bb.0: # %entry 1934; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma 1935; CHECK-NEXT: sf.vc.v.ivv 3, v8, v12, 10 1936; CHECK-NEXT: ret 1937entry: 1938 %0 = tail call <64 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv64i8.iXLen.iXLen.iXLen(iXLen 3, <64 x i8> %vd, <64 x i8> %vs2, iXLen 10, iXLen %vl) 1939 ret <64 x i8> %0 1940} 1941 1942declare <64 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv64i8.iXLen.iXLen.iXLen(iXLen, <64 x i8>, <64 x i8>, iXLen, iXLen) 1943 1944define <1 x i16> @test_sf_vc_v_ivv_se_e16mf4(<1 x i16> %vd, <1 x i16> %vs2, iXLen %vl) { 1945; CHECK-LABEL: test_sf_vc_v_ivv_se_e16mf4: 1946; CHECK: # %bb.0: # %entry 1947; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma 1948; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 1949; CHECK-NEXT: ret 1950entry: 1951 %0 = tail call <1 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv1i16.iXLen.iXLen.iXLen(iXLen 3, <1 x i16> %vd, <1 x i16> %vs2, iXLen 10, iXLen %vl) 1952 ret <1 x i16> %0 1953} 1954 1955declare <1 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv1i16.iXLen.iXLen.iXLen(iXLen, <1 x i16>, <1 x i16>, iXLen, iXLen) 1956 1957define <2 x i16> @test_sf_vc_v_ivv_se_e16mf2(<2 x i16> %vd, <2 x i16> %vs2, iXLen %vl) { 1958; CHECK-LABEL: test_sf_vc_v_ivv_se_e16mf2: 1959; CHECK: # %bb.0: # %entry 1960; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma 1961; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 1962; CHECK-NEXT: ret 1963entry: 1964 %0 = tail call <2 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv2i16.iXLen.iXLen.iXLen(iXLen 3, <2 x i16> %vd, <2 x i16> %vs2, iXLen 10, iXLen %vl) 1965 ret <2 x i16> %0 1966} 1967 1968declare <2 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv2i16.iXLen.iXLen.iXLen(iXLen, <2 x i16>, <2 x i16>, iXLen, iXLen) 1969 1970define <4 x i16> @test_sf_vc_v_ivv_se_e16m1(<4 x i16> %vd, <4 x i16> %vs2, iXLen %vl) { 1971; CHECK-LABEL: test_sf_vc_v_ivv_se_e16m1: 1972; CHECK: # %bb.0: # %entry 1973; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma 1974; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 1975; CHECK-NEXT: ret 1976entry: 1977 %0 = tail call <4 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv4i16.iXLen.iXLen.iXLen(iXLen 3, <4 x i16> %vd, <4 x i16> %vs2, iXLen 10, iXLen %vl) 1978 ret <4 x i16> %0 1979} 1980 1981declare <4 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv4i16.iXLen.iXLen.iXLen(iXLen, <4 x i16>, <4 x i16>, iXLen, iXLen) 1982 1983define <8 x i16> @test_sf_vc_v_ivv_se_e16m2(<8 x i16> %vd, <8 x i16> %vs2, iXLen %vl) { 1984; CHECK-LABEL: test_sf_vc_v_ivv_se_e16m2: 1985; CHECK: # %bb.0: # %entry 1986; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma 1987; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 1988; CHECK-NEXT: ret 1989entry: 1990 %0 = tail call <8 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv8i16.iXLen.iXLen.iXLen(iXLen 3, <8 x i16> %vd, <8 x i16> %vs2, iXLen 10, iXLen %vl) 1991 ret <8 x i16> %0 1992} 1993 1994declare <8 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv8i16.iXLen.iXLen.iXLen(iXLen, <8 x i16>, <8 x i16>, iXLen, iXLen) 1995 1996define <16 x i16> @test_sf_vc_v_ivv_se_e16m4(<16 x i16> %vd, <16 x i16> %vs2, iXLen %vl) { 1997; CHECK-LABEL: test_sf_vc_v_ivv_se_e16m4: 1998; CHECK: # %bb.0: # %entry 1999; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma 2000; CHECK-NEXT: sf.vc.v.ivv 3, v8, v10, 10 2001; CHECK-NEXT: ret 2002entry: 2003 %0 = tail call <16 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv16i16.iXLen.iXLen.iXLen(iXLen 3, <16 x i16> %vd, <16 x i16> %vs2, iXLen 10, iXLen %vl) 2004 ret <16 x i16> %0 2005} 2006 2007declare <16 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv16i16.iXLen.iXLen.iXLen(iXLen, <16 x i16>, <16 x i16>, iXLen, iXLen) 2008 2009define <32 x i16> @test_sf_vc_v_ivv_se_e16m8(<32 x i16> %vd, <32 x i16> %vs2, iXLen %vl) { 2010; CHECK-LABEL: test_sf_vc_v_ivv_se_e16m8: 2011; CHECK: # %bb.0: # %entry 2012; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma 2013; CHECK-NEXT: sf.vc.v.ivv 3, v8, v12, 10 2014; CHECK-NEXT: ret 2015entry: 2016 %0 = tail call <32 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv32i16.iXLen.iXLen.iXLen(iXLen 3, <32 x i16> %vd, <32 x i16> %vs2, iXLen 10, iXLen %vl) 2017 ret <32 x i16> %0 2018} 2019 2020declare <32 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv32i16.iXLen.iXLen.iXLen(iXLen, <32 x i16>, <32 x i16>, iXLen, iXLen) 2021 2022define <1 x i32> @test_sf_vc_v_ivv_se_e32mf2(<1 x i32> %vd, <1 x i32> %vs2, iXLen %vl) { 2023; CHECK-LABEL: test_sf_vc_v_ivv_se_e32mf2: 2024; CHECK: # %bb.0: # %entry 2025; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma 2026; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 2027; CHECK-NEXT: ret 2028entry: 2029 %0 = tail call <1 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv1i32.iXLen.iXLen.iXLen(iXLen 3, <1 x i32> %vd, <1 x i32> %vs2, iXLen 10, iXLen %vl) 2030 ret <1 x i32> %0 2031} 2032 2033declare <1 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv1i32.iXLen.iXLen.iXLen(iXLen, <1 x i32>, <1 x i32>, iXLen, iXLen) 2034 2035define <2 x i32> @test_sf_vc_v_ivv_se_e32m1(<2 x i32> %vd, <2 x i32> %vs2, iXLen %vl) { 2036; CHECK-LABEL: test_sf_vc_v_ivv_se_e32m1: 2037; CHECK: # %bb.0: # %entry 2038; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma 2039; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 2040; CHECK-NEXT: ret 2041entry: 2042 %0 = tail call <2 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv2i32.iXLen.iXLen.iXLen(iXLen 3, <2 x i32> %vd, <2 x i32> %vs2, iXLen 10, iXLen %vl) 2043 ret <2 x i32> %0 2044} 2045 2046declare <2 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv2i32.iXLen.iXLen.iXLen(iXLen, <2 x i32>, <2 x i32>, iXLen, iXLen) 2047 2048define <4 x i32> @test_sf_vc_v_ivv_se_e32m2(<4 x i32> %vd, <4 x i32> %vs2, iXLen %vl) { 2049; CHECK-LABEL: test_sf_vc_v_ivv_se_e32m2: 2050; CHECK: # %bb.0: # %entry 2051; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma 2052; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 2053; CHECK-NEXT: ret 2054entry: 2055 %0 = tail call <4 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv4i32.iXLen.iXLen.iXLen(iXLen 3, <4 x i32> %vd, <4 x i32> %vs2, iXLen 10, iXLen %vl) 2056 ret <4 x i32> %0 2057} 2058 2059declare <4 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv4i32.iXLen.iXLen.iXLen(iXLen, <4 x i32>, <4 x i32>, iXLen, iXLen) 2060 2061define <8 x i32> @test_sf_vc_v_ivv_se_e32m4(<8 x i32> %vd, <8 x i32> %vs2, iXLen %vl) { 2062; CHECK-LABEL: test_sf_vc_v_ivv_se_e32m4: 2063; CHECK: # %bb.0: # %entry 2064; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma 2065; CHECK-NEXT: sf.vc.v.ivv 3, v8, v10, 10 2066; CHECK-NEXT: ret 2067entry: 2068 %0 = tail call <8 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv8i32.iXLen.iXLen.iXLen(iXLen 3, <8 x i32> %vd, <8 x i32> %vs2, iXLen 10, iXLen %vl) 2069 ret <8 x i32> %0 2070} 2071 2072declare <8 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv8i32.iXLen.iXLen.iXLen(iXLen, <8 x i32>, <8 x i32>, iXLen, iXLen) 2073 2074define <16 x i32> @test_sf_vc_v_ivv_se_e32m8(<16 x i32> %vd, <16 x i32> %vs2, iXLen %vl) { 2075; CHECK-LABEL: test_sf_vc_v_ivv_se_e32m8: 2076; CHECK: # %bb.0: # %entry 2077; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma 2078; CHECK-NEXT: sf.vc.v.ivv 3, v8, v12, 10 2079; CHECK-NEXT: ret 2080entry: 2081 %0 = tail call <16 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv16i32.iXLen.iXLen.iXLen(iXLen 3, <16 x i32> %vd, <16 x i32> %vs2, iXLen 10, iXLen %vl) 2082 ret <16 x i32> %0 2083} 2084 2085declare <16 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv16i32.iXLen.iXLen.iXLen(iXLen, <16 x i32>, <16 x i32>, iXLen, iXLen) 2086 2087define <1 x i64> @test_sf_vc_v_ivv_se_e64m1(<1 x i64> %vd, <1 x i64> %vs2, iXLen %vl) { 2088; CHECK-LABEL: test_sf_vc_v_ivv_se_e64m1: 2089; CHECK: # %bb.0: # %entry 2090; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma 2091; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 2092; CHECK-NEXT: ret 2093entry: 2094 %0 = tail call <1 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv1i64.iXLen.iXLen.iXLen(iXLen 3, <1 x i64> %vd, <1 x i64> %vs2, iXLen 10, iXLen %vl) 2095 ret <1 x i64> %0 2096} 2097 2098declare <1 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv1i64.iXLen.iXLen.iXLen(iXLen, <1 x i64>, <1 x i64>, iXLen, iXLen) 2099 2100define <2 x i64> @test_sf_vc_v_ivv_se_e64m2(<2 x i64> %vd, <2 x i64> %vs2, iXLen %vl) { 2101; CHECK-LABEL: test_sf_vc_v_ivv_se_e64m2: 2102; CHECK: # %bb.0: # %entry 2103; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma 2104; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 2105; CHECK-NEXT: ret 2106entry: 2107 %0 = tail call <2 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv2i64.iXLen.iXLen.iXLen(iXLen 3, <2 x i64> %vd, <2 x i64> %vs2, iXLen 10, iXLen %vl) 2108 ret <2 x i64> %0 2109} 2110 2111declare <2 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv2i64.iXLen.iXLen.iXLen(iXLen, <2 x i64>, <2 x i64>, iXLen, iXLen) 2112 2113define <4 x i64> @test_sf_vc_v_ivv_se_e64m4(<4 x i64> %vd, <4 x i64> %vs2, iXLen %vl) { 2114; CHECK-LABEL: test_sf_vc_v_ivv_se_e64m4: 2115; CHECK: # %bb.0: # %entry 2116; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma 2117; CHECK-NEXT: sf.vc.v.ivv 3, v8, v10, 10 2118; CHECK-NEXT: ret 2119entry: 2120 %0 = tail call <4 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv4i64.iXLen.iXLen.iXLen(iXLen 3, <4 x i64> %vd, <4 x i64> %vs2, iXLen 10, iXLen %vl) 2121 ret <4 x i64> %0 2122} 2123 2124declare <4 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv4i64.iXLen.iXLen.iXLen(iXLen, <4 x i64>, <4 x i64>, iXLen, iXLen) 2125 2126define <8 x i64> @test_sf_vc_v_ivv_se_e64m8(<8 x i64> %vd, <8 x i64> %vs2, iXLen %vl) { 2127; CHECK-LABEL: test_sf_vc_v_ivv_se_e64m8: 2128; CHECK: # %bb.0: # %entry 2129; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma 2130; CHECK-NEXT: sf.vc.v.ivv 3, v8, v12, 10 2131; CHECK-NEXT: ret 2132entry: 2133 %0 = tail call <8 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv8i64.iXLen.iXLen.iXLen(iXLen 3, <8 x i64> %vd, <8 x i64> %vs2, iXLen 10, iXLen %vl) 2134 ret <8 x i64> %0 2135} 2136 2137declare <8 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv8i64.iXLen.iXLen.iXLen(iXLen, <8 x i64>, <8 x i64>, iXLen, iXLen) 2138 2139define <1 x i8> @test_sf_vc_v_ivv_e8mf8(<1 x i8> %vd, <1 x i8> %vs2, iXLen %vl) { 2140; CHECK-LABEL: test_sf_vc_v_ivv_e8mf8: 2141; CHECK: # %bb.0: # %entry 2142; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma 2143; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 2144; CHECK-NEXT: ret 2145entry: 2146 %0 = tail call <1 x i8> @llvm.riscv.sf.vc.v.ivv.nxv1i8.iXLen.iXLen.iXLen(iXLen 3, <1 x i8> %vd, <1 x i8> %vs2, iXLen 10, iXLen %vl) 2147 ret <1 x i8> %0 2148} 2149 2150declare <1 x i8> @llvm.riscv.sf.vc.v.ivv.nxv1i8.iXLen.iXLen.iXLen(iXLen, <1 x i8>, <1 x i8>, iXLen, iXLen) 2151 2152define <2 x i8> @test_sf_vc_v_ivv_e8mf4(<2 x i8> %vd, <2 x i8> %vs2, iXLen %vl) { 2153; CHECK-LABEL: test_sf_vc_v_ivv_e8mf4: 2154; CHECK: # %bb.0: # %entry 2155; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma 2156; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 2157; CHECK-NEXT: ret 2158entry: 2159 %0 = tail call <2 x i8> @llvm.riscv.sf.vc.v.ivv.nxv2i8.iXLen.iXLen.iXLen(iXLen 3, <2 x i8> %vd, <2 x i8> %vs2, iXLen 10, iXLen %vl) 2160 ret <2 x i8> %0 2161} 2162 2163declare <2 x i8> @llvm.riscv.sf.vc.v.ivv.nxv2i8.iXLen.iXLen.iXLen(iXLen, <2 x i8>, <2 x i8>, iXLen, iXLen) 2164 2165define <4 x i8> @test_sf_vc_v_ivv_e8mf2(<4 x i8> %vd, <4 x i8> %vs2, iXLen %vl) { 2166; CHECK-LABEL: test_sf_vc_v_ivv_e8mf2: 2167; CHECK: # %bb.0: # %entry 2168; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma 2169; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 2170; CHECK-NEXT: ret 2171entry: 2172 %0 = tail call <4 x i8> @llvm.riscv.sf.vc.v.ivv.nxv4i8.iXLen.iXLen.iXLen(iXLen 3, <4 x i8> %vd, <4 x i8> %vs2, iXLen 10, iXLen %vl) 2173 ret <4 x i8> %0 2174} 2175 2176declare <4 x i8> @llvm.riscv.sf.vc.v.ivv.nxv4i8.iXLen.iXLen.iXLen(iXLen, <4 x i8>, <4 x i8>, iXLen, iXLen) 2177 2178define <8 x i8> @test_sf_vc_v_ivv_e8m1(<8 x i8> %vd, <8 x i8> %vs2, iXLen %vl) { 2179; CHECK-LABEL: test_sf_vc_v_ivv_e8m1: 2180; CHECK: # %bb.0: # %entry 2181; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma 2182; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 2183; CHECK-NEXT: ret 2184entry: 2185 %0 = tail call <8 x i8> @llvm.riscv.sf.vc.v.ivv.nxv8i8.iXLen.iXLen.iXLen(iXLen 3, <8 x i8> %vd, <8 x i8> %vs2, iXLen 10, iXLen %vl) 2186 ret <8 x i8> %0 2187} 2188 2189declare <8 x i8> @llvm.riscv.sf.vc.v.ivv.nxv8i8.iXLen.iXLen.iXLen(iXLen, <8 x i8>, <8 x i8>, iXLen, iXLen) 2190 2191define <16 x i8> @test_sf_vc_v_ivv_e8m2(<16 x i8> %vd, <16 x i8> %vs2, iXLen %vl) { 2192; CHECK-LABEL: test_sf_vc_v_ivv_e8m2: 2193; CHECK: # %bb.0: # %entry 2194; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma 2195; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 2196; CHECK-NEXT: ret 2197entry: 2198 %0 = tail call <16 x i8> @llvm.riscv.sf.vc.v.ivv.nxv16i8.iXLen.iXLen.iXLen(iXLen 3, <16 x i8> %vd, <16 x i8> %vs2, iXLen 10, iXLen %vl) 2199 ret <16 x i8> %0 2200} 2201 2202declare <16 x i8> @llvm.riscv.sf.vc.v.ivv.nxv16i8.iXLen.iXLen.iXLen(iXLen, <16 x i8>, <16 x i8>, iXLen, iXLen) 2203 2204define <32 x i8> @test_sf_vc_v_ivv_e8m4(<32 x i8> %vd, <32 x i8> %vs2, iXLen %vl) { 2205; CHECK-LABEL: test_sf_vc_v_ivv_e8m4: 2206; CHECK: # %bb.0: # %entry 2207; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma 2208; CHECK-NEXT: sf.vc.v.ivv 3, v8, v10, 10 2209; CHECK-NEXT: ret 2210entry: 2211 %0 = tail call <32 x i8> @llvm.riscv.sf.vc.v.ivv.nxv32i8.iXLen.iXLen.iXLen(iXLen 3, <32 x i8> %vd, <32 x i8> %vs2, iXLen 10, iXLen %vl) 2212 ret <32 x i8> %0 2213} 2214 2215declare <32 x i8> @llvm.riscv.sf.vc.v.ivv.nxv32i8.iXLen.iXLen.iXLen(iXLen, <32 x i8>, <32 x i8>, iXLen, iXLen) 2216 2217define <64 x i8> @test_sf_vc_v_ivv_e8m8(<64 x i8> %vd, <64 x i8> %vs2, iXLen %vl) { 2218; CHECK-LABEL: test_sf_vc_v_ivv_e8m8: 2219; CHECK: # %bb.0: # %entry 2220; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma 2221; CHECK-NEXT: sf.vc.v.ivv 3, v8, v12, 10 2222; CHECK-NEXT: ret 2223entry: 2224 %0 = tail call <64 x i8> @llvm.riscv.sf.vc.v.ivv.nxv64i8.iXLen.iXLen.iXLen(iXLen 3, <64 x i8> %vd, <64 x i8> %vs2, iXLen 10, iXLen %vl) 2225 ret <64 x i8> %0 2226} 2227 2228declare <64 x i8> @llvm.riscv.sf.vc.v.ivv.nxv64i8.iXLen.iXLen.iXLen(iXLen, <64 x i8>, <64 x i8>, iXLen, iXLen) 2229 2230define <1 x i16> @test_sf_vc_v_ivv_e16mf4(<1 x i16> %vd, <1 x i16> %vs2, iXLen %vl) { 2231; CHECK-LABEL: test_sf_vc_v_ivv_e16mf4: 2232; CHECK: # %bb.0: # %entry 2233; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma 2234; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 2235; CHECK-NEXT: ret 2236entry: 2237 %0 = tail call <1 x i16> @llvm.riscv.sf.vc.v.ivv.nxv1i16.iXLen.iXLen.iXLen(iXLen 3, <1 x i16> %vd, <1 x i16> %vs2, iXLen 10, iXLen %vl) 2238 ret <1 x i16> %0 2239} 2240 2241declare <1 x i16> @llvm.riscv.sf.vc.v.ivv.nxv1i16.iXLen.iXLen.iXLen(iXLen, <1 x i16>, <1 x i16>, iXLen, iXLen) 2242 2243define <2 x i16> @test_sf_vc_v_ivv_e16mf2(<2 x i16> %vd, <2 x i16> %vs2, iXLen %vl) { 2244; CHECK-LABEL: test_sf_vc_v_ivv_e16mf2: 2245; CHECK: # %bb.0: # %entry 2246; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma 2247; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 2248; CHECK-NEXT: ret 2249entry: 2250 %0 = tail call <2 x i16> @llvm.riscv.sf.vc.v.ivv.nxv2i16.iXLen.iXLen.iXLen(iXLen 3, <2 x i16> %vd, <2 x i16> %vs2, iXLen 10, iXLen %vl) 2251 ret <2 x i16> %0 2252} 2253 2254declare <2 x i16> @llvm.riscv.sf.vc.v.ivv.nxv2i16.iXLen.iXLen.iXLen(iXLen, <2 x i16>, <2 x i16>, iXLen, iXLen) 2255 2256define <4 x i16> @test_sf_vc_v_ivv_e16m1(<4 x i16> %vd, <4 x i16> %vs2, iXLen %vl) { 2257; CHECK-LABEL: test_sf_vc_v_ivv_e16m1: 2258; CHECK: # %bb.0: # %entry 2259; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma 2260; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 2261; CHECK-NEXT: ret 2262entry: 2263 %0 = tail call <4 x i16> @llvm.riscv.sf.vc.v.ivv.nxv4i16.iXLen.iXLen.iXLen(iXLen 3, <4 x i16> %vd, <4 x i16> %vs2, iXLen 10, iXLen %vl) 2264 ret <4 x i16> %0 2265} 2266 2267declare <4 x i16> @llvm.riscv.sf.vc.v.ivv.nxv4i16.iXLen.iXLen.iXLen(iXLen, <4 x i16>, <4 x i16>, iXLen, iXLen) 2268 2269define <8 x i16> @test_sf_vc_v_ivv_e16m2(<8 x i16> %vd, <8 x i16> %vs2, iXLen %vl) { 2270; CHECK-LABEL: test_sf_vc_v_ivv_e16m2: 2271; CHECK: # %bb.0: # %entry 2272; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma 2273; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 2274; CHECK-NEXT: ret 2275entry: 2276 %0 = tail call <8 x i16> @llvm.riscv.sf.vc.v.ivv.nxv8i16.iXLen.iXLen.iXLen(iXLen 3, <8 x i16> %vd, <8 x i16> %vs2, iXLen 10, iXLen %vl) 2277 ret <8 x i16> %0 2278} 2279 2280declare <8 x i16> @llvm.riscv.sf.vc.v.ivv.nxv8i16.iXLen.iXLen.iXLen(iXLen, <8 x i16>, <8 x i16>, iXLen, iXLen) 2281 2282define <16 x i16> @test_sf_vc_v_ivv_e16m4(<16 x i16> %vd, <16 x i16> %vs2, iXLen %vl) { 2283; CHECK-LABEL: test_sf_vc_v_ivv_e16m4: 2284; CHECK: # %bb.0: # %entry 2285; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma 2286; CHECK-NEXT: sf.vc.v.ivv 3, v8, v10, 10 2287; CHECK-NEXT: ret 2288entry: 2289 %0 = tail call <16 x i16> @llvm.riscv.sf.vc.v.ivv.nxv16i16.iXLen.iXLen.iXLen(iXLen 3, <16 x i16> %vd, <16 x i16> %vs2, iXLen 10, iXLen %vl) 2290 ret <16 x i16> %0 2291} 2292 2293declare <16 x i16> @llvm.riscv.sf.vc.v.ivv.nxv16i16.iXLen.iXLen.iXLen(iXLen, <16 x i16>, <16 x i16>, iXLen, iXLen) 2294 2295define <32 x i16> @test_sf_vc_v_ivv_e16m8(<32 x i16> %vd, <32 x i16> %vs2, iXLen %vl) { 2296; CHECK-LABEL: test_sf_vc_v_ivv_e16m8: 2297; CHECK: # %bb.0: # %entry 2298; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma 2299; CHECK-NEXT: sf.vc.v.ivv 3, v8, v12, 10 2300; CHECK-NEXT: ret 2301entry: 2302 %0 = tail call <32 x i16> @llvm.riscv.sf.vc.v.ivv.nxv32i16.iXLen.iXLen.iXLen(iXLen 3, <32 x i16> %vd, <32 x i16> %vs2, iXLen 10, iXLen %vl) 2303 ret <32 x i16> %0 2304} 2305 2306declare <32 x i16> @llvm.riscv.sf.vc.v.ivv.nxv32i16.iXLen.iXLen.iXLen(iXLen, <32 x i16>, <32 x i16>, iXLen, iXLen) 2307 2308define <1 x i32> @test_sf_vc_v_ivv_e32mf2(<1 x i32> %vd, <1 x i32> %vs2, iXLen %vl) { 2309; CHECK-LABEL: test_sf_vc_v_ivv_e32mf2: 2310; CHECK: # %bb.0: # %entry 2311; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma 2312; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 2313; CHECK-NEXT: ret 2314entry: 2315 %0 = tail call <1 x i32> @llvm.riscv.sf.vc.v.ivv.nxv1i32.iXLen.iXLen.iXLen(iXLen 3, <1 x i32> %vd, <1 x i32> %vs2, iXLen 10, iXLen %vl) 2316 ret <1 x i32> %0 2317} 2318 2319declare <1 x i32> @llvm.riscv.sf.vc.v.ivv.nxv1i32.iXLen.iXLen.iXLen(iXLen, <1 x i32>, <1 x i32>, iXLen, iXLen) 2320 2321define <2 x i32> @test_sf_vc_v_ivv_e32m1(<2 x i32> %vd, <2 x i32> %vs2, iXLen %vl) { 2322; CHECK-LABEL: test_sf_vc_v_ivv_e32m1: 2323; CHECK: # %bb.0: # %entry 2324; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma 2325; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 2326; CHECK-NEXT: ret 2327entry: 2328 %0 = tail call <2 x i32> @llvm.riscv.sf.vc.v.ivv.nxv2i32.iXLen.iXLen.iXLen(iXLen 3, <2 x i32> %vd, <2 x i32> %vs2, iXLen 10, iXLen %vl) 2329 ret <2 x i32> %0 2330} 2331 2332declare <2 x i32> @llvm.riscv.sf.vc.v.ivv.nxv2i32.iXLen.iXLen.iXLen(iXLen, <2 x i32>, <2 x i32>, iXLen, iXLen) 2333 2334define <4 x i32> @test_sf_vc_v_ivv_e32m2(<4 x i32> %vd, <4 x i32> %vs2, iXLen %vl) { 2335; CHECK-LABEL: test_sf_vc_v_ivv_e32m2: 2336; CHECK: # %bb.0: # %entry 2337; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma 2338; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 2339; CHECK-NEXT: ret 2340entry: 2341 %0 = tail call <4 x i32> @llvm.riscv.sf.vc.v.ivv.nxv4i32.iXLen.iXLen.iXLen(iXLen 3, <4 x i32> %vd, <4 x i32> %vs2, iXLen 10, iXLen %vl) 2342 ret <4 x i32> %0 2343} 2344 2345declare <4 x i32> @llvm.riscv.sf.vc.v.ivv.nxv4i32.iXLen.iXLen.iXLen(iXLen, <4 x i32>, <4 x i32>, iXLen, iXLen) 2346 2347define <8 x i32> @test_sf_vc_v_ivv_e32m4(<8 x i32> %vd, <8 x i32> %vs2, iXLen %vl) { 2348; CHECK-LABEL: test_sf_vc_v_ivv_e32m4: 2349; CHECK: # %bb.0: # %entry 2350; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma 2351; CHECK-NEXT: sf.vc.v.ivv 3, v8, v10, 10 2352; CHECK-NEXT: ret 2353entry: 2354 %0 = tail call <8 x i32> @llvm.riscv.sf.vc.v.ivv.nxv8i32.iXLen.iXLen.iXLen(iXLen 3, <8 x i32> %vd, <8 x i32> %vs2, iXLen 10, iXLen %vl) 2355 ret <8 x i32> %0 2356} 2357 2358declare <8 x i32> @llvm.riscv.sf.vc.v.ivv.nxv8i32.iXLen.iXLen.iXLen(iXLen, <8 x i32>, <8 x i32>, iXLen, iXLen) 2359 2360define <16 x i32> @test_sf_vc_v_ivv_e32m8(<16 x i32> %vd, <16 x i32> %vs2, iXLen %vl) { 2361; CHECK-LABEL: test_sf_vc_v_ivv_e32m8: 2362; CHECK: # %bb.0: # %entry 2363; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma 2364; CHECK-NEXT: sf.vc.v.ivv 3, v8, v12, 10 2365; CHECK-NEXT: ret 2366entry: 2367 %0 = tail call <16 x i32> @llvm.riscv.sf.vc.v.ivv.nxv16i32.iXLen.iXLen.iXLen(iXLen 3, <16 x i32> %vd, <16 x i32> %vs2, iXLen 10, iXLen %vl) 2368 ret <16 x i32> %0 2369} 2370 2371declare <16 x i32> @llvm.riscv.sf.vc.v.ivv.nxv16i32.iXLen.iXLen.iXLen(iXLen, <16 x i32>, <16 x i32>, iXLen, iXLen) 2372 2373define <1 x i64> @test_sf_vc_v_ivv_e64m1(<1 x i64> %vd, <1 x i64> %vs2, iXLen %vl) { 2374; CHECK-LABEL: test_sf_vc_v_ivv_e64m1: 2375; CHECK: # %bb.0: # %entry 2376; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma 2377; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 2378; CHECK-NEXT: ret 2379entry: 2380 %0 = tail call <1 x i64> @llvm.riscv.sf.vc.v.ivv.nxv1i64.iXLen.iXLen.iXLen(iXLen 3, <1 x i64> %vd, <1 x i64> %vs2, iXLen 10, iXLen %vl) 2381 ret <1 x i64> %0 2382} 2383 2384declare <1 x i64> @llvm.riscv.sf.vc.v.ivv.nxv1i64.iXLen.iXLen.iXLen(iXLen, <1 x i64>, <1 x i64>, iXLen, iXLen) 2385 2386define <2 x i64> @test_sf_vc_v_ivv_e64m2(<2 x i64> %vd, <2 x i64> %vs2, iXLen %vl) { 2387; CHECK-LABEL: test_sf_vc_v_ivv_e64m2: 2388; CHECK: # %bb.0: # %entry 2389; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma 2390; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 10 2391; CHECK-NEXT: ret 2392entry: 2393 %0 = tail call <2 x i64> @llvm.riscv.sf.vc.v.ivv.nxv2i64.iXLen.iXLen.iXLen(iXLen 3, <2 x i64> %vd, <2 x i64> %vs2, iXLen 10, iXLen %vl) 2394 ret <2 x i64> %0 2395} 2396 2397declare <2 x i64> @llvm.riscv.sf.vc.v.ivv.nxv2i64.iXLen.iXLen.iXLen(iXLen, <2 x i64>, <2 x i64>, iXLen, iXLen) 2398 2399define <4 x i64> @test_sf_vc_v_ivv_e64m4(<4 x i64> %vd, <4 x i64> %vs2, iXLen %vl) { 2400; CHECK-LABEL: test_sf_vc_v_ivv_e64m4: 2401; CHECK: # %bb.0: # %entry 2402; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma 2403; CHECK-NEXT: sf.vc.v.ivv 3, v8, v10, 10 2404; CHECK-NEXT: ret 2405entry: 2406 %0 = tail call <4 x i64> @llvm.riscv.sf.vc.v.ivv.nxv4i64.iXLen.iXLen.iXLen(iXLen 3, <4 x i64> %vd, <4 x i64> %vs2, iXLen 10, iXLen %vl) 2407 ret <4 x i64> %0 2408} 2409 2410declare <4 x i64> @llvm.riscv.sf.vc.v.ivv.nxv4i64.iXLen.iXLen.iXLen(iXLen, <4 x i64>, <4 x i64>, iXLen, iXLen) 2411 2412define <8 x i64> @test_sf_vc_v_ivv_e64m8(<8 x i64> %vd, <8 x i64> %vs2, iXLen %vl) { 2413; CHECK-LABEL: test_sf_vc_v_ivv_e64m8: 2414; CHECK: # %bb.0: # %entry 2415; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma 2416; CHECK-NEXT: sf.vc.v.ivv 3, v8, v12, 10 2417; CHECK-NEXT: ret 2418entry: 2419 %0 = tail call <8 x i64> @llvm.riscv.sf.vc.v.ivv.nxv8i64.iXLen.iXLen.iXLen(iXLen 3, <8 x i64> %vd, <8 x i64> %vs2, iXLen 10, iXLen %vl) 2420 ret <8 x i64> %0 2421} 2422 2423declare <8 x i64> @llvm.riscv.sf.vc.v.ivv.nxv8i64.iXLen.iXLen.iXLen(iXLen, <8 x i64>, <8 x i64>, iXLen, iXLen) 2424 2425define void @test_sf_vc_fvvv_se_e16mf4(<1 x half> %vd, <1 x i16> %vs2, <1 x i16> %vs1, iXLen %vl) { 2426; CHECK-LABEL: test_sf_vc_fvvv_se_e16mf4: 2427; CHECK: # %bb.0: # %entry 2428; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma 2429; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 2430; CHECK-NEXT: ret 2431entry: 2432 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1f16.nxv1i16.nxv1i16.iXLen(iXLen 3, <1 x half> %vd, <1 x i16> %vs2, <1 x i16> %vs1, iXLen %vl) 2433 ret void 2434} 2435 2436declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1f16.nxv1i16.nxv1i16.iXLen(iXLen, <1 x half>, <1 x i16>, <1 x i16>, iXLen) 2437 2438define <1 x half> @test_sf_vc_fv_fvv_se_e16mf4(<1 x half> %vd, <1 x i16> %vs2, <1 x i16> %vs1, iXLen %vl) { 2439; CHECK-LABEL: test_sf_vc_fv_fvv_se_e16mf4: 2440; CHECK: # %bb.0: # %entry 2441; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma 2442; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 2443; CHECK-NEXT: ret 2444entry: 2445 %0 = tail call <1 x half> @llvm.riscv.sf.vc.v.vvv.se.nxv1f16.nxv1i16.nxv1i16.iXLen(iXLen 3, <1 x half> %vd, <1 x i16> %vs2, <1 x i16> %vs1, iXLen %vl) 2446 ret <1 x half> %0 2447} 2448 2449declare <1 x half> @llvm.riscv.sf.vc.v.vvv.se.nxv1f16.nxv1i16.nxv1i16.iXLen(iXLen, <1 x half>, <1 x i16>, <1 x i16>, iXLen) 2450 2451define void @test_sf_vc_fvvv_se_e16mf2(<2 x half> %vd, <2 x i16> %vs2, <2 x i16> %vs1, iXLen %vl) { 2452; CHECK-LABEL: test_sf_vc_fvvv_se_e16mf2: 2453; CHECK: # %bb.0: # %entry 2454; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma 2455; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 2456; CHECK-NEXT: ret 2457entry: 2458 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2f16.nxv2i16.nxv2i16.iXLen(iXLen 3, <2 x half> %vd, <2 x i16> %vs2, <2 x i16> %vs1, iXLen %vl) 2459 ret void 2460} 2461 2462declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2f16.nxv2i16.nxv2i16.iXLen(iXLen, <2 x half>, <2 x i16>, <2 x i16>, iXLen) 2463 2464define <2 x half> @test_sf_vc_fv_fvv_se_e16mf2(<2 x half> %vd, <2 x i16> %vs2, <2 x i16> %vs1, iXLen %vl) { 2465; CHECK-LABEL: test_sf_vc_fv_fvv_se_e16mf2: 2466; CHECK: # %bb.0: # %entry 2467; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma 2468; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 2469; CHECK-NEXT: ret 2470entry: 2471 %0 = tail call <2 x half> @llvm.riscv.sf.vc.v.vvv.se.nxv2f16.nxv2i16.nxv2i16.iXLen(iXLen 3, <2 x half> %vd, <2 x i16> %vs2, <2 x i16> %vs1, iXLen %vl) 2472 ret <2 x half> %0 2473} 2474 2475declare <2 x half> @llvm.riscv.sf.vc.v.vvv.se.nxv2f16.nxv2i16.nxv2i16.iXLen(iXLen, <2 x half>, <2 x i16>, <2 x i16>, iXLen) 2476 2477define void @test_sf_vc_fvvv_se_e16m1(<4 x half> %vd, <4 x i16> %vs2, <4 x i16> %vs1, iXLen %vl) { 2478; CHECK-LABEL: test_sf_vc_fvvv_se_e16m1: 2479; CHECK: # %bb.0: # %entry 2480; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 2481; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 2482; CHECK-NEXT: ret 2483entry: 2484 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4f16.nxv4i16.nxv4i16.iXLen(iXLen 3, <4 x half> %vd, <4 x i16> %vs2, <4 x i16> %vs1, iXLen %vl) 2485 ret void 2486} 2487 2488declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4f16.nxv4i16.nxv4i16.iXLen(iXLen, <4 x half>, <4 x i16>, <4 x i16>, iXLen) 2489 2490define <4 x half> @test_sf_vc_fv_fvv_se_e16m1(<4 x half> %vd, <4 x i16> %vs2, <4 x i16> %vs1, iXLen %vl) { 2491; CHECK-LABEL: test_sf_vc_fv_fvv_se_e16m1: 2492; CHECK: # %bb.0: # %entry 2493; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma 2494; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 2495; CHECK-NEXT: ret 2496entry: 2497 %0 = tail call <4 x half> @llvm.riscv.sf.vc.v.vvv.se.nxv4f16.nxv4i16.nxv4i16.iXLen(iXLen 3, <4 x half> %vd, <4 x i16> %vs2, <4 x i16> %vs1, iXLen %vl) 2498 ret <4 x half> %0 2499} 2500 2501declare <4 x half> @llvm.riscv.sf.vc.v.vvv.se.nxv4f16.nxv4i16.nxv4i16.iXLen(iXLen, <4 x half>, <4 x i16>, <4 x i16>, iXLen) 2502 2503define void @test_sf_vc_fvvv_se_e16m2(<8 x half> %vd, <8 x i16> %vs2, <8 x i16> %vs1, iXLen %vl) { 2504; CHECK-LABEL: test_sf_vc_fvvv_se_e16m2: 2505; CHECK: # %bb.0: # %entry 2506; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma 2507; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 2508; CHECK-NEXT: ret 2509entry: 2510 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8f16.nxv8i16.nxv8i16.iXLen(iXLen 3, <8 x half> %vd, <8 x i16> %vs2, <8 x i16> %vs1, iXLen %vl) 2511 ret void 2512} 2513 2514declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8f16.nxv8i16.nxv8i16.iXLen(iXLen, <8 x half>, <8 x i16>, <8 x i16>, iXLen) 2515 2516define <8 x half> @test_sf_vc_fv_fvv_se_e16m2(<8 x half> %vd, <8 x i16> %vs2, <8 x i16> %vs1, iXLen %vl) { 2517; CHECK-LABEL: test_sf_vc_fv_fvv_se_e16m2: 2518; CHECK: # %bb.0: # %entry 2519; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma 2520; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 2521; CHECK-NEXT: ret 2522entry: 2523 %0 = tail call <8 x half> @llvm.riscv.sf.vc.v.vvv.se.nxv8f16.nxv8i16.nxv8i16.iXLen(iXLen 3, <8 x half> %vd, <8 x i16> %vs2, <8 x i16> %vs1, iXLen %vl) 2524 ret <8 x half> %0 2525} 2526 2527declare <8 x half> @llvm.riscv.sf.vc.v.vvv.se.nxv8f16.nxv8i16.nxv8i16.iXLen(iXLen, <8 x half>, <8 x i16>, <8 x i16>, iXLen) 2528 2529define void @test_sf_vc_fvvv_se_e16m4(<16 x half> %vd, <16 x i16> %vs2, <16 x i16> %vs1, iXLen %vl) { 2530; CHECK-LABEL: test_sf_vc_fvvv_se_e16m4: 2531; CHECK: # %bb.0: # %entry 2532; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma 2533; CHECK-NEXT: sf.vc.vvv 3, v8, v10, v12 2534; CHECK-NEXT: ret 2535entry: 2536 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv16f16.nxv16i16.nxv16i16.iXLen(iXLen 3, <16 x half> %vd, <16 x i16> %vs2, <16 x i16> %vs1, iXLen %vl) 2537 ret void 2538} 2539 2540declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv16f16.nxv16i16.nxv16i16.iXLen(iXLen, <16 x half>, <16 x i16>, <16 x i16>, iXLen) 2541 2542define <16 x half> @test_sf_vc_fv_fvv_se_e16m4(<16 x half> %vd, <16 x i16> %vs2, <16 x i16> %vs1, iXLen %vl) { 2543; CHECK-LABEL: test_sf_vc_fv_fvv_se_e16m4: 2544; CHECK: # %bb.0: # %entry 2545; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma 2546; CHECK-NEXT: sf.vc.v.vvv 3, v8, v10, v12 2547; CHECK-NEXT: ret 2548entry: 2549 %0 = tail call <16 x half> @llvm.riscv.sf.vc.v.vvv.se.nxv16f16.nxv16i16.nxv16i16.iXLen(iXLen 3, <16 x half> %vd, <16 x i16> %vs2, <16 x i16> %vs1, iXLen %vl) 2550 ret <16 x half> %0 2551} 2552 2553declare <16 x half> @llvm.riscv.sf.vc.v.vvv.se.nxv16f16.nxv16i16.nxv16i16.iXLen(iXLen, <16 x half>, <16 x i16>, <16 x i16>, iXLen) 2554 2555define void @test_sf_vc_fvvv_se_e16m8(<32 x half> %vd, <32 x i16> %vs2, <32 x i16> %vs1, iXLen %vl) { 2556; CHECK-LABEL: test_sf_vc_fvvv_se_e16m8: 2557; CHECK: # %bb.0: # %entry 2558; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma 2559; CHECK-NEXT: sf.vc.vvv 3, v8, v12, v16 2560; CHECK-NEXT: ret 2561entry: 2562 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv32f16.nxv32i16.nxv32i16.iXLen(iXLen 3, <32 x half> %vd, <32 x i16> %vs2, <32 x i16> %vs1, iXLen %vl) 2563 ret void 2564} 2565 2566declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv32f16.nxv32i16.nxv32i16.iXLen(iXLen, <32 x half>, <32 x i16>, <32 x i16>, iXLen) 2567 2568define <32 x half> @test_sf_vc_fv_fvv_se_e16m8(<32 x half> %vd, <32 x i16> %vs2, <32 x i16> %vs1, iXLen %vl) { 2569; CHECK-LABEL: test_sf_vc_fv_fvv_se_e16m8: 2570; CHECK: # %bb.0: # %entry 2571; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma 2572; CHECK-NEXT: sf.vc.v.vvv 3, v8, v12, v16 2573; CHECK-NEXT: ret 2574entry: 2575 %0 = tail call <32 x half> @llvm.riscv.sf.vc.v.vvv.se.nxv32f16.nxv32i16.nxv32i16.iXLen(iXLen 3, <32 x half> %vd, <32 x i16> %vs2, <32 x i16> %vs1, iXLen %vl) 2576 ret <32 x half> %0 2577} 2578 2579declare <32 x half> @llvm.riscv.sf.vc.v.vvv.se.nxv32f16.nxv32i16.nxv32i16.iXLen(iXLen, <32 x half>, <32 x i16>, <32 x i16>, iXLen) 2580 2581define void @test_sf_vc_fvvv_se_e32mf2(<1 x float> %vd, <1 x i32> %vs2, <1 x i32> %vs1, iXLen %vl) { 2582; CHECK-LABEL: test_sf_vc_fvvv_se_e32mf2: 2583; CHECK: # %bb.0: # %entry 2584; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma 2585; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 2586; CHECK-NEXT: ret 2587entry: 2588 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1f32.nxv1i32.nxv1i32.iXLen(iXLen 3, <1 x float> %vd, <1 x i32> %vs2, <1 x i32> %vs1, iXLen %vl) 2589 ret void 2590} 2591 2592declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1f32.nxv1i32.nxv1i32.iXLen(iXLen, <1 x float>, <1 x i32>, <1 x i32>, iXLen) 2593 2594define <1 x float> @test_sf_vc_fv_fvv_se_e32mf2(<1 x float> %vd, <1 x i32> %vs2, <1 x i32> %vs1, iXLen %vl) { 2595; CHECK-LABEL: test_sf_vc_fv_fvv_se_e32mf2: 2596; CHECK: # %bb.0: # %entry 2597; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma 2598; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 2599; CHECK-NEXT: ret 2600entry: 2601 %0 = tail call <1 x float> @llvm.riscv.sf.vc.v.vvv.se.nxv1f32.nxv1i32.nxv1i32.iXLen(iXLen 3, <1 x float> %vd, <1 x i32> %vs2, <1 x i32> %vs1, iXLen %vl) 2602 ret <1 x float> %0 2603} 2604 2605declare <1 x float> @llvm.riscv.sf.vc.v.vvv.se.nxv1f32.nxv1i32.nxv1i32.iXLen(iXLen, <1 x float>, <1 x i32>, <1 x i32>, iXLen) 2606 2607define void @test_sf_vc_fvvv_se_e32m1(<2 x float> %vd, <2 x i32> %vs2, <2 x i32> %vs1, iXLen %vl) { 2608; CHECK-LABEL: test_sf_vc_fvvv_se_e32m1: 2609; CHECK: # %bb.0: # %entry 2610; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma 2611; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 2612; CHECK-NEXT: ret 2613entry: 2614 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2f32.nxv2i32.nxv2i32.iXLen(iXLen 3, <2 x float> %vd, <2 x i32> %vs2, <2 x i32> %vs1, iXLen %vl) 2615 ret void 2616} 2617 2618declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2f32.nxv2i32.nxv2i32.iXLen(iXLen, <2 x float>, <2 x i32>, <2 x i32>, iXLen) 2619 2620define <2 x float> @test_sf_vc_fv_fvv_se_e32m1(<2 x float> %vd, <2 x i32> %vs2, <2 x i32> %vs1, iXLen %vl) { 2621; CHECK-LABEL: test_sf_vc_fv_fvv_se_e32m1: 2622; CHECK: # %bb.0: # %entry 2623; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma 2624; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 2625; CHECK-NEXT: ret 2626entry: 2627 %0 = tail call <2 x float> @llvm.riscv.sf.vc.v.vvv.se.nxv2f32.nxv2i32.nxv2i32.iXLen(iXLen 3, <2 x float> %vd, <2 x i32> %vs2, <2 x i32> %vs1, iXLen %vl) 2628 ret <2 x float> %0 2629} 2630 2631declare <2 x float> @llvm.riscv.sf.vc.v.vvv.se.nxv2f32.nxv2i32.nxv2i32.iXLen(iXLen, <2 x float>, <2 x i32>, <2 x i32>, iXLen) 2632 2633define void @test_sf_vc_fvvv_se_e32m2(<4 x float> %vd, <4 x i32> %vs2, <4 x i32> %vs1, iXLen %vl) { 2634; CHECK-LABEL: test_sf_vc_fvvv_se_e32m2: 2635; CHECK: # %bb.0: # %entry 2636; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 2637; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 2638; CHECK-NEXT: ret 2639entry: 2640 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4f32.nxv4i32.nxv4i32.iXLen(iXLen 3, <4 x float> %vd, <4 x i32> %vs2, <4 x i32> %vs1, iXLen %vl) 2641 ret void 2642} 2643 2644declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4f32.nxv4i32.nxv4i32.iXLen(iXLen, <4 x float>, <4 x i32>, <4 x i32>, iXLen) 2645 2646define <4 x float> @test_sf_vc_fv_fvv_se_e32m2(<4 x float> %vd, <4 x i32> %vs2, <4 x i32> %vs1, iXLen %vl) { 2647; CHECK-LABEL: test_sf_vc_fv_fvv_se_e32m2: 2648; CHECK: # %bb.0: # %entry 2649; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma 2650; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 2651; CHECK-NEXT: ret 2652entry: 2653 %0 = tail call <4 x float> @llvm.riscv.sf.vc.v.vvv.se.nxv4f32.nxv4i32.nxv4i32.iXLen(iXLen 3, <4 x float> %vd, <4 x i32> %vs2, <4 x i32> %vs1, iXLen %vl) 2654 ret <4 x float> %0 2655} 2656 2657declare <4 x float> @llvm.riscv.sf.vc.v.vvv.se.nxv4f32.nxv4i32.nxv4i32.iXLen(iXLen, <4 x float>, <4 x i32>, <4 x i32>, iXLen) 2658 2659define void @test_sf_vc_fvvv_se_e32m4(<8 x float> %vd, <8 x i32> %vs2, <8 x i32> %vs1, iXLen %vl) { 2660; CHECK-LABEL: test_sf_vc_fvvv_se_e32m4: 2661; CHECK: # %bb.0: # %entry 2662; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma 2663; CHECK-NEXT: sf.vc.vvv 3, v8, v10, v12 2664; CHECK-NEXT: ret 2665entry: 2666 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8f32.nxv8i32.nxv8i32.iXLen(iXLen 3, <8 x float> %vd, <8 x i32> %vs2, <8 x i32> %vs1, iXLen %vl) 2667 ret void 2668} 2669 2670declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8f32.nxv8i32.nxv8i32.iXLen(iXLen, <8 x float>, <8 x i32>, <8 x i32>, iXLen) 2671 2672define <8 x float> @test_sf_vc_fv_fvv_se_e32m4(<8 x float> %vd, <8 x i32> %vs2, <8 x i32> %vs1, iXLen %vl) { 2673; CHECK-LABEL: test_sf_vc_fv_fvv_se_e32m4: 2674; CHECK: # %bb.0: # %entry 2675; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma 2676; CHECK-NEXT: sf.vc.v.vvv 3, v8, v10, v12 2677; CHECK-NEXT: ret 2678entry: 2679 %0 = tail call <8 x float> @llvm.riscv.sf.vc.v.vvv.se.nxv8f32.nxv8i32.nxv8i32.iXLen(iXLen 3, <8 x float> %vd, <8 x i32> %vs2, <8 x i32> %vs1, iXLen %vl) 2680 ret <8 x float> %0 2681} 2682 2683declare <8 x float> @llvm.riscv.sf.vc.v.vvv.se.nxv8f32.nxv8i32.nxv8i32.iXLen(iXLen, <8 x float>, <8 x i32>, <8 x i32>, iXLen) 2684 2685define void @test_sf_vc_fvvv_se_e32m8(<16 x float> %vd, <16 x i32> %vs2, <16 x i32> %vs1, iXLen %vl) { 2686; CHECK-LABEL: test_sf_vc_fvvv_se_e32m8: 2687; CHECK: # %bb.0: # %entry 2688; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma 2689; CHECK-NEXT: sf.vc.vvv 3, v8, v12, v16 2690; CHECK-NEXT: ret 2691entry: 2692 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv16f32.nxv16i32.nxv16i32.iXLen(iXLen 3, <16 x float> %vd, <16 x i32> %vs2, <16 x i32> %vs1, iXLen %vl) 2693 ret void 2694} 2695 2696declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv16f32.nxv16i32.nxv16i32.iXLen(iXLen, <16 x float>, <16 x i32>, <16 x i32>, iXLen) 2697 2698define <16 x float> @test_sf_vc_fv_fvv_se_e32m8(<16 x float> %vd, <16 x i32> %vs2, <16 x i32> %vs1, iXLen %vl) { 2699; CHECK-LABEL: test_sf_vc_fv_fvv_se_e32m8: 2700; CHECK: # %bb.0: # %entry 2701; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma 2702; CHECK-NEXT: sf.vc.v.vvv 3, v8, v12, v16 2703; CHECK-NEXT: ret 2704entry: 2705 %0 = tail call <16 x float> @llvm.riscv.sf.vc.v.vvv.se.nxv16f32.nxv16i32.nxv16i32.iXLen(iXLen 3, <16 x float> %vd, <16 x i32> %vs2, <16 x i32> %vs1, iXLen %vl) 2706 ret <16 x float> %0 2707} 2708 2709declare <16 x float> @llvm.riscv.sf.vc.v.vvv.se.nxv16f32.nxv16i32.nxv16i32.iXLen(iXLen, <16 x float>, <16 x i32>, <16 x i32>, iXLen) 2710 2711define void @test_sf_vc_fvvv_se_e64m1(<1 x double> %vd, <1 x i64> %vs2, <1 x i64> %vs1, iXLen %vl) { 2712; CHECK-LABEL: test_sf_vc_fvvv_se_e64m1: 2713; CHECK: # %bb.0: # %entry 2714; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma 2715; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 2716; CHECK-NEXT: ret 2717entry: 2718 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1f64.nxv1i64.nxv1i64.iXLen(iXLen 3, <1 x double> %vd, <1 x i64> %vs2, <1 x i64> %vs1, iXLen %vl) 2719 ret void 2720} 2721 2722declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1f64.nxv1i64.nxv1i64.iXLen(iXLen, <1 x double>, <1 x i64>, <1 x i64>, iXLen) 2723 2724define <1 x double> @test_sf_vc_fv_fvv_se_e64m1(<1 x double> %vd, <1 x i64> %vs2, <1 x i64> %vs1, iXLen %vl) { 2725; CHECK-LABEL: test_sf_vc_fv_fvv_se_e64m1: 2726; CHECK: # %bb.0: # %entry 2727; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma 2728; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 2729; CHECK-NEXT: ret 2730entry: 2731 %0 = tail call <1 x double> @llvm.riscv.sf.vc.v.vvv.se.nxv1f64.nxv1i64.nxv1i64.iXLen(iXLen 3, <1 x double> %vd, <1 x i64> %vs2, <1 x i64> %vs1, iXLen %vl) 2732 ret <1 x double> %0 2733} 2734 2735declare <1 x double> @llvm.riscv.sf.vc.v.vvv.se.nxv1f64.nxv1i64.nxv1i64.iXLen(iXLen, <1 x double>, <1 x i64>, <1 x i64>, iXLen) 2736 2737define void @test_sf_vc_fvvv_se_e64m2(<2 x double> %vd, <2 x i64> %vs2, <2 x i64> %vs1, iXLen %vl) { 2738; CHECK-LABEL: test_sf_vc_fvvv_se_e64m2: 2739; CHECK: # %bb.0: # %entry 2740; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma 2741; CHECK-NEXT: sf.vc.vvv 3, v8, v9, v10 2742; CHECK-NEXT: ret 2743entry: 2744 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2f64.nxv2i64.nxv2i64.iXLen(iXLen 3, <2 x double> %vd, <2 x i64> %vs2, <2 x i64> %vs1, iXLen %vl) 2745 ret void 2746} 2747 2748declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2f64.nxv2i64.nxv2i64.iXLen(iXLen, <2 x double>, <2 x i64>, <2 x i64>, iXLen) 2749 2750define <2 x double> @test_sf_vc_fv_fvv_se_e64m2(<2 x double> %vd, <2 x i64> %vs2, <2 x i64> %vs1, iXLen %vl) { 2751; CHECK-LABEL: test_sf_vc_fv_fvv_se_e64m2: 2752; CHECK: # %bb.0: # %entry 2753; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma 2754; CHECK-NEXT: sf.vc.v.vvv 3, v8, v9, v10 2755; CHECK-NEXT: ret 2756entry: 2757 %0 = tail call <2 x double> @llvm.riscv.sf.vc.v.vvv.se.nxv2f64.nxv2i64.nxv2i64.iXLen(iXLen 3, <2 x double> %vd, <2 x i64> %vs2, <2 x i64> %vs1, iXLen %vl) 2758 ret <2 x double> %0 2759} 2760 2761declare <2 x double> @llvm.riscv.sf.vc.v.vvv.se.nxv2f64.nxv2i64.nxv2i64.iXLen(iXLen, <2 x double>, <2 x i64>, <2 x i64>, iXLen) 2762 2763define void @test_sf_vc_fvvv_se_e64m4(<4 x double> %vd, <4 x i64> %vs2, <4 x i64> %vs1, iXLen %vl) { 2764; CHECK-LABEL: test_sf_vc_fvvv_se_e64m4: 2765; CHECK: # %bb.0: # %entry 2766; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma 2767; CHECK-NEXT: sf.vc.vvv 3, v8, v10, v12 2768; CHECK-NEXT: ret 2769entry: 2770 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4f64.nxv4i64.nxv4i64.iXLen(iXLen 3, <4 x double> %vd, <4 x i64> %vs2, <4 x i64> %vs1, iXLen %vl) 2771 ret void 2772} 2773 2774declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4f64.nxv4i64.nxv4i64.iXLen(iXLen, <4 x double>, <4 x i64>, <4 x i64>, iXLen) 2775 2776define <4 x double> @test_sf_vc_fv_fvv_se_e64m4(<4 x double> %vd, <4 x i64> %vs2, <4 x i64> %vs1, iXLen %vl) { 2777; CHECK-LABEL: test_sf_vc_fv_fvv_se_e64m4: 2778; CHECK: # %bb.0: # %entry 2779; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma 2780; CHECK-NEXT: sf.vc.v.vvv 3, v8, v10, v12 2781; CHECK-NEXT: ret 2782entry: 2783 %0 = tail call <4 x double> @llvm.riscv.sf.vc.v.vvv.se.nxv4f64.nxv4i64.nxv4i64.iXLen(iXLen 3, <4 x double> %vd, <4 x i64> %vs2, <4 x i64> %vs1, iXLen %vl) 2784 ret <4 x double> %0 2785} 2786 2787declare <4 x double> @llvm.riscv.sf.vc.v.vvv.se.nxv4f64.nxv4i64.nxv4i64.iXLen(iXLen, <4 x double>, <4 x i64>, <4 x i64>, iXLen) 2788 2789define void @test_sf_vc_fvvv_se_e64m8(<8 x double> %vd, <8 x i64> %vs2, <8 x i64> %vs1, iXLen %vl) { 2790; CHECK-LABEL: test_sf_vc_fvvv_se_e64m8: 2791; CHECK: # %bb.0: # %entry 2792; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma 2793; CHECK-NEXT: sf.vc.vvv 3, v8, v12, v16 2794; CHECK-NEXT: ret 2795entry: 2796 tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8f64.nxv8i64.nxv8i64.iXLen(iXLen 3, <8 x double> %vd, <8 x i64> %vs2, <8 x i64> %vs1, iXLen %vl) 2797 ret void 2798} 2799 2800declare void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8f64.nxv8i64.nxv8i64.iXLen(iXLen, <8 x double>, <8 x i64>, <8 x i64>, iXLen) 2801 2802define <8 x double> @test_sf_vc_fv_fvv_se_e64m8(<8 x double> %vd, <8 x i64> %vs2, <8 x i64> %vs1, iXLen %vl) { 2803; CHECK-LABEL: test_sf_vc_fv_fvv_se_e64m8: 2804; CHECK: # %bb.0: # %entry 2805; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma 2806; CHECK-NEXT: sf.vc.v.vvv 3, v8, v12, v16 2807; CHECK-NEXT: ret 2808entry: 2809 %0 = tail call <8 x double> @llvm.riscv.sf.vc.v.vvv.se.nxv8f64.nxv8i64.nxv8i64.iXLen(iXLen 3, <8 x double> %vd, <8 x i64> %vs2, <8 x i64> %vs1, iXLen %vl) 2810 ret <8 x double> %0 2811} 2812 2813declare <8 x double> @llvm.riscv.sf.vc.v.vvv.se.nxv8f64.nxv8i64.nxv8i64.iXLen(iXLen, <8 x double>, <8 x i64>, <8 x i64>, iXLen) 2814 2815define void @test_sf_vc_fvvx_se_e16mf4(<1 x half> %vd, <1 x i16> %vs2, i16 %rs1, iXLen %vl) { 2816; CHECK-LABEL: test_sf_vc_fvvx_se_e16mf4: 2817; CHECK: # %bb.0: # %entry 2818; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma 2819; CHECK-NEXT: sf.vc.xvv 3, v8, v9, a0 2820; CHECK-NEXT: ret 2821entry: 2822 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv1f16.nxv1i16.i16.iXLen(iXLen 3, <1 x half> %vd, <1 x i16> %vs2, i16 %rs1, iXLen %vl) 2823 ret void 2824} 2825 2826declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv1f16.nxv1i16.i16.iXLen(iXLen, <1 x half>, <1 x i16>, i16, iXLen) 2827 2828define <1 x half> @test_sf_vc_v_fvvx_se_e16mf4(<1 x half> %vd, <1 x i16> %vs2, i16 %rs1, iXLen %vl) { 2829; CHECK-LABEL: test_sf_vc_v_fvvx_se_e16mf4: 2830; CHECK: # %bb.0: # %entry 2831; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, ma 2832; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 2833; CHECK-NEXT: ret 2834entry: 2835 %0 = tail call <1 x half> @llvm.riscv.sf.vc.v.xvv.se.nxv1f16.nxv1f16.nxv1i16.i16.iXLen(iXLen 3, <1 x half> %vd, <1 x i16> %vs2, i16 %rs1, iXLen %vl) 2836 ret <1 x half> %0 2837} 2838 2839declare <1 x half> @llvm.riscv.sf.vc.v.xvv.se.nxv1f16.nxv1f16.nxv1i16.i16.iXLen(iXLen, <1 x half>, <1 x i16>, i16, iXLen) 2840 2841define void @test_sf_vc_fvvx_se_e16mf2(<2 x half> %vd, <2 x i16> %vs2, i16 %rs1, iXLen %vl) { 2842; CHECK-LABEL: test_sf_vc_fvvx_se_e16mf2: 2843; CHECK: # %bb.0: # %entry 2844; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma 2845; CHECK-NEXT: sf.vc.xvv 3, v8, v9, a0 2846; CHECK-NEXT: ret 2847entry: 2848 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv2f16.nxv2i16.i16.iXLen(iXLen 3, <2 x half> %vd, <2 x i16> %vs2, i16 %rs1, iXLen %vl) 2849 ret void 2850} 2851 2852declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv2f16.nxv2i16.i16.iXLen(iXLen, <2 x half>, <2 x i16>, i16, iXLen) 2853 2854define <2 x half> @test_sf_vc_v_fvvx_se_e16mf2(<2 x half> %vd, <2 x i16> %vs2, i16 %rs1, iXLen %vl) { 2855; CHECK-LABEL: test_sf_vc_v_fvvx_se_e16mf2: 2856; CHECK: # %bb.0: # %entry 2857; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, ma 2858; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 2859; CHECK-NEXT: ret 2860entry: 2861 %0 = tail call <2 x half> @llvm.riscv.sf.vc.v.xvv.se.nxv2f16.nxv2f16.nxv2i16.i16.iXLen(iXLen 3, <2 x half> %vd, <2 x i16> %vs2, i16 %rs1, iXLen %vl) 2862 ret <2 x half> %0 2863} 2864 2865declare <2 x half> @llvm.riscv.sf.vc.v.xvv.se.nxv2f16.nxv2f16.nxv2i16.i16.iXLen(iXLen, <2 x half>, <2 x i16>, i16, iXLen) 2866 2867define void @test_sf_vc_fvvx_se_e16m1(<4 x half> %vd, <4 x i16> %vs2, i16 %rs1, iXLen %vl) { 2868; CHECK-LABEL: test_sf_vc_fvvx_se_e16m1: 2869; CHECK: # %bb.0: # %entry 2870; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma 2871; CHECK-NEXT: sf.vc.xvv 3, v8, v9, a0 2872; CHECK-NEXT: ret 2873entry: 2874 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv4f16.nxv4i16.i16.iXLen(iXLen 3, <4 x half> %vd, <4 x i16> %vs2, i16 %rs1, iXLen %vl) 2875 ret void 2876} 2877 2878declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv4f16.nxv4i16.i16.iXLen(iXLen, <4 x half>, <4 x i16>, i16, iXLen) 2879 2880define <4 x half> @test_sf_vc_v_fvvx_se_e16m1(<4 x half> %vd, <4 x i16> %vs2, i16 %rs1, iXLen %vl) { 2881; CHECK-LABEL: test_sf_vc_v_fvvx_se_e16m1: 2882; CHECK: # %bb.0: # %entry 2883; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, ma 2884; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 2885; CHECK-NEXT: ret 2886entry: 2887 %0 = tail call <4 x half> @llvm.riscv.sf.vc.v.xvv.se.nxv4f16.nxv4f16.nxv4i16.i16.iXLen(iXLen 3, <4 x half> %vd, <4 x i16> %vs2, i16 %rs1, iXLen %vl) 2888 ret <4 x half> %0 2889} 2890 2891declare <4 x half> @llvm.riscv.sf.vc.v.xvv.se.nxv4f16.nxv4f16.nxv4i16.i16.iXLen(iXLen, <4 x half>, <4 x i16>, i16, iXLen) 2892 2893define void @test_sf_vc_fvvx_se_e16m2(<8 x half> %vd, <8 x i16> %vs2, i16 %rs1, iXLen %vl) { 2894; CHECK-LABEL: test_sf_vc_fvvx_se_e16m2: 2895; CHECK: # %bb.0: # %entry 2896; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma 2897; CHECK-NEXT: sf.vc.xvv 3, v8, v9, a0 2898; CHECK-NEXT: ret 2899entry: 2900 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv8f16.nxv8i16.i16.iXLen(iXLen 3, <8 x half> %vd, <8 x i16> %vs2, i16 %rs1, iXLen %vl) 2901 ret void 2902} 2903 2904declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv8f16.nxv8i16.i16.iXLen(iXLen, <8 x half>, <8 x i16>, i16, iXLen) 2905 2906define <8 x half> @test_sf_vc_v_fvvx_se_e16m2(<8 x half> %vd, <8 x i16> %vs2, i16 %rs1, iXLen %vl) { 2907; CHECK-LABEL: test_sf_vc_v_fvvx_se_e16m2: 2908; CHECK: # %bb.0: # %entry 2909; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma 2910; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 2911; CHECK-NEXT: ret 2912entry: 2913 %0 = tail call <8 x half> @llvm.riscv.sf.vc.v.xvv.se.nxv8f16.nxv8f16.nxv8i16.i16.iXLen(iXLen 3, <8 x half> %vd, <8 x i16> %vs2, i16 %rs1, iXLen %vl) 2914 ret <8 x half> %0 2915} 2916 2917declare <8 x half> @llvm.riscv.sf.vc.v.xvv.se.nxv8f16.nxv8f16.nxv8i16.i16.iXLen(iXLen, <8 x half>, <8 x i16>, i16, iXLen) 2918 2919define void @test_sf_vc_fvvx_se_e16m4(<16 x half> %vd, <16 x i16> %vs2, i16 %rs1, iXLen %vl) { 2920; CHECK-LABEL: test_sf_vc_fvvx_se_e16m4: 2921; CHECK: # %bb.0: # %entry 2922; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma 2923; CHECK-NEXT: sf.vc.xvv 3, v8, v10, a0 2924; CHECK-NEXT: ret 2925entry: 2926 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv16f16.nxv16i16.i16.iXLen(iXLen 3, <16 x half> %vd, <16 x i16> %vs2, i16 %rs1, iXLen %vl) 2927 ret void 2928} 2929 2930declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv16f16.nxv16i16.i16.iXLen(iXLen, <16 x half>, <16 x i16>, i16, iXLen) 2931 2932define <16 x half> @test_sf_vc_v_fvvx_se_e16m4(<16 x half> %vd, <16 x i16> %vs2, i16 %rs1, iXLen %vl) { 2933; CHECK-LABEL: test_sf_vc_v_fvvx_se_e16m4: 2934; CHECK: # %bb.0: # %entry 2935; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, ma 2936; CHECK-NEXT: sf.vc.v.xvv 3, v8, v10, a0 2937; CHECK-NEXT: ret 2938entry: 2939 %0 = tail call <16 x half> @llvm.riscv.sf.vc.v.xvv.se.nxv16f16.nxv16f16.nxv16i16.i16.iXLen(iXLen 3, <16 x half> %vd, <16 x i16> %vs2, i16 %rs1, iXLen %vl) 2940 ret <16 x half> %0 2941} 2942 2943declare <16 x half> @llvm.riscv.sf.vc.v.xvv.se.nxv16f16.nxv16f16.nxv16i16.i16.iXLen(iXLen, <16 x half>, <16 x i16>, i16, iXLen) 2944 2945define void @test_sf_vc_fvvx_se_e16m8(<32 x half> %vd, <32 x i16> %vs2, i16 %rs1, iXLen %vl) { 2946; CHECK-LABEL: test_sf_vc_fvvx_se_e16m8: 2947; CHECK: # %bb.0: # %entry 2948; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma 2949; CHECK-NEXT: sf.vc.xvv 3, v8, v12, a0 2950; CHECK-NEXT: ret 2951entry: 2952 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv32f16.nxv32i16.i16.iXLen(iXLen 3, <32 x half> %vd, <32 x i16> %vs2, i16 %rs1, iXLen %vl) 2953 ret void 2954} 2955 2956declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv32f16.nxv32i16.i16.iXLen(iXLen, <32 x half>, <32 x i16>, i16, iXLen) 2957 2958define <32 x half> @test_sf_vc_v_fvvx_se_e16m8(<32 x half> %vd, <32 x i16> %vs2, i16 %rs1, iXLen %vl) { 2959; CHECK-LABEL: test_sf_vc_v_fvvx_se_e16m8: 2960; CHECK: # %bb.0: # %entry 2961; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, ma 2962; CHECK-NEXT: sf.vc.v.xvv 3, v8, v12, a0 2963; CHECK-NEXT: ret 2964entry: 2965 %0 = tail call <32 x half> @llvm.riscv.sf.vc.v.xvv.se.nxv32f16.nxv32f16.nxv32i16.i16.iXLen(iXLen 3, <32 x half> %vd, <32 x i16> %vs2, i16 %rs1, iXLen %vl) 2966 ret <32 x half> %0 2967} 2968 2969declare <32 x half> @llvm.riscv.sf.vc.v.xvv.se.nxv32f16.nxv32f16.nxv32i16.i16.iXLen(iXLen, <32 x half>, <32 x i16>, i16, iXLen) 2970 2971define void @test_sf_vc_fvvx_se_e32mf2(<1 x float> %vd, <1 x i32> %vs2, i32 %rs1, iXLen %vl) { 2972; CHECK-LABEL: test_sf_vc_fvvx_se_e32mf2: 2973; CHECK: # %bb.0: # %entry 2974; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma 2975; CHECK-NEXT: sf.vc.xvv 3, v8, v9, a0 2976; CHECK-NEXT: ret 2977entry: 2978 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv1f32.nxv1i32.i32.iXLen(iXLen 3, <1 x float> %vd, <1 x i32> %vs2, i32 %rs1, iXLen %vl) 2979 ret void 2980} 2981 2982declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv1f32.nxv1i32.i32.iXLen(iXLen, <1 x float>, <1 x i32>, i32, iXLen) 2983 2984define <1 x float> @test_sf_vc_v_fvvx_se_e32mf2(<1 x float> %vd, <1 x i32> %vs2, i32 %rs1, iXLen %vl) { 2985; CHECK-LABEL: test_sf_vc_v_fvvx_se_e32mf2: 2986; CHECK: # %bb.0: # %entry 2987; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma 2988; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 2989; CHECK-NEXT: ret 2990entry: 2991 %0 = tail call <1 x float> @llvm.riscv.sf.vc.v.xvv.se.nxv1f32.nxv1f32.nxv1i32.i32.iXLen(iXLen 3, <1 x float> %vd, <1 x i32> %vs2, i32 %rs1, iXLen %vl) 2992 ret <1 x float> %0 2993} 2994 2995declare <1 x float> @llvm.riscv.sf.vc.v.xvv.se.nxv1f32.nxv1f32.nxv1i32.i32.iXLen(iXLen, <1 x float>, <1 x i32>, i32, iXLen) 2996 2997define void @test_sf_vc_fvvx_se_e32m1(<2 x float> %vd, <2 x i32> %vs2, i32 %rs1, iXLen %vl) { 2998; CHECK-LABEL: test_sf_vc_fvvx_se_e32m1: 2999; CHECK: # %bb.0: # %entry 3000; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma 3001; CHECK-NEXT: sf.vc.xvv 3, v8, v9, a0 3002; CHECK-NEXT: ret 3003entry: 3004 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv2f32.nxv2i32.i32.iXLen(iXLen 3, <2 x float> %vd, <2 x i32> %vs2, i32 %rs1, iXLen %vl) 3005 ret void 3006} 3007 3008declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv2f32.nxv2i32.i32.iXLen(iXLen, <2 x float>, <2 x i32>, i32, iXLen) 3009 3010define <2 x float> @test_sf_vc_v_fvvx_se_e32m1(<2 x float> %vd, <2 x i32> %vs2, i32 %rs1, iXLen %vl) { 3011; CHECK-LABEL: test_sf_vc_v_fvvx_se_e32m1: 3012; CHECK: # %bb.0: # %entry 3013; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma 3014; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 3015; CHECK-NEXT: ret 3016entry: 3017 %0 = tail call <2 x float> @llvm.riscv.sf.vc.v.xvv.se.nxv2f32.nxv2f32.nxv2i32.i32.iXLen(iXLen 3, <2 x float> %vd, <2 x i32> %vs2, i32 %rs1, iXLen %vl) 3018 ret <2 x float> %0 3019} 3020 3021declare <2 x float> @llvm.riscv.sf.vc.v.xvv.se.nxv2f32.nxv2f32.nxv2i32.i32.iXLen(iXLen, <2 x float>, <2 x i32>, i32, iXLen) 3022 3023define void @test_sf_vc_fvvx_se_e32m2(<4 x float> %vd, <4 x i32> %vs2, i32 %rs1, iXLen %vl) { 3024; CHECK-LABEL: test_sf_vc_fvvx_se_e32m2: 3025; CHECK: # %bb.0: # %entry 3026; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma 3027; CHECK-NEXT: sf.vc.xvv 3, v8, v9, a0 3028; CHECK-NEXT: ret 3029entry: 3030 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv4f32.nxv4i32.i32.iXLen(iXLen 3, <4 x float> %vd, <4 x i32> %vs2, i32 %rs1, iXLen %vl) 3031 ret void 3032} 3033 3034declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv4f32.nxv4i32.i32.iXLen(iXLen, <4 x float>, <4 x i32>, i32, iXLen) 3035 3036define <4 x float> @test_sf_vc_v_fvvx_se_e32m2(<4 x float> %vd, <4 x i32> %vs2, i32 %rs1, iXLen %vl) { 3037; CHECK-LABEL: test_sf_vc_v_fvvx_se_e32m2: 3038; CHECK: # %bb.0: # %entry 3039; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma 3040; CHECK-NEXT: sf.vc.v.xvv 3, v8, v9, a0 3041; CHECK-NEXT: ret 3042entry: 3043 %0 = tail call <4 x float> @llvm.riscv.sf.vc.v.xvv.se.nxv4f32.nxv4f32.nxv4i32.i32.iXLen(iXLen 3, <4 x float> %vd, <4 x i32> %vs2, i32 %rs1, iXLen %vl) 3044 ret <4 x float> %0 3045} 3046 3047declare <4 x float> @llvm.riscv.sf.vc.v.xvv.se.nxv4f32.nxv4f32.nxv4i32.i32.iXLen(iXLen, <4 x float>, <4 x i32>, i32, iXLen) 3048 3049define void @test_sf_vc_fvvx_se_e32m4(<8 x float> %vd, <8 x i32> %vs2, i32 %rs1, iXLen %vl) { 3050; CHECK-LABEL: test_sf_vc_fvvx_se_e32m4: 3051; CHECK: # %bb.0: # %entry 3052; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma 3053; CHECK-NEXT: sf.vc.xvv 3, v8, v10, a0 3054; CHECK-NEXT: ret 3055entry: 3056 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv8f32.nxv8i32.i32.iXLen(iXLen 3, <8 x float> %vd, <8 x i32> %vs2, i32 %rs1, iXLen %vl) 3057 ret void 3058} 3059 3060declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv8f32.nxv8i32.i32.iXLen(iXLen, <8 x float>, <8 x i32>, i32, iXLen) 3061 3062define <8 x float> @test_sf_vc_v_fvvx_se_e32m4(<8 x float> %vd, <8 x i32> %vs2, i32 %rs1, iXLen %vl) { 3063; CHECK-LABEL: test_sf_vc_v_fvvx_se_e32m4: 3064; CHECK: # %bb.0: # %entry 3065; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma 3066; CHECK-NEXT: sf.vc.v.xvv 3, v8, v10, a0 3067; CHECK-NEXT: ret 3068entry: 3069 %0 = tail call <8 x float> @llvm.riscv.sf.vc.v.xvv.se.nxv8f32.nxv8f32.nxv8i32.i32.iXLen(iXLen 3, <8 x float> %vd, <8 x i32> %vs2, i32 %rs1, iXLen %vl) 3070 ret <8 x float> %0 3071} 3072 3073declare <8 x float> @llvm.riscv.sf.vc.v.xvv.se.nxv8f32.nxv8f32.nxv8i32.i32.iXLen(iXLen, <8 x float>, <8 x i32>, i32, iXLen) 3074 3075define void @test_sf_vc_fvvx_se_e32m8(<16 x float> %vd, <16 x i32> %vs2, i32 %rs1, iXLen %vl) { 3076; CHECK-LABEL: test_sf_vc_fvvx_se_e32m8: 3077; CHECK: # %bb.0: # %entry 3078; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma 3079; CHECK-NEXT: sf.vc.xvv 3, v8, v12, a0 3080; CHECK-NEXT: ret 3081entry: 3082 tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv16f32.nxv16i32.i32.iXLen(iXLen 3, <16 x float> %vd, <16 x i32> %vs2, i32 %rs1, iXLen %vl) 3083 ret void 3084} 3085 3086declare void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv16f32.nxv16i32.i32.iXLen(iXLen, <16 x float>, <16 x i32>, i32, iXLen) 3087 3088define <16 x float> @test_sf_vc_v_fvvx_se_e32m8(<16 x float> %vd, <16 x i32> %vs2, i32 %rs1, iXLen %vl) { 3089; CHECK-LABEL: test_sf_vc_v_fvvx_se_e32m8: 3090; CHECK: # %bb.0: # %entry 3091; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma 3092; CHECK-NEXT: sf.vc.v.xvv 3, v8, v12, a0 3093; CHECK-NEXT: ret 3094entry: 3095 %0 = tail call <16 x float> @llvm.riscv.sf.vc.v.xvv.se.nxv16f32.nxv16f32.nxv16i32.i32.iXLen(iXLen 3, <16 x float> %vd, <16 x i32> %vs2, i32 %rs1, iXLen %vl) 3096 ret <16 x float> %0 3097} 3098 3099declare <16 x float> @llvm.riscv.sf.vc.v.xvv.se.nxv16f32.nxv16f32.nxv16i32.i32.iXLen(iXLen, <16 x float>, <16 x i32>, i32, iXLen) 3100 3101define void @test_sf_vc_fvvi_se_e16mf4(<1 x half> %vd, <1 x i16> %vs2, iXLen %vl) { 3102; CHECK-LABEL: test_sf_vc_fvvi_se_e16mf4: 3103; CHECK: # %bb.0: # %entry 3104; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma 3105; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 3 3106; CHECK-NEXT: ret 3107entry: 3108 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv1f16.nxv1i16.iXLen.iXLen(iXLen 3, <1 x half> %vd, <1 x i16> %vs2, iXLen 3, iXLen %vl) 3109 ret void 3110} 3111 3112declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv1f16.nxv1i16.iXLen.iXLen(iXLen, <1 x half>, <1 x i16>, iXLen, iXLen) 3113 3114define <1 x half> @test_sf_vc_fv_fvvi_se_e16mf4(<1 x half> %vd, <1 x i16> %vs2, iXLen %vl) { 3115; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e16mf4: 3116; CHECK: # %bb.0: # %entry 3117; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma 3118; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 3 3119; CHECK-NEXT: ret 3120entry: 3121 %0 = tail call <1 x half> @llvm.riscv.sf.vc.v.ivv.se.nxv1f16.nxv1f16.nxv1i16.iXLen.iXLen(iXLen 3, <1 x half> %vd, <1 x i16> %vs2, iXLen 3, iXLen %vl) 3122 ret <1 x half> %0 3123} 3124 3125declare <1 x half> @llvm.riscv.sf.vc.v.ivv.se.nxv1f16.nxv1f16.nxv1i16.iXLen.iXLen(iXLen, <1 x half>, <1 x i16>, iXLen, iXLen) 3126 3127define void @test_sf_vc_fvvi_se_e16mf2(<2 x half> %vd, <2 x i16> %vs2, iXLen %vl) { 3128; CHECK-LABEL: test_sf_vc_fvvi_se_e16mf2: 3129; CHECK: # %bb.0: # %entry 3130; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma 3131; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 3 3132; CHECK-NEXT: ret 3133entry: 3134 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv2f16.nxv2i16.iXLen.iXLen(iXLen 3, <2 x half> %vd, <2 x i16> %vs2, iXLen 3, iXLen %vl) 3135 ret void 3136} 3137 3138declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv2f16.nxv2i16.iXLen.iXLen(iXLen, <2 x half>, <2 x i16>, iXLen, iXLen) 3139 3140define <2 x half> @test_sf_vc_fv_fvvi_se_e16mf2(<2 x half> %vd, <2 x i16> %vs2, iXLen %vl) { 3141; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e16mf2: 3142; CHECK: # %bb.0: # %entry 3143; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma 3144; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 3 3145; CHECK-NEXT: ret 3146entry: 3147 %0 = tail call <2 x half> @llvm.riscv.sf.vc.v.ivv.se.nxv2f16.nxv2f16.nxv2i16.iXLen.iXLen(iXLen 3, <2 x half> %vd, <2 x i16> %vs2, iXLen 3, iXLen %vl) 3148 ret <2 x half> %0 3149} 3150 3151declare <2 x half> @llvm.riscv.sf.vc.v.ivv.se.nxv2f16.nxv2f16.nxv2i16.iXLen.iXLen(iXLen, <2 x half>, <2 x i16>, iXLen, iXLen) 3152 3153define void @test_sf_vc_fvvi_se_e16m1(<4 x half> %vd, <4 x i16> %vs2, iXLen %vl) { 3154; CHECK-LABEL: test_sf_vc_fvvi_se_e16m1: 3155; CHECK: # %bb.0: # %entry 3156; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 3157; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 3 3158; CHECK-NEXT: ret 3159entry: 3160 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv4f16.nxv4i16.iXLen.iXLen(iXLen 3, <4 x half> %vd, <4 x i16> %vs2, iXLen 3, iXLen %vl) 3161 ret void 3162} 3163 3164declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv4f16.nxv4i16.iXLen.iXLen(iXLen, <4 x half>, <4 x i16>, iXLen, iXLen) 3165 3166define <4 x half> @test_sf_vc_fv_fvvi_se_e16m1(<4 x half> %vd, <4 x i16> %vs2, iXLen %vl) { 3167; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e16m1: 3168; CHECK: # %bb.0: # %entry 3169; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma 3170; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 3 3171; CHECK-NEXT: ret 3172entry: 3173 %0 = tail call <4 x half> @llvm.riscv.sf.vc.v.ivv.se.nxv4f16.nxv4f16.nxv4i16.iXLen.iXLen(iXLen 3, <4 x half> %vd, <4 x i16> %vs2, iXLen 3, iXLen %vl) 3174 ret <4 x half> %0 3175} 3176 3177declare <4 x half> @llvm.riscv.sf.vc.v.ivv.se.nxv4f16.nxv4f16.nxv4i16.iXLen.iXLen(iXLen, <4 x half>, <4 x i16>, iXLen, iXLen) 3178 3179define void @test_sf_vc_fvvi_se_e16m2(<8 x half> %vd, <8 x i16> %vs2, iXLen %vl) { 3180; CHECK-LABEL: test_sf_vc_fvvi_se_e16m2: 3181; CHECK: # %bb.0: # %entry 3182; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma 3183; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 3 3184; CHECK-NEXT: ret 3185entry: 3186 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv8f16.nxv8i16.iXLen.iXLen(iXLen 3, <8 x half> %vd, <8 x i16> %vs2, iXLen 3, iXLen %vl) 3187 ret void 3188} 3189 3190declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv8f16.nxv8i16.iXLen.iXLen(iXLen, <8 x half>, <8 x i16>, iXLen, iXLen) 3191 3192define <8 x half> @test_sf_vc_fv_fvvi_se_e16m2(<8 x half> %vd, <8 x i16> %vs2, iXLen %vl) { 3193; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e16m2: 3194; CHECK: # %bb.0: # %entry 3195; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma 3196; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 3 3197; CHECK-NEXT: ret 3198entry: 3199 %0 = tail call <8 x half> @llvm.riscv.sf.vc.v.ivv.se.nxv8f16.nxv8f16.nxv8i16.iXLen.iXLen(iXLen 3, <8 x half> %vd, <8 x i16> %vs2, iXLen 3, iXLen %vl) 3200 ret <8 x half> %0 3201} 3202 3203declare <8 x half> @llvm.riscv.sf.vc.v.ivv.se.nxv8f16.nxv8f16.nxv8i16.iXLen.iXLen(iXLen, <8 x half>, <8 x i16>, iXLen, iXLen) 3204 3205define void @test_sf_vc_fvvi_se_e16m4(<16 x half> %vd, <16 x i16> %vs2, iXLen %vl) { 3206; CHECK-LABEL: test_sf_vc_fvvi_se_e16m4: 3207; CHECK: # %bb.0: # %entry 3208; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma 3209; CHECK-NEXT: sf.vc.ivv 3, v8, v10, 3 3210; CHECK-NEXT: ret 3211entry: 3212 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv16f16.nxv16i16.iXLen.iXLen(iXLen 3, <16 x half> %vd, <16 x i16> %vs2, iXLen 3, iXLen %vl) 3213 ret void 3214} 3215 3216declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv16f16.nxv16i16.iXLen.iXLen(iXLen, <16 x half>, <16 x i16>, iXLen, iXLen) 3217 3218define <16 x half> @test_sf_vc_fv_fvvi_se_e16m4(<16 x half> %vd, <16 x i16> %vs2, iXLen %vl) { 3219; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e16m4: 3220; CHECK: # %bb.0: # %entry 3221; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma 3222; CHECK-NEXT: sf.vc.v.ivv 3, v8, v10, 3 3223; CHECK-NEXT: ret 3224entry: 3225 %0 = tail call <16 x half> @llvm.riscv.sf.vc.v.ivv.se.nxv16f16.nxv16f16.nxv16i16.iXLen.iXLen(iXLen 3, <16 x half> %vd, <16 x i16> %vs2, iXLen 3, iXLen %vl) 3226 ret <16 x half> %0 3227} 3228 3229declare <16 x half> @llvm.riscv.sf.vc.v.ivv.se.nxv16f16.nxv16f16.nxv16i16.iXLen.iXLen(iXLen, <16 x half>, <16 x i16>, iXLen, iXLen) 3230 3231define void @test_sf_vc_fvvi_se_e16m8(<32 x half> %vd, <32 x i16> %vs2, iXLen %vl) { 3232; CHECK-LABEL: test_sf_vc_fvvi_se_e16m8: 3233; CHECK: # %bb.0: # %entry 3234; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma 3235; CHECK-NEXT: sf.vc.ivv 3, v8, v12, 3 3236; CHECK-NEXT: ret 3237entry: 3238 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv32f16.nxv32i16.iXLen.iXLen(iXLen 3, <32 x half> %vd, <32 x i16> %vs2, iXLen 3, iXLen %vl) 3239 ret void 3240} 3241 3242declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv32f16.nxv32i16.iXLen.iXLen(iXLen, <32 x half>, <32 x i16>, iXLen, iXLen) 3243 3244define <32 x half> @test_sf_vc_fv_fvvi_se_e16m8(<32 x half> %vd, <32 x i16> %vs2, iXLen %vl) { 3245; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e16m8: 3246; CHECK: # %bb.0: # %entry 3247; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma 3248; CHECK-NEXT: sf.vc.v.ivv 3, v8, v12, 3 3249; CHECK-NEXT: ret 3250entry: 3251 %0 = tail call <32 x half> @llvm.riscv.sf.vc.v.ivv.se.nxv32f16.nxv32f16.nxv32i16.iXLen.iXLen(iXLen 3, <32 x half> %vd, <32 x i16> %vs2, iXLen 3, iXLen %vl) 3252 ret <32 x half> %0 3253} 3254 3255declare <32 x half> @llvm.riscv.sf.vc.v.ivv.se.nxv32f16.nxv32f16.nxv32i16.iXLen.iXLen(iXLen, <32 x half>, <32 x i16>, iXLen, iXLen) 3256 3257define void @test_sf_vc_fvvi_se_e32mf2(<1 x float> %vd, <1 x i32> %vs2, iXLen %vl) { 3258; CHECK-LABEL: test_sf_vc_fvvi_se_e32mf2: 3259; CHECK: # %bb.0: # %entry 3260; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma 3261; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 3 3262; CHECK-NEXT: ret 3263entry: 3264 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv1f32.nxv1i32.iXLen.iXLen(iXLen 3, <1 x float> %vd, <1 x i32> %vs2, iXLen 3, iXLen %vl) 3265 ret void 3266} 3267 3268declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv1f32.nxv1i32.iXLen.iXLen(iXLen, <1 x float>, <1 x i32>, iXLen, iXLen) 3269 3270define <1 x float> @test_sf_vc_fv_fvvi_se_e32mf2(<1 x float> %vd, <1 x i32> %vs2, iXLen %vl) { 3271; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e32mf2: 3272; CHECK: # %bb.0: # %entry 3273; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma 3274; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 3 3275; CHECK-NEXT: ret 3276entry: 3277 %0 = tail call <1 x float> @llvm.riscv.sf.vc.v.ivv.se.nxv1f32.nxv1f32.nxv1i32.iXLen.iXLen(iXLen 3, <1 x float> %vd, <1 x i32> %vs2, iXLen 3, iXLen %vl) 3278 ret <1 x float> %0 3279} 3280 3281declare <1 x float> @llvm.riscv.sf.vc.v.ivv.se.nxv1f32.nxv1f32.nxv1i32.iXLen.iXLen(iXLen, <1 x float>, <1 x i32>, iXLen, iXLen) 3282 3283define void @test_sf_vc_fvvi_se_e32m1(<2 x float> %vd, <2 x i32> %vs2, iXLen %vl) { 3284; CHECK-LABEL: test_sf_vc_fvvi_se_e32m1: 3285; CHECK: # %bb.0: # %entry 3286; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma 3287; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 3 3288; CHECK-NEXT: ret 3289entry: 3290 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv2f32.nxv2i32.iXLen.iXLen(iXLen 3, <2 x float> %vd, <2 x i32> %vs2, iXLen 3, iXLen %vl) 3291 ret void 3292} 3293 3294declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv2f32.nxv2i32.iXLen.iXLen(iXLen, <2 x float>, <2 x i32>, iXLen, iXLen) 3295 3296define <2 x float> @test_sf_vc_fv_fvvi_se_e32m1(<2 x float> %vd, <2 x i32> %vs2, iXLen %vl) { 3297; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e32m1: 3298; CHECK: # %bb.0: # %entry 3299; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma 3300; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 3 3301; CHECK-NEXT: ret 3302entry: 3303 %0 = tail call <2 x float> @llvm.riscv.sf.vc.v.ivv.se.nxv2f32.nxv2f32.nxv2i32.iXLen.iXLen(iXLen 3, <2 x float> %vd, <2 x i32> %vs2, iXLen 3, iXLen %vl) 3304 ret <2 x float> %0 3305} 3306 3307declare <2 x float> @llvm.riscv.sf.vc.v.ivv.se.nxv2f32.nxv2f32.nxv2i32.iXLen.iXLen(iXLen, <2 x float>, <2 x i32>, iXLen, iXLen) 3308 3309define void @test_sf_vc_fvvi_se_e32m2(<4 x float> %vd, <4 x i32> %vs2, iXLen %vl) { 3310; CHECK-LABEL: test_sf_vc_fvvi_se_e32m2: 3311; CHECK: # %bb.0: # %entry 3312; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 3313; CHECK-NEXT: sf.vc.ivv 3, v8, v9, 3 3314; CHECK-NEXT: ret 3315entry: 3316 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv4f32.nxv4i32.iXLen.iXLen(iXLen 3, <4 x float> %vd, <4 x i32> %vs2, iXLen 3, iXLen %vl) 3317 ret void 3318} 3319 3320declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv4f32.nxv4i32.iXLen.iXLen(iXLen, <4 x float>, <4 x i32>, iXLen, iXLen) 3321 3322define <4 x float> @test_sf_vc_fv_fvvi_se_e32m2(<4 x float> %vd, <4 x i32> %vs2, iXLen %vl) { 3323; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e32m2: 3324; CHECK: # %bb.0: # %entry 3325; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma 3326; CHECK-NEXT: sf.vc.v.ivv 3, v8, v9, 3 3327; CHECK-NEXT: ret 3328entry: 3329 %0 = tail call <4 x float> @llvm.riscv.sf.vc.v.ivv.se.nxv4f32.nxv4f32.nxv4i32.iXLen.iXLen(iXLen 3, <4 x float> %vd, <4 x i32> %vs2, iXLen 3, iXLen %vl) 3330 ret <4 x float> %0 3331} 3332 3333declare <4 x float> @llvm.riscv.sf.vc.v.ivv.se.nxv4f32.nxv4f32.nxv4i32.iXLen.iXLen(iXLen, <4 x float>, <4 x i32>, iXLen, iXLen) 3334 3335define void @test_sf_vc_fvvi_se_e32m4(<8 x float> %vd, <8 x i32> %vs2, iXLen %vl) { 3336; CHECK-LABEL: test_sf_vc_fvvi_se_e32m4: 3337; CHECK: # %bb.0: # %entry 3338; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma 3339; CHECK-NEXT: sf.vc.ivv 3, v8, v10, 3 3340; CHECK-NEXT: ret 3341entry: 3342 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv8f32.nxv8i32.iXLen.iXLen(iXLen 3, <8 x float> %vd, <8 x i32> %vs2, iXLen 3, iXLen %vl) 3343 ret void 3344} 3345 3346declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv8f32.nxv8i32.iXLen.iXLen(iXLen, <8 x float>, <8 x i32>, iXLen, iXLen) 3347 3348define <8 x float> @test_sf_vc_fv_fvvi_se_e32m4(<8 x float> %vd, <8 x i32> %vs2, iXLen %vl) { 3349; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e32m4: 3350; CHECK: # %bb.0: # %entry 3351; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma 3352; CHECK-NEXT: sf.vc.v.ivv 3, v8, v10, 3 3353; CHECK-NEXT: ret 3354entry: 3355 %0 = tail call <8 x float> @llvm.riscv.sf.vc.v.ivv.se.nxv8f32.nxv8f32.nxv8i32.iXLen.iXLen(iXLen 3, <8 x float> %vd, <8 x i32> %vs2, iXLen 3, iXLen %vl) 3356 ret <8 x float> %0 3357} 3358 3359declare <8 x float> @llvm.riscv.sf.vc.v.ivv.se.nxv8f32.nxv8f32.nxv8i32.iXLen.iXLen(iXLen, <8 x float>, <8 x i32>, iXLen, iXLen) 3360 3361define void @test_sf_vc_fvvi_se_e32m8(<16 x float> %vd, <16 x i32> %vs2, iXLen %vl) { 3362; CHECK-LABEL: test_sf_vc_fvvi_se_e32m8: 3363; CHECK: # %bb.0: # %entry 3364; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma 3365; CHECK-NEXT: sf.vc.ivv 3, v8, v12, 3 3366; CHECK-NEXT: ret 3367entry: 3368 tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv16f32.nxv16i32.iXLen.iXLen(iXLen 3, <16 x float> %vd, <16 x i32> %vs2, iXLen 3, iXLen %vl) 3369 ret void 3370} 3371 3372declare void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv16f32.nxv16i32.iXLen.iXLen(iXLen, <16 x float>, <16 x i32>, iXLen, iXLen) 3373 3374define <16 x float> @test_sf_vc_fv_fvvi_se_e32m8(<16 x float> %vd, <16 x i32> %vs2, iXLen %vl) { 3375; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e32m8: 3376; CHECK: # %bb.0: # %entry 3377; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma 3378; CHECK-NEXT: sf.vc.v.ivv 3, v8, v12, 3 3379; CHECK-NEXT: ret 3380entry: 3381 %0 = tail call <16 x float> @llvm.riscv.sf.vc.v.ivv.se.nxv16f32.nxv16f32.nxv16i32.iXLen.iXLen(iXLen 3, <16 x float> %vd, <16 x i32> %vs2, iXLen 3, iXLen %vl) 3382 ret <16 x float> %0 3383} 3384 3385declare <16 x float> @llvm.riscv.sf.vc.v.ivv.se.nxv16f32.nxv16f32.nxv16i32.iXLen.iXLen(iXLen, <16 x float>, <16 x i32>, iXLen, iXLen) 3386 3387define void @test_sf_vc_fvvf_se_e16mf4(<1 x half> %vd, <1 x i16> %vs2, half %rs1, iXLen %vl) { 3388; CHECK-LABEL: test_sf_vc_fvvf_se_e16mf4: 3389; CHECK: # %bb.0: # %entry 3390; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma 3391; CHECK-NEXT: sf.vc.fvv 1, v8, v9, fa0 3392; CHECK-NEXT: ret 3393entry: 3394 tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv1f16.nxv1i16.f16.iXLen(iXLen 1, <1 x half> %vd, <1 x i16> %vs2, half %rs1, iXLen %vl) 3395 ret void 3396} 3397 3398declare void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv1f16.nxv1i16.f16.iXLen(iXLen, <1 x half>, <1 x i16>, half, iXLen) 3399 3400define <1 x half> @test_sf_vc_fv_fvvf_se_e16mf4(<1 x half> %vd, <1 x i16> %vs2, half %rs1, iXLen %vl) { 3401; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e16mf4: 3402; CHECK: # %bb.0: # %entry 3403; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma 3404; CHECK-NEXT: sf.vc.v.fvv 1, v8, v9, fa0 3405; CHECK-NEXT: ret 3406entry: 3407 %0 = tail call <1 x half> @llvm.riscv.sf.vc.v.fvv.se.nxv1f16.nxv1f16.nxv1i16.f16.iXLen(iXLen 1, <1 x half> %vd, <1 x i16> %vs2, half %rs1, iXLen %vl) 3408 ret <1 x half> %0 3409} 3410 3411declare <1 x half> @llvm.riscv.sf.vc.v.fvv.se.nxv1f16.nxv1f16.nxv1i16.f16.iXLen(iXLen, <1 x half>, <1 x i16>, half %rs1, iXLen) 3412 3413define void @test_sf_vc_fvvf_se_e16mf2(<2 x half> %vd, <2 x i16> %vs2, half %rs1, iXLen %vl) { 3414; CHECK-LABEL: test_sf_vc_fvvf_se_e16mf2: 3415; CHECK: # %bb.0: # %entry 3416; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma 3417; CHECK-NEXT: sf.vc.fvv 1, v8, v9, fa0 3418; CHECK-NEXT: ret 3419entry: 3420 tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv2f16.nxv2i16.f16.iXLen(iXLen 1, <2 x half> %vd, <2 x i16> %vs2, half %rs1, iXLen %vl) 3421 ret void 3422} 3423 3424declare void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv2f16.nxv2i16.f16.iXLen(iXLen, <2 x half>, <2 x i16>, half, iXLen) 3425 3426define <2 x half> @test_sf_vc_fv_fvvf_se_e16mf2(<2 x half> %vd, <2 x i16> %vs2, half %rs1, iXLen %vl) { 3427; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e16mf2: 3428; CHECK: # %bb.0: # %entry 3429; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma 3430; CHECK-NEXT: sf.vc.v.fvv 1, v8, v9, fa0 3431; CHECK-NEXT: ret 3432entry: 3433 %0 = tail call <2 x half> @llvm.riscv.sf.vc.v.fvv.se.nxv2f16.nxv2f16.nxv2i16.f16.iXLen(iXLen 1, <2 x half> %vd, <2 x i16> %vs2, half %rs1, iXLen %vl) 3434 ret <2 x half> %0 3435} 3436 3437declare <2 x half> @llvm.riscv.sf.vc.v.fvv.se.nxv2f16.nxv2f16.nxv2i16.f16.iXLen(iXLen, <2 x half>, <2 x i16>, half %rs1, iXLen) 3438 3439define void @test_sf_vc_fvvf_se_e16m1(<4 x half> %vd, <4 x i16> %vs2, half %rs1, iXLen %vl) { 3440; CHECK-LABEL: test_sf_vc_fvvf_se_e16m1: 3441; CHECK: # %bb.0: # %entry 3442; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 3443; CHECK-NEXT: sf.vc.fvv 1, v8, v9, fa0 3444; CHECK-NEXT: ret 3445entry: 3446 tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv4f16.nxv4i16.f16.iXLen(iXLen 1, <4 x half> %vd, <4 x i16> %vs2, half %rs1, iXLen %vl) 3447 ret void 3448} 3449 3450declare void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv4f16.nxv4i16.f16.iXLen(iXLen, <4 x half>, <4 x i16>, half, iXLen) 3451 3452define <4 x half> @test_sf_vc_fv_fvvf_se_e16m1(<4 x half> %vd, <4 x i16> %vs2, half %rs1, iXLen %vl) { 3453; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e16m1: 3454; CHECK: # %bb.0: # %entry 3455; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma 3456; CHECK-NEXT: sf.vc.v.fvv 1, v8, v9, fa0 3457; CHECK-NEXT: ret 3458entry: 3459 %0 = tail call <4 x half> @llvm.riscv.sf.vc.v.fvv.se.nxv4f16.nxv4f16.nxv4i16.f16.iXLen(iXLen 1, <4 x half> %vd, <4 x i16> %vs2, half %rs1, iXLen %vl) 3460 ret <4 x half> %0 3461} 3462 3463declare <4 x half> @llvm.riscv.sf.vc.v.fvv.se.nxv4f16.nxv4f16.nxv4i16.f16.iXLen(iXLen, <4 x half>, <4 x i16>, half %rs1, iXLen) 3464 3465define void @test_sf_vc_fvvf_se_e16m2(<8 x half> %vd, <8 x i16> %vs2, half %rs1, iXLen %vl) { 3466; CHECK-LABEL: test_sf_vc_fvvf_se_e16m2: 3467; CHECK: # %bb.0: # %entry 3468; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma 3469; CHECK-NEXT: sf.vc.fvv 1, v8, v9, fa0 3470; CHECK-NEXT: ret 3471entry: 3472 tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv8f16.nxv8i16.f16.iXLen(iXLen 1, <8 x half> %vd, <8 x i16> %vs2, half %rs1, iXLen %vl) 3473 ret void 3474} 3475 3476declare void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv8f16.nxv8i16.f16.iXLen(iXLen, <8 x half>, <8 x i16>, half, iXLen) 3477 3478define <8 x half> @test_sf_vc_fv_fvvf_se_e16m2(<8 x half> %vd, <8 x i16> %vs2, half %rs1, iXLen %vl) { 3479; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e16m2: 3480; CHECK: # %bb.0: # %entry 3481; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma 3482; CHECK-NEXT: sf.vc.v.fvv 1, v8, v9, fa0 3483; CHECK-NEXT: ret 3484entry: 3485 %0 = tail call <8 x half> @llvm.riscv.sf.vc.v.fvv.se.nxv8f16.nxv8f16.nxv8i16.f16.iXLen(iXLen 1, <8 x half> %vd, <8 x i16> %vs2, half %rs1, iXLen %vl) 3486 ret <8 x half> %0 3487} 3488 3489declare <8 x half> @llvm.riscv.sf.vc.v.fvv.se.nxv8f16.nxv8f16.nxv8i16.f16.iXLen(iXLen, <8 x half>, <8 x i16>, half %rs1, iXLen) 3490 3491define void @test_sf_vc_fvvf_se_e16m4(<16 x half> %vd, <16 x i16> %vs2, half %rs1, iXLen %vl) { 3492; CHECK-LABEL: test_sf_vc_fvvf_se_e16m4: 3493; CHECK: # %bb.0: # %entry 3494; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma 3495; CHECK-NEXT: sf.vc.fvv 1, v8, v10, fa0 3496; CHECK-NEXT: ret 3497entry: 3498 tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv16f16.nxv16i16.f16.iXLen(iXLen 1, <16 x half> %vd, <16 x i16> %vs2, half %rs1, iXLen %vl) 3499 ret void 3500} 3501 3502declare void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv16f16.nxv16i16.f16.iXLen(iXLen, <16 x half>, <16 x i16>, half, iXLen) 3503 3504define <16 x half> @test_sf_vc_fv_fvvf_se_e16m4(<16 x half> %vd, <16 x i16> %vs2, half %rs1, iXLen %vl) { 3505; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e16m4: 3506; CHECK: # %bb.0: # %entry 3507; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma 3508; CHECK-NEXT: sf.vc.v.fvv 1, v8, v10, fa0 3509; CHECK-NEXT: ret 3510entry: 3511 %0 = tail call <16 x half> @llvm.riscv.sf.vc.v.fvv.se.nxv16f16.nxv16f16.nxv16i16.f16.iXLen(iXLen 1, <16 x half> %vd, <16 x i16> %vs2, half %rs1, iXLen %vl) 3512 ret <16 x half> %0 3513} 3514 3515declare <16 x half> @llvm.riscv.sf.vc.v.fvv.se.nxv16f16.nxv16f16.nxv16i16.f16.iXLen(iXLen, <16 x half>, <16 x i16>, half %rs1, iXLen) 3516 3517define void @test_sf_vc_fvvf_se_e16m8(<32 x half> %vd, <32 x i16> %vs2, half %rs1, iXLen %vl) { 3518; CHECK-LABEL: test_sf_vc_fvvf_se_e16m8: 3519; CHECK: # %bb.0: # %entry 3520; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma 3521; CHECK-NEXT: sf.vc.fvv 1, v8, v12, fa0 3522; CHECK-NEXT: ret 3523entry: 3524 tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv32f16.nxv32i16.f16.iXLen(iXLen 1, <32 x half> %vd, <32 x i16> %vs2, half %rs1, iXLen %vl) 3525 ret void 3526} 3527 3528declare void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv32f16.nxv32i16.f16.iXLen(iXLen, <32 x half>, <32 x i16>, half, iXLen) 3529 3530define <32 x half> @test_sf_vc_fv_fvvf_se_e16m8(<32 x half> %vd, <32 x i16> %vs2, half %rs1, iXLen %vl) { 3531; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e16m8: 3532; CHECK: # %bb.0: # %entry 3533; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma 3534; CHECK-NEXT: sf.vc.v.fvv 1, v8, v12, fa0 3535; CHECK-NEXT: ret 3536entry: 3537 %0 = tail call <32 x half> @llvm.riscv.sf.vc.v.fvv.se.nxv32f16.nxv32f16.nxv32i16.f16.iXLen(iXLen 1, <32 x half> %vd, <32 x i16> %vs2, half %rs1, iXLen %vl) 3538 ret <32 x half> %0 3539} 3540 3541declare <32 x half> @llvm.riscv.sf.vc.v.fvv.se.nxv32f16.nxv32f16.nxv32i16.f16.iXLen(iXLen, <32 x half>, <32 x i16>, half %rs1, iXLen) 3542 3543define void @test_sf_vc_fvvf_se_e32mf2(<1 x float> %vd, <1 x i32> %vs2, float %rs1, iXLen %vl) { 3544; CHECK-LABEL: test_sf_vc_fvvf_se_e32mf2: 3545; CHECK: # %bb.0: # %entry 3546; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma 3547; CHECK-NEXT: sf.vc.fvv 1, v8, v9, fa0 3548; CHECK-NEXT: ret 3549entry: 3550 tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv1f32.nxv1i32.f32.iXLen(iXLen 1, <1 x float> %vd, <1 x i32> %vs2, float %rs1, iXLen %vl) 3551 ret void 3552} 3553 3554declare void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv1f32.nxv1i32.f32.iXLen(iXLen, <1 x float>, <1 x i32>, float, iXLen) 3555 3556define <1 x float> @test_sf_vc_fv_fvvf_se_e32mf2(<1 x float> %vd, <1 x i32> %vs2, float %rs1, iXLen %vl) { 3557; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e32mf2: 3558; CHECK: # %bb.0: # %entry 3559; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma 3560; CHECK-NEXT: sf.vc.v.fvv 1, v8, v9, fa0 3561; CHECK-NEXT: ret 3562entry: 3563 %0 = tail call <1 x float> @llvm.riscv.sf.vc.v.fvv.se.nxv1f32.nxv1f32.nxv1i32.f32.iXLen(iXLen 1, <1 x float> %vd, <1 x i32> %vs2, float %rs1, iXLen %vl) 3564 ret <1 x float> %0 3565} 3566 3567declare <1 x float> @llvm.riscv.sf.vc.v.fvv.se.nxv1f32.nxv1f32.nxv1i32.f32.iXLen(iXLen, <1 x float>, <1 x i32>, float %rs1, iXLen) 3568 3569define void @test_sf_vc_fvvf_se_e32m1(<2 x float> %vd, <2 x i32> %vs2, float %rs1, iXLen %vl) { 3570; CHECK-LABEL: test_sf_vc_fvvf_se_e32m1: 3571; CHECK: # %bb.0: # %entry 3572; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma 3573; CHECK-NEXT: sf.vc.fvv 1, v8, v9, fa0 3574; CHECK-NEXT: ret 3575entry: 3576 tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv2f32.nxv2i32.f32.iXLen(iXLen 1, <2 x float> %vd, <2 x i32> %vs2, float %rs1, iXLen %vl) 3577 ret void 3578} 3579 3580declare void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv2f32.nxv2i32.f32.iXLen(iXLen, <2 x float>, <2 x i32>, float, iXLen) 3581 3582define <2 x float> @test_sf_vc_fv_fvvf_se_e32m1(<2 x float> %vd, <2 x i32> %vs2, float %rs1, iXLen %vl) { 3583; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e32m1: 3584; CHECK: # %bb.0: # %entry 3585; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma 3586; CHECK-NEXT: sf.vc.v.fvv 1, v8, v9, fa0 3587; CHECK-NEXT: ret 3588entry: 3589 %0 = tail call <2 x float> @llvm.riscv.sf.vc.v.fvv.se.nxv2f32.nxv2f32.nxv2i32.f32.iXLen(iXLen 1, <2 x float> %vd, <2 x i32> %vs2, float %rs1, iXLen %vl) 3590 ret <2 x float> %0 3591} 3592 3593declare <2 x float> @llvm.riscv.sf.vc.v.fvv.se.nxv2f32.nxv2f32.nxv2i32.f32.iXLen(iXLen, <2 x float>, <2 x i32>, float %rs1, iXLen) 3594 3595define void @test_sf_vc_fvvf_se_e32m2(<4 x float> %vd, <4 x i32> %vs2, float %rs1, iXLen %vl) { 3596; CHECK-LABEL: test_sf_vc_fvvf_se_e32m2: 3597; CHECK: # %bb.0: # %entry 3598; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 3599; CHECK-NEXT: sf.vc.fvv 1, v8, v9, fa0 3600; CHECK-NEXT: ret 3601entry: 3602 tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv4f32.nxv4i32.f32.iXLen(iXLen 1, <4 x float> %vd, <4 x i32> %vs2, float %rs1, iXLen %vl) 3603 ret void 3604} 3605 3606declare void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv4f32.nxv4i32.f32.iXLen(iXLen, <4 x float>, <4 x i32>, float, iXLen) 3607 3608define <4 x float> @test_sf_vc_fv_fvvf_se_e32m2(<4 x float> %vd, <4 x i32> %vs2, float %rs1, iXLen %vl) { 3609; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e32m2: 3610; CHECK: # %bb.0: # %entry 3611; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma 3612; CHECK-NEXT: sf.vc.v.fvv 1, v8, v9, fa0 3613; CHECK-NEXT: ret 3614entry: 3615 %0 = tail call <4 x float> @llvm.riscv.sf.vc.v.fvv.se.nxv4f32.nxv4f32.nxv4i32.f32.iXLen(iXLen 1, <4 x float> %vd, <4 x i32> %vs2, float %rs1, iXLen %vl) 3616 ret <4 x float> %0 3617} 3618 3619declare <4 x float> @llvm.riscv.sf.vc.v.fvv.se.nxv4f32.nxv4f32.nxv4i32.f32.iXLen(iXLen, <4 x float>, <4 x i32>, float %rs1, iXLen) 3620 3621define void @test_sf_vc_fvvf_se_e32m4(<8 x float> %vd, <8 x i32> %vs2, float %rs1, iXLen %vl) { 3622; CHECK-LABEL: test_sf_vc_fvvf_se_e32m4: 3623; CHECK: # %bb.0: # %entry 3624; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma 3625; CHECK-NEXT: sf.vc.fvv 1, v8, v10, fa0 3626; CHECK-NEXT: ret 3627entry: 3628 tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv8f32.nxv8i32.f32.iXLen(iXLen 1, <8 x float> %vd, <8 x i32> %vs2, float %rs1, iXLen %vl) 3629 ret void 3630} 3631 3632declare void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv8f32.nxv8i32.f32.iXLen(iXLen, <8 x float>, <8 x i32>, float, iXLen) 3633 3634define <8 x float> @test_sf_vc_fv_fvvf_se_e32m4(<8 x float> %vd, <8 x i32> %vs2, float %rs1, iXLen %vl) { 3635; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e32m4: 3636; CHECK: # %bb.0: # %entry 3637; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma 3638; CHECK-NEXT: sf.vc.v.fvv 1, v8, v10, fa0 3639; CHECK-NEXT: ret 3640entry: 3641 %0 = tail call <8 x float> @llvm.riscv.sf.vc.v.fvv.se.nxv8f32.nxv8f32.nxv8i32.f32.iXLen(iXLen 1, <8 x float> %vd, <8 x i32> %vs2, float %rs1, iXLen %vl) 3642 ret <8 x float> %0 3643} 3644 3645declare <8 x float> @llvm.riscv.sf.vc.v.fvv.se.nxv8f32.nxv8f32.nxv8i32.f32.iXLen(iXLen, <8 x float>, <8 x i32>, float %rs1, iXLen) 3646 3647define void @test_sf_vc_fvvf_se_e32m8(<16 x float> %vd, <16 x i32> %vs2, float %rs1, iXLen %vl) { 3648; CHECK-LABEL: test_sf_vc_fvvf_se_e32m8: 3649; CHECK: # %bb.0: # %entry 3650; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma 3651; CHECK-NEXT: sf.vc.fvv 1, v8, v12, fa0 3652; CHECK-NEXT: ret 3653entry: 3654 tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv16f32.nxv16i32.f32.iXLen(iXLen 1, <16 x float> %vd, <16 x i32> %vs2, float %rs1, iXLen %vl) 3655 ret void 3656} 3657 3658declare void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv16f32.nxv16i32.f32.iXLen(iXLen, <16 x float>, <16 x i32>, float, iXLen) 3659 3660define <16 x float> @test_sf_vc_fv_fvvf_se_e32m8(<16 x float> %vd, <16 x i32> %vs2, float %rs1, iXLen %vl) { 3661; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e32m8: 3662; CHECK: # %bb.0: # %entry 3663; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma 3664; CHECK-NEXT: sf.vc.v.fvv 1, v8, v12, fa0 3665; CHECK-NEXT: ret 3666entry: 3667 %0 = tail call <16 x float> @llvm.riscv.sf.vc.v.fvv.se.nxv16f32.nxv16f32.nxv16i32.f32.iXLen(iXLen 1, <16 x float> %vd, <16 x i32> %vs2, float %rs1, iXLen %vl) 3668 ret <16 x float> %0 3669} 3670 3671declare <16 x float> @llvm.riscv.sf.vc.v.fvv.se.nxv16f32.nxv16f32.nxv16i32.f32.iXLen(iXLen, <16 x float>, <16 x i32>, float %rs1, iXLen) 3672