xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll (revision 97982a8c605fac7c86d02e641a6cd7898b3ca343) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64
6
7declare <8 x i7> @llvm.vp.sub.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32)
8
9define <8 x i7> @vsub_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
10; CHECK-LABEL: vsub_vv_v8i7:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
13; CHECK-NEXT:    vsub.vv v8, v8, v9, v0.t
14; CHECK-NEXT:    ret
15  %v = call <8 x i7> @llvm.vp.sub.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
16  ret <8 x i7> %v
17}
18
19declare <2 x i8> @llvm.vp.sub.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32)
20
21define <2 x i8> @vsub_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {
22; CHECK-LABEL: vsub_vv_v2i8:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
25; CHECK-NEXT:    vsub.vv v8, v8, v9, v0.t
26; CHECK-NEXT:    ret
27  %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)
28  ret <2 x i8> %v
29}
30
31define <2 x i8> @vsub_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {
32; CHECK-LABEL: vsub_vv_v2i8_unmasked:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
35; CHECK-NEXT:    vsub.vv v8, v8, v9
36; CHECK-NEXT:    ret
37  %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)
38  ret <2 x i8> %v
39}
40
41define <2 x i8> @vsub_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
42; CHECK-LABEL: vsub_vx_v2i8:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
45; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
46; CHECK-NEXT:    ret
47  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
48  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
49  %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)
50  ret <2 x i8> %v
51}
52
53define <2 x i8> @vsub_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
54; CHECK-LABEL: vsub_vx_v2i8_unmasked:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
57; CHECK-NEXT:    vsub.vx v8, v8, a0
58; CHECK-NEXT:    ret
59  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
60  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
61  %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl)
62  ret <2 x i8> %v
63}
64
65declare <3 x i8> @llvm.vp.sub.v3i8(<3 x i8>, <3 x i8>, <3 x i1>, i32)
66
67define <3 x i8> @vsub_vv_v3i8(<3 x i8> %va, <3 x i8> %b, <3 x i1> %m, i32 zeroext %evl) {
68; CHECK-LABEL: vsub_vv_v3i8:
69; CHECK:       # %bb.0:
70; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
71; CHECK-NEXT:    vsub.vv v8, v8, v9, v0.t
72; CHECK-NEXT:    ret
73  %v = call <3 x i8> @llvm.vp.sub.v3i8(<3 x i8> %va, <3 x i8> %b, <3 x i1> %m, i32 %evl)
74  ret <3 x i8> %v
75}
76
77define <3 x i8> @vsub_vv_v3i8_unmasked(<3 x i8> %va, <3 x i8> %b, i32 zeroext %evl) {
78; CHECK-LABEL: vsub_vv_v3i8_unmasked:
79; CHECK:       # %bb.0:
80; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
81; CHECK-NEXT:    vsub.vv v8, v8, v9
82; CHECK-NEXT:    ret
83  %v = call <3 x i8> @llvm.vp.sub.v3i8(<3 x i8> %va, <3 x i8> %b, <3 x i1> splat (i1 true), i32 %evl)
84  ret <3 x i8> %v
85}
86
87define <3 x i8> @vsub_vx_v3i8(<3 x i8> %va, i8 %b, <3 x i1> %m, i32 zeroext %evl) {
88; CHECK-LABEL: vsub_vx_v3i8:
89; CHECK:       # %bb.0:
90; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
91; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
92; CHECK-NEXT:    ret
93  %elt.head = insertelement <3 x i8> poison, i8 %b, i32 0
94  %vb = shufflevector <3 x i8> %elt.head, <3 x i8> poison, <3 x i32> zeroinitializer
95  %v = call <3 x i8> @llvm.vp.sub.v3i8(<3 x i8> %va, <3 x i8> %vb, <3 x i1> %m, i32 %evl)
96  ret <3 x i8> %v
97}
98
99define <3 x i8> @vsub_vx_v3i8_unmasked(<3 x i8> %va, i8 %b, i32 zeroext %evl) {
100; CHECK-LABEL: vsub_vx_v3i8_unmasked:
101; CHECK:       # %bb.0:
102; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
103; CHECK-NEXT:    vsub.vx v8, v8, a0
104; CHECK-NEXT:    ret
105  %elt.head = insertelement <3 x i8> poison, i8 %b, i32 0
106  %vb = shufflevector <3 x i8> %elt.head, <3 x i8> poison, <3 x i32> zeroinitializer
107  %v = call <3 x i8> @llvm.vp.sub.v3i8(<3 x i8> %va, <3 x i8> %vb, <3 x i1> splat (i1 true), i32 %evl)
108  ret <3 x i8> %v
109}
110
111declare <4 x i8> @llvm.vp.sub.v4i8(<4 x i8>, <4 x i8>, <4 x i1>, i32)
112
113define <4 x i8> @vsub_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {
114; CHECK-LABEL: vsub_vv_v4i8:
115; CHECK:       # %bb.0:
116; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
117; CHECK-NEXT:    vsub.vv v8, v8, v9, v0.t
118; CHECK-NEXT:    ret
119  %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)
120  ret <4 x i8> %v
121}
122
123define <4 x i8> @vsub_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {
124; CHECK-LABEL: vsub_vv_v4i8_unmasked:
125; CHECK:       # %bb.0:
126; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
127; CHECK-NEXT:    vsub.vv v8, v8, v9
128; CHECK-NEXT:    ret
129  %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)
130  ret <4 x i8> %v
131}
132
133define <4 x i8> @vsub_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
134; CHECK-LABEL: vsub_vx_v4i8:
135; CHECK:       # %bb.0:
136; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
137; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
138; CHECK-NEXT:    ret
139  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
140  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
141  %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)
142  ret <4 x i8> %v
143}
144
145define <4 x i8> @vsub_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
146; CHECK-LABEL: vsub_vx_v4i8_unmasked:
147; CHECK:       # %bb.0:
148; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
149; CHECK-NEXT:    vsub.vx v8, v8, a0
150; CHECK-NEXT:    ret
151  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
152  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
153  %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl)
154  ret <4 x i8> %v
155}
156
157declare <8 x i8> @llvm.vp.sub.v8i8(<8 x i8>, <8 x i8>, <8 x i1>, i32)
158
159define <8 x i8> @vsub_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {
160; CHECK-LABEL: vsub_vv_v8i8:
161; CHECK:       # %bb.0:
162; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
163; CHECK-NEXT:    vsub.vv v8, v8, v9, v0.t
164; CHECK-NEXT:    ret
165  %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)
166  ret <8 x i8> %v
167}
168
169define <8 x i8> @vsub_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {
170; CHECK-LABEL: vsub_vv_v8i8_unmasked:
171; CHECK:       # %bb.0:
172; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
173; CHECK-NEXT:    vsub.vv v8, v8, v9
174; CHECK-NEXT:    ret
175  %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)
176  ret <8 x i8> %v
177}
178
179define <8 x i8> @vsub_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {
180; CHECK-LABEL: vsub_vx_v8i8:
181; CHECK:       # %bb.0:
182; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
183; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
184; CHECK-NEXT:    ret
185  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
186  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
187  %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)
188  ret <8 x i8> %v
189}
190
191define <8 x i8> @vsub_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
192; CHECK-LABEL: vsub_vx_v8i8_unmasked:
193; CHECK:       # %bb.0:
194; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
195; CHECK-NEXT:    vsub.vx v8, v8, a0
196; CHECK-NEXT:    ret
197  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
198  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
199  %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl)
200  ret <8 x i8> %v
201}
202
203declare <16 x i8> @llvm.vp.sub.v16i8(<16 x i8>, <16 x i8>, <16 x i1>, i32)
204
205define <16 x i8> @vsub_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {
206; CHECK-LABEL: vsub_vv_v16i8:
207; CHECK:       # %bb.0:
208; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
209; CHECK-NEXT:    vsub.vv v8, v8, v9, v0.t
210; CHECK-NEXT:    ret
211  %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)
212  ret <16 x i8> %v
213}
214
215define <16 x i8> @vsub_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {
216; CHECK-LABEL: vsub_vv_v16i8_unmasked:
217; CHECK:       # %bb.0:
218; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
219; CHECK-NEXT:    vsub.vv v8, v8, v9
220; CHECK-NEXT:    ret
221  %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)
222  ret <16 x i8> %v
223}
224
225define <16 x i8> @vsub_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {
226; CHECK-LABEL: vsub_vx_v16i8:
227; CHECK:       # %bb.0:
228; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
229; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
230; CHECK-NEXT:    ret
231  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
232  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
233  %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)
234  ret <16 x i8> %v
235}
236
237define <16 x i8> @vsub_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {
238; CHECK-LABEL: vsub_vx_v16i8_unmasked:
239; CHECK:       # %bb.0:
240; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
241; CHECK-NEXT:    vsub.vx v8, v8, a0
242; CHECK-NEXT:    ret
243  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
244  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
245  %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl)
246  ret <16 x i8> %v
247}
248
249declare <2 x i16> @llvm.vp.sub.v2i16(<2 x i16>, <2 x i16>, <2 x i1>, i32)
250
251define <2 x i16> @vsub_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {
252; CHECK-LABEL: vsub_vv_v2i16:
253; CHECK:       # %bb.0:
254; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
255; CHECK-NEXT:    vsub.vv v8, v8, v9, v0.t
256; CHECK-NEXT:    ret
257  %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)
258  ret <2 x i16> %v
259}
260
261define <2 x i16> @vsub_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {
262; CHECK-LABEL: vsub_vv_v2i16_unmasked:
263; CHECK:       # %bb.0:
264; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
265; CHECK-NEXT:    vsub.vv v8, v8, v9
266; CHECK-NEXT:    ret
267  %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)
268  ret <2 x i16> %v
269}
270
271define <2 x i16> @vsub_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {
272; CHECK-LABEL: vsub_vx_v2i16:
273; CHECK:       # %bb.0:
274; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
275; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
276; CHECK-NEXT:    ret
277  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
278  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
279  %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)
280  ret <2 x i16> %v
281}
282
283define <2 x i16> @vsub_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {
284; CHECK-LABEL: vsub_vx_v2i16_unmasked:
285; CHECK:       # %bb.0:
286; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
287; CHECK-NEXT:    vsub.vx v8, v8, a0
288; CHECK-NEXT:    ret
289  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
290  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
291  %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl)
292  ret <2 x i16> %v
293}
294
295declare <4 x i16> @llvm.vp.sub.v4i16(<4 x i16>, <4 x i16>, <4 x i1>, i32)
296
297define <4 x i16> @vsub_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {
298; CHECK-LABEL: vsub_vv_v4i16:
299; CHECK:       # %bb.0:
300; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
301; CHECK-NEXT:    vsub.vv v8, v8, v9, v0.t
302; CHECK-NEXT:    ret
303  %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)
304  ret <4 x i16> %v
305}
306
307define <4 x i16> @vsub_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {
308; CHECK-LABEL: vsub_vv_v4i16_unmasked:
309; CHECK:       # %bb.0:
310; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
311; CHECK-NEXT:    vsub.vv v8, v8, v9
312; CHECK-NEXT:    ret
313  %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)
314  ret <4 x i16> %v
315}
316
317define <4 x i16> @vsub_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {
318; CHECK-LABEL: vsub_vx_v4i16:
319; CHECK:       # %bb.0:
320; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
321; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
322; CHECK-NEXT:    ret
323  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
324  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
325  %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)
326  ret <4 x i16> %v
327}
328
329define <4 x i16> @vsub_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {
330; CHECK-LABEL: vsub_vx_v4i16_unmasked:
331; CHECK:       # %bb.0:
332; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
333; CHECK-NEXT:    vsub.vx v8, v8, a0
334; CHECK-NEXT:    ret
335  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
336  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
337  %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl)
338  ret <4 x i16> %v
339}
340
341declare <8 x i16> @llvm.vp.sub.v8i16(<8 x i16>, <8 x i16>, <8 x i1>, i32)
342
343define <8 x i16> @vsub_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {
344; CHECK-LABEL: vsub_vv_v8i16:
345; CHECK:       # %bb.0:
346; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
347; CHECK-NEXT:    vsub.vv v8, v8, v9, v0.t
348; CHECK-NEXT:    ret
349  %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)
350  ret <8 x i16> %v
351}
352
353define <8 x i16> @vsub_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {
354; CHECK-LABEL: vsub_vv_v8i16_unmasked:
355; CHECK:       # %bb.0:
356; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
357; CHECK-NEXT:    vsub.vv v8, v8, v9
358; CHECK-NEXT:    ret
359  %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)
360  ret <8 x i16> %v
361}
362
363define <8 x i16> @vsub_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {
364; CHECK-LABEL: vsub_vx_v8i16:
365; CHECK:       # %bb.0:
366; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
367; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
368; CHECK-NEXT:    ret
369  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
370  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
371  %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)
372  ret <8 x i16> %v
373}
374
375define <8 x i16> @vsub_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {
376; CHECK-LABEL: vsub_vx_v8i16_unmasked:
377; CHECK:       # %bb.0:
378; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
379; CHECK-NEXT:    vsub.vx v8, v8, a0
380; CHECK-NEXT:    ret
381  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
382  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
383  %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl)
384  ret <8 x i16> %v
385}
386
387declare <16 x i16> @llvm.vp.sub.v16i16(<16 x i16>, <16 x i16>, <16 x i1>, i32)
388
389define <16 x i16> @vsub_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {
390; CHECK-LABEL: vsub_vv_v16i16:
391; CHECK:       # %bb.0:
392; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
393; CHECK-NEXT:    vsub.vv v8, v8, v10, v0.t
394; CHECK-NEXT:    ret
395  %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)
396  ret <16 x i16> %v
397}
398
399define <16 x i16> @vsub_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {
400; CHECK-LABEL: vsub_vv_v16i16_unmasked:
401; CHECK:       # %bb.0:
402; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
403; CHECK-NEXT:    vsub.vv v8, v8, v10
404; CHECK-NEXT:    ret
405  %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)
406  ret <16 x i16> %v
407}
408
409define <16 x i16> @vsub_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {
410; CHECK-LABEL: vsub_vx_v16i16:
411; CHECK:       # %bb.0:
412; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
413; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
414; CHECK-NEXT:    ret
415  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
416  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
417  %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)
418  ret <16 x i16> %v
419}
420
421define <16 x i16> @vsub_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {
422; CHECK-LABEL: vsub_vx_v16i16_unmasked:
423; CHECK:       # %bb.0:
424; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
425; CHECK-NEXT:    vsub.vx v8, v8, a0
426; CHECK-NEXT:    ret
427  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
428  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
429  %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl)
430  ret <16 x i16> %v
431}
432
433declare <2 x i32> @llvm.vp.sub.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32)
434
435define <2 x i32> @vsub_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {
436; CHECK-LABEL: vsub_vv_v2i32:
437; CHECK:       # %bb.0:
438; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
439; CHECK-NEXT:    vsub.vv v8, v8, v9, v0.t
440; CHECK-NEXT:    ret
441  %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)
442  ret <2 x i32> %v
443}
444
445define <2 x i32> @vsub_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {
446; CHECK-LABEL: vsub_vv_v2i32_unmasked:
447; CHECK:       # %bb.0:
448; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
449; CHECK-NEXT:    vsub.vv v8, v8, v9
450; CHECK-NEXT:    ret
451  %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)
452  ret <2 x i32> %v
453}
454
455define <2 x i32> @vsub_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {
456; CHECK-LABEL: vsub_vx_v2i32:
457; CHECK:       # %bb.0:
458; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
459; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
460; CHECK-NEXT:    ret
461  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
462  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
463  %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)
464  ret <2 x i32> %v
465}
466
467define <2 x i32> @vsub_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {
468; CHECK-LABEL: vsub_vx_v2i32_unmasked:
469; CHECK:       # %bb.0:
470; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
471; CHECK-NEXT:    vsub.vx v8, v8, a0
472; CHECK-NEXT:    ret
473  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
474  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
475  %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl)
476  ret <2 x i32> %v
477}
478
479declare <4 x i32> @llvm.vp.sub.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
480
481define <4 x i32> @vsub_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {
482; CHECK-LABEL: vsub_vv_v4i32:
483; CHECK:       # %bb.0:
484; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
485; CHECK-NEXT:    vsub.vv v8, v8, v9, v0.t
486; CHECK-NEXT:    ret
487  %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)
488  ret <4 x i32> %v
489}
490
491define <4 x i32> @vsub_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {
492; CHECK-LABEL: vsub_vv_v4i32_unmasked:
493; CHECK:       # %bb.0:
494; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
495; CHECK-NEXT:    vsub.vv v8, v8, v9
496; CHECK-NEXT:    ret
497  %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)
498  ret <4 x i32> %v
499}
500
501define <4 x i32> @vsub_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {
502; CHECK-LABEL: vsub_vx_v4i32:
503; CHECK:       # %bb.0:
504; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
505; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
506; CHECK-NEXT:    ret
507  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
508  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
509  %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)
510  ret <4 x i32> %v
511}
512
513define <4 x i32> @vsub_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {
514; CHECK-LABEL: vsub_vx_v4i32_unmasked:
515; CHECK:       # %bb.0:
516; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
517; CHECK-NEXT:    vsub.vx v8, v8, a0
518; CHECK-NEXT:    ret
519  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
520  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
521  %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl)
522  ret <4 x i32> %v
523}
524
525declare <8 x i32> @llvm.vp.sub.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
526
527define <8 x i32> @vsub_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {
528; CHECK-LABEL: vsub_vv_v8i32:
529; CHECK:       # %bb.0:
530; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
531; CHECK-NEXT:    vsub.vv v8, v8, v10, v0.t
532; CHECK-NEXT:    ret
533  %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)
534  ret <8 x i32> %v
535}
536
537define <8 x i32> @vsub_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {
538; CHECK-LABEL: vsub_vv_v8i32_unmasked:
539; CHECK:       # %bb.0:
540; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
541; CHECK-NEXT:    vsub.vv v8, v8, v10
542; CHECK-NEXT:    ret
543  %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)
544  ret <8 x i32> %v
545}
546
547define <8 x i32> @vsub_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {
548; CHECK-LABEL: vsub_vx_v8i32:
549; CHECK:       # %bb.0:
550; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
551; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
552; CHECK-NEXT:    ret
553  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
554  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
555  %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)
556  ret <8 x i32> %v
557}
558
559define <8 x i32> @vsub_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {
560; CHECK-LABEL: vsub_vx_v8i32_unmasked:
561; CHECK:       # %bb.0:
562; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
563; CHECK-NEXT:    vsub.vx v8, v8, a0
564; CHECK-NEXT:    ret
565  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
566  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
567  %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl)
568  ret <8 x i32> %v
569}
570
571declare <16 x i32> @llvm.vp.sub.v16i32(<16 x i32>, <16 x i32>, <16 x i1>, i32)
572
573define <16 x i32> @vsub_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {
574; CHECK-LABEL: vsub_vv_v16i32:
575; CHECK:       # %bb.0:
576; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
577; CHECK-NEXT:    vsub.vv v8, v8, v12, v0.t
578; CHECK-NEXT:    ret
579  %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)
580  ret <16 x i32> %v
581}
582
583define <16 x i32> @vsub_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {
584; CHECK-LABEL: vsub_vv_v16i32_unmasked:
585; CHECK:       # %bb.0:
586; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
587; CHECK-NEXT:    vsub.vv v8, v8, v12
588; CHECK-NEXT:    ret
589  %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)
590  ret <16 x i32> %v
591}
592
593define <16 x i32> @vsub_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {
594; CHECK-LABEL: vsub_vx_v16i32:
595; CHECK:       # %bb.0:
596; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
597; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
598; CHECK-NEXT:    ret
599  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
600  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
601  %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)
602  ret <16 x i32> %v
603}
604
605define <16 x i32> @vsub_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {
606; CHECK-LABEL: vsub_vx_v16i32_unmasked:
607; CHECK:       # %bb.0:
608; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
609; CHECK-NEXT:    vsub.vx v8, v8, a0
610; CHECK-NEXT:    ret
611  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
612  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
613  %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl)
614  ret <16 x i32> %v
615}
616
617declare <2 x i64> @llvm.vp.sub.v2i64(<2 x i64>, <2 x i64>, <2 x i1>, i32)
618
619define <2 x i64> @vsub_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {
620; CHECK-LABEL: vsub_vv_v2i64:
621; CHECK:       # %bb.0:
622; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
623; CHECK-NEXT:    vsub.vv v8, v8, v9, v0.t
624; CHECK-NEXT:    ret
625  %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)
626  ret <2 x i64> %v
627}
628
629define <2 x i64> @vsub_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {
630; CHECK-LABEL: vsub_vv_v2i64_unmasked:
631; CHECK:       # %bb.0:
632; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
633; CHECK-NEXT:    vsub.vv v8, v8, v9
634; CHECK-NEXT:    ret
635  %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)
636  ret <2 x i64> %v
637}
638
639define <2 x i64> @vsub_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
640; RV32-LABEL: vsub_vx_v2i64:
641; RV32:       # %bb.0:
642; RV32-NEXT:    addi sp, sp, -16
643; RV32-NEXT:    .cfi_def_cfa_offset 16
644; RV32-NEXT:    sw a0, 8(sp)
645; RV32-NEXT:    sw a1, 12(sp)
646; RV32-NEXT:    addi a0, sp, 8
647; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
648; RV32-NEXT:    vlse64.v v9, (a0), zero
649; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
650; RV32-NEXT:    vsub.vv v8, v8, v9, v0.t
651; RV32-NEXT:    addi sp, sp, 16
652; RV32-NEXT:    .cfi_def_cfa_offset 0
653; RV32-NEXT:    ret
654;
655; RV64-LABEL: vsub_vx_v2i64:
656; RV64:       # %bb.0:
657; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
658; RV64-NEXT:    vsub.vx v8, v8, a0, v0.t
659; RV64-NEXT:    ret
660  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
661  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
662  %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
663  ret <2 x i64> %v
664}
665
666define <2 x i64> @vsub_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
667; RV32-LABEL: vsub_vx_v2i64_unmasked:
668; RV32:       # %bb.0:
669; RV32-NEXT:    addi sp, sp, -16
670; RV32-NEXT:    .cfi_def_cfa_offset 16
671; RV32-NEXT:    sw a0, 8(sp)
672; RV32-NEXT:    sw a1, 12(sp)
673; RV32-NEXT:    addi a0, sp, 8
674; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
675; RV32-NEXT:    vlse64.v v9, (a0), zero
676; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
677; RV32-NEXT:    vsub.vv v8, v8, v9
678; RV32-NEXT:    addi sp, sp, 16
679; RV32-NEXT:    .cfi_def_cfa_offset 0
680; RV32-NEXT:    ret
681;
682; RV64-LABEL: vsub_vx_v2i64_unmasked:
683; RV64:       # %bb.0:
684; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
685; RV64-NEXT:    vsub.vx v8, v8, a0
686; RV64-NEXT:    ret
687  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
688  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
689  %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl)
690  ret <2 x i64> %v
691}
692
693declare <4 x i64> @llvm.vp.sub.v4i64(<4 x i64>, <4 x i64>, <4 x i1>, i32)
694
695define <4 x i64> @vsub_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {
696; CHECK-LABEL: vsub_vv_v4i64:
697; CHECK:       # %bb.0:
698; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
699; CHECK-NEXT:    vsub.vv v8, v8, v10, v0.t
700; CHECK-NEXT:    ret
701  %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)
702  ret <4 x i64> %v
703}
704
705define <4 x i64> @vsub_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {
706; CHECK-LABEL: vsub_vv_v4i64_unmasked:
707; CHECK:       # %bb.0:
708; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
709; CHECK-NEXT:    vsub.vv v8, v8, v10
710; CHECK-NEXT:    ret
711  %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)
712  ret <4 x i64> %v
713}
714
715define <4 x i64> @vsub_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
716; RV32-LABEL: vsub_vx_v4i64:
717; RV32:       # %bb.0:
718; RV32-NEXT:    addi sp, sp, -16
719; RV32-NEXT:    .cfi_def_cfa_offset 16
720; RV32-NEXT:    sw a0, 8(sp)
721; RV32-NEXT:    sw a1, 12(sp)
722; RV32-NEXT:    addi a0, sp, 8
723; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
724; RV32-NEXT:    vlse64.v v10, (a0), zero
725; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
726; RV32-NEXT:    vsub.vv v8, v8, v10, v0.t
727; RV32-NEXT:    addi sp, sp, 16
728; RV32-NEXT:    .cfi_def_cfa_offset 0
729; RV32-NEXT:    ret
730;
731; RV64-LABEL: vsub_vx_v4i64:
732; RV64:       # %bb.0:
733; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
734; RV64-NEXT:    vsub.vx v8, v8, a0, v0.t
735; RV64-NEXT:    ret
736  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
737  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
738  %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
739  ret <4 x i64> %v
740}
741
742define <4 x i64> @vsub_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
743; RV32-LABEL: vsub_vx_v4i64_unmasked:
744; RV32:       # %bb.0:
745; RV32-NEXT:    addi sp, sp, -16
746; RV32-NEXT:    .cfi_def_cfa_offset 16
747; RV32-NEXT:    sw a0, 8(sp)
748; RV32-NEXT:    sw a1, 12(sp)
749; RV32-NEXT:    addi a0, sp, 8
750; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
751; RV32-NEXT:    vlse64.v v10, (a0), zero
752; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
753; RV32-NEXT:    vsub.vv v8, v8, v10
754; RV32-NEXT:    addi sp, sp, 16
755; RV32-NEXT:    .cfi_def_cfa_offset 0
756; RV32-NEXT:    ret
757;
758; RV64-LABEL: vsub_vx_v4i64_unmasked:
759; RV64:       # %bb.0:
760; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
761; RV64-NEXT:    vsub.vx v8, v8, a0
762; RV64-NEXT:    ret
763  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
764  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
765  %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl)
766  ret <4 x i64> %v
767}
768
769declare <8 x i64> @llvm.vp.sub.v8i64(<8 x i64>, <8 x i64>, <8 x i1>, i32)
770
771define <8 x i64> @vsub_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {
772; CHECK-LABEL: vsub_vv_v8i64:
773; CHECK:       # %bb.0:
774; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
775; CHECK-NEXT:    vsub.vv v8, v8, v12, v0.t
776; CHECK-NEXT:    ret
777  %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)
778  ret <8 x i64> %v
779}
780
781define <8 x i64> @vsub_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {
782; CHECK-LABEL: vsub_vv_v8i64_unmasked:
783; CHECK:       # %bb.0:
784; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
785; CHECK-NEXT:    vsub.vv v8, v8, v12
786; CHECK-NEXT:    ret
787  %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)
788  ret <8 x i64> %v
789}
790
791define <8 x i64> @vsub_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
792; RV32-LABEL: vsub_vx_v8i64:
793; RV32:       # %bb.0:
794; RV32-NEXT:    addi sp, sp, -16
795; RV32-NEXT:    .cfi_def_cfa_offset 16
796; RV32-NEXT:    sw a0, 8(sp)
797; RV32-NEXT:    sw a1, 12(sp)
798; RV32-NEXT:    addi a0, sp, 8
799; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
800; RV32-NEXT:    vlse64.v v12, (a0), zero
801; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
802; RV32-NEXT:    vsub.vv v8, v8, v12, v0.t
803; RV32-NEXT:    addi sp, sp, 16
804; RV32-NEXT:    .cfi_def_cfa_offset 0
805; RV32-NEXT:    ret
806;
807; RV64-LABEL: vsub_vx_v8i64:
808; RV64:       # %bb.0:
809; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
810; RV64-NEXT:    vsub.vx v8, v8, a0, v0.t
811; RV64-NEXT:    ret
812  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
813  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
814  %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
815  ret <8 x i64> %v
816}
817
818define <8 x i64> @vsub_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
819; RV32-LABEL: vsub_vx_v8i64_unmasked:
820; RV32:       # %bb.0:
821; RV32-NEXT:    addi sp, sp, -16
822; RV32-NEXT:    .cfi_def_cfa_offset 16
823; RV32-NEXT:    sw a0, 8(sp)
824; RV32-NEXT:    sw a1, 12(sp)
825; RV32-NEXT:    addi a0, sp, 8
826; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
827; RV32-NEXT:    vlse64.v v12, (a0), zero
828; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
829; RV32-NEXT:    vsub.vv v8, v8, v12
830; RV32-NEXT:    addi sp, sp, 16
831; RV32-NEXT:    .cfi_def_cfa_offset 0
832; RV32-NEXT:    ret
833;
834; RV64-LABEL: vsub_vx_v8i64_unmasked:
835; RV64:       # %bb.0:
836; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
837; RV64-NEXT:    vsub.vx v8, v8, a0
838; RV64-NEXT:    ret
839  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
840  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
841  %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl)
842  ret <8 x i64> %v
843}
844
845declare <16 x i64> @llvm.vp.sub.v16i64(<16 x i64>, <16 x i64>, <16 x i1>, i32)
846
847define <16 x i64> @vsub_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {
848; CHECK-LABEL: vsub_vv_v16i64:
849; CHECK:       # %bb.0:
850; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
851; CHECK-NEXT:    vsub.vv v8, v8, v16, v0.t
852; CHECK-NEXT:    ret
853  %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)
854  ret <16 x i64> %v
855}
856
857define <16 x i64> @vsub_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {
858; CHECK-LABEL: vsub_vv_v16i64_unmasked:
859; CHECK:       # %bb.0:
860; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
861; CHECK-NEXT:    vsub.vv v8, v8, v16
862; CHECK-NEXT:    ret
863  %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)
864  ret <16 x i64> %v
865}
866
867define <16 x i64> @vsub_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
868; RV32-LABEL: vsub_vx_v16i64:
869; RV32:       # %bb.0:
870; RV32-NEXT:    addi sp, sp, -16
871; RV32-NEXT:    .cfi_def_cfa_offset 16
872; RV32-NEXT:    sw a0, 8(sp)
873; RV32-NEXT:    sw a1, 12(sp)
874; RV32-NEXT:    addi a0, sp, 8
875; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
876; RV32-NEXT:    vlse64.v v16, (a0), zero
877; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
878; RV32-NEXT:    vsub.vv v8, v8, v16, v0.t
879; RV32-NEXT:    addi sp, sp, 16
880; RV32-NEXT:    .cfi_def_cfa_offset 0
881; RV32-NEXT:    ret
882;
883; RV64-LABEL: vsub_vx_v16i64:
884; RV64:       # %bb.0:
885; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
886; RV64-NEXT:    vsub.vx v8, v8, a0, v0.t
887; RV64-NEXT:    ret
888  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
889  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
890  %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
891  ret <16 x i64> %v
892}
893
894define <16 x i64> @vsub_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
895; RV32-LABEL: vsub_vx_v16i64_unmasked:
896; RV32:       # %bb.0:
897; RV32-NEXT:    addi sp, sp, -16
898; RV32-NEXT:    .cfi_def_cfa_offset 16
899; RV32-NEXT:    sw a0, 8(sp)
900; RV32-NEXT:    sw a1, 12(sp)
901; RV32-NEXT:    addi a0, sp, 8
902; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
903; RV32-NEXT:    vlse64.v v16, (a0), zero
904; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
905; RV32-NEXT:    vsub.vv v8, v8, v16
906; RV32-NEXT:    addi sp, sp, 16
907; RV32-NEXT:    .cfi_def_cfa_offset 0
908; RV32-NEXT:    ret
909;
910; RV64-LABEL: vsub_vx_v16i64_unmasked:
911; RV64:       # %bb.0:
912; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
913; RV64-NEXT:    vsub.vx v8, v8, a0
914; RV64-NEXT:    ret
915  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
916  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
917  %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl)
918  ret <16 x i64> %v
919}
920