xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64
6
7declare <8 x i7> @llvm.vp.usub.sat.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32)
8
9define <8 x i7> @vssubu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
10; CHECK-LABEL: vssubu_vv_v8i7:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    li a1, 127
13; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
14; CHECK-NEXT:    vand.vx v9, v9, a1
15; CHECK-NEXT:    vand.vx v8, v8, a1
16; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
17; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t
18; CHECK-NEXT:    ret
19  %v = call <8 x i7> @llvm.vp.usub.sat.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
20  ret <8 x i7> %v
21}
22
23declare <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32)
24
25define <2 x i8> @vssubu_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {
26; CHECK-LABEL: vssubu_vv_v2i8:
27; CHECK:       # %bb.0:
28; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
29; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t
30; CHECK-NEXT:    ret
31  %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)
32  ret <2 x i8> %v
33}
34
35define <2 x i8> @vssubu_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {
36; CHECK-LABEL: vssubu_vv_v2i8_unmasked:
37; CHECK:       # %bb.0:
38; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
39; CHECK-NEXT:    vssubu.vv v8, v8, v9
40; CHECK-NEXT:    ret
41  %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)
42  ret <2 x i8> %v
43}
44
45define <2 x i8> @vssubu_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
46; CHECK-LABEL: vssubu_vx_v2i8:
47; CHECK:       # %bb.0:
48; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
49; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t
50; CHECK-NEXT:    ret
51  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
52  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
53  %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)
54  ret <2 x i8> %v
55}
56
57define <2 x i8> @vssubu_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
58; CHECK-LABEL: vssubu_vx_v2i8_unmasked:
59; CHECK:       # %bb.0:
60; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
61; CHECK-NEXT:    vssubu.vx v8, v8, a0
62; CHECK-NEXT:    ret
63  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
64  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
65  %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl)
66  ret <2 x i8> %v
67}
68
69define <2 x i8> @vssubu_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
70; CHECK-LABEL: vssubu_vi_v2i8:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    li a1, -1
73; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
74; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t
75; CHECK-NEXT:    ret
76  %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl)
77  ret <2 x i8> %v
78}
79
80define <2 x i8> @vssubu_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
81; CHECK-LABEL: vssubu_vi_v2i8_unmasked:
82; CHECK:       # %bb.0:
83; CHECK-NEXT:    li a1, -1
84; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
85; CHECK-NEXT:    vssubu.vx v8, v8, a1
86; CHECK-NEXT:    ret
87  %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl)
88  ret <2 x i8> %v
89}
90
91declare <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8>, <4 x i8>, <4 x i1>, i32)
92
93define <4 x i8> @vssubu_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {
94; CHECK-LABEL: vssubu_vv_v4i8:
95; CHECK:       # %bb.0:
96; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
97; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t
98; CHECK-NEXT:    ret
99  %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)
100  ret <4 x i8> %v
101}
102
103define <4 x i8> @vssubu_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {
104; CHECK-LABEL: vssubu_vv_v4i8_unmasked:
105; CHECK:       # %bb.0:
106; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
107; CHECK-NEXT:    vssubu.vv v8, v8, v9
108; CHECK-NEXT:    ret
109  %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)
110  ret <4 x i8> %v
111}
112
113define <4 x i8> @vssubu_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
114; CHECK-LABEL: vssubu_vx_v4i8:
115; CHECK:       # %bb.0:
116; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
117; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t
118; CHECK-NEXT:    ret
119  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
120  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
121  %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)
122  ret <4 x i8> %v
123}
124
125define <4 x i8> @vssubu_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
126; CHECK-LABEL: vssubu_vx_v4i8_commute:
127; CHECK:       # %bb.0:
128; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
129; CHECK-NEXT:    vmv.v.x v9, a0
130; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
131; CHECK-NEXT:    vssubu.vv v8, v9, v8, v0.t
132; CHECK-NEXT:    ret
133  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
134  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
135  %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl)
136  ret <4 x i8> %v
137}
138
139define <4 x i8> @vssubu_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
140; CHECK-LABEL: vssubu_vx_v4i8_unmasked:
141; CHECK:       # %bb.0:
142; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
143; CHECK-NEXT:    vssubu.vx v8, v8, a0
144; CHECK-NEXT:    ret
145  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
146  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
147  %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl)
148  ret <4 x i8> %v
149}
150
151define <4 x i8> @vssubu_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
152; CHECK-LABEL: vssubu_vi_v4i8:
153; CHECK:       # %bb.0:
154; CHECK-NEXT:    li a1, -1
155; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
156; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t
157; CHECK-NEXT:    ret
158  %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl)
159  ret <4 x i8> %v
160}
161
162define <4 x i8> @vssubu_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
163; CHECK-LABEL: vssubu_vi_v4i8_unmasked:
164; CHECK:       # %bb.0:
165; CHECK-NEXT:    li a1, -1
166; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
167; CHECK-NEXT:    vssubu.vx v8, v8, a1
168; CHECK-NEXT:    ret
169  %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl)
170  ret <4 x i8> %v
171}
172
173declare <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8>, <5 x i8>, <5 x i1>, i32)
174
175define <5 x i8> @vssubu_vv_v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 zeroext %evl) {
176; CHECK-LABEL: vssubu_vv_v5i8:
177; CHECK:       # %bb.0:
178; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
179; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t
180; CHECK-NEXT:    ret
181  %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl)
182  ret <5 x i8> %v
183}
184
185define <5 x i8> @vssubu_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %evl) {
186; CHECK-LABEL: vssubu_vv_v5i8_unmasked:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
189; CHECK-NEXT:    vssubu.vv v8, v8, v9
190; CHECK-NEXT:    ret
191  %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl)
192  ret <5 x i8> %v
193}
194
195define <5 x i8> @vssubu_vx_v5i8(<5 x i8> %va, i8 %b, <5 x i1> %m, i32 zeroext %evl) {
196; CHECK-LABEL: vssubu_vx_v5i8:
197; CHECK:       # %bb.0:
198; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
199; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t
200; CHECK-NEXT:    ret
201  %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
202  %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer
203  %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl)
204  ret <5 x i8> %v
205}
206
207define <5 x i8> @vssubu_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) {
208; CHECK-LABEL: vssubu_vx_v5i8_unmasked:
209; CHECK:       # %bb.0:
210; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
211; CHECK-NEXT:    vssubu.vx v8, v8, a0
212; CHECK-NEXT:    ret
213  %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
214  %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer
215  %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl)
216  ret <5 x i8> %v
217}
218
219define <5 x i8> @vssubu_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) {
220; CHECK-LABEL: vssubu_vi_v5i8:
221; CHECK:       # %bb.0:
222; CHECK-NEXT:    li a1, -1
223; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
224; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t
225; CHECK-NEXT:    ret
226  %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> %m, i32 %evl)
227  ret <5 x i8> %v
228}
229
230define <5 x i8> @vssubu_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) {
231; CHECK-LABEL: vssubu_vi_v5i8_unmasked:
232; CHECK:       # %bb.0:
233; CHECK-NEXT:    li a1, -1
234; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
235; CHECK-NEXT:    vssubu.vx v8, v8, a1
236; CHECK-NEXT:    ret
237  %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> splat (i1 true), i32 %evl)
238  ret <5 x i8> %v
239}
240
241declare <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8>, <8 x i8>, <8 x i1>, i32)
242
243define <8 x i8> @vssubu_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {
244; CHECK-LABEL: vssubu_vv_v8i8:
245; CHECK:       # %bb.0:
246; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
247; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t
248; CHECK-NEXT:    ret
249  %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)
250  ret <8 x i8> %v
251}
252
253define <8 x i8> @vssubu_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {
254; CHECK-LABEL: vssubu_vv_v8i8_unmasked:
255; CHECK:       # %bb.0:
256; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
257; CHECK-NEXT:    vssubu.vv v8, v8, v9
258; CHECK-NEXT:    ret
259  %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)
260  ret <8 x i8> %v
261}
262
263define <8 x i8> @vssubu_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {
264; CHECK-LABEL: vssubu_vx_v8i8:
265; CHECK:       # %bb.0:
266; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
267; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t
268; CHECK-NEXT:    ret
269  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
270  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
271  %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)
272  ret <8 x i8> %v
273}
274
275define <8 x i8> @vssubu_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
276; CHECK-LABEL: vssubu_vx_v8i8_unmasked:
277; CHECK:       # %bb.0:
278; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
279; CHECK-NEXT:    vssubu.vx v8, v8, a0
280; CHECK-NEXT:    ret
281  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
282  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
283  %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl)
284  ret <8 x i8> %v
285}
286
287define <8 x i8> @vssubu_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
288; CHECK-LABEL: vssubu_vi_v8i8:
289; CHECK:       # %bb.0:
290; CHECK-NEXT:    li a1, -1
291; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
292; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t
293; CHECK-NEXT:    ret
294  %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl)
295  ret <8 x i8> %v
296}
297
298define <8 x i8> @vssubu_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
299; CHECK-LABEL: vssubu_vi_v8i8_unmasked:
300; CHECK:       # %bb.0:
301; CHECK-NEXT:    li a1, -1
302; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
303; CHECK-NEXT:    vssubu.vx v8, v8, a1
304; CHECK-NEXT:    ret
305  %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl)
306  ret <8 x i8> %v
307}
308
309declare <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8>, <16 x i8>, <16 x i1>, i32)
310
311define <16 x i8> @vssubu_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {
312; CHECK-LABEL: vssubu_vv_v16i8:
313; CHECK:       # %bb.0:
314; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
315; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t
316; CHECK-NEXT:    ret
317  %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)
318  ret <16 x i8> %v
319}
320
321define <16 x i8> @vssubu_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {
322; CHECK-LABEL: vssubu_vv_v16i8_unmasked:
323; CHECK:       # %bb.0:
324; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
325; CHECK-NEXT:    vssubu.vv v8, v8, v9
326; CHECK-NEXT:    ret
327  %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)
328  ret <16 x i8> %v
329}
330
331define <16 x i8> @vssubu_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {
332; CHECK-LABEL: vssubu_vx_v16i8:
333; CHECK:       # %bb.0:
334; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
335; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t
336; CHECK-NEXT:    ret
337  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
338  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
339  %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)
340  ret <16 x i8> %v
341}
342
343define <16 x i8> @vssubu_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {
344; CHECK-LABEL: vssubu_vx_v16i8_unmasked:
345; CHECK:       # %bb.0:
346; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
347; CHECK-NEXT:    vssubu.vx v8, v8, a0
348; CHECK-NEXT:    ret
349  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
350  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
351  %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl)
352  ret <16 x i8> %v
353}
354
355define <16 x i8> @vssubu_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
356; CHECK-LABEL: vssubu_vi_v16i8:
357; CHECK:       # %bb.0:
358; CHECK-NEXT:    li a1, -1
359; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
360; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t
361; CHECK-NEXT:    ret
362  %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl)
363  ret <16 x i8> %v
364}
365
366define <16 x i8> @vssubu_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
367; CHECK-LABEL: vssubu_vi_v16i8_unmasked:
368; CHECK:       # %bb.0:
369; CHECK-NEXT:    li a1, -1
370; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
371; CHECK-NEXT:    vssubu.vx v8, v8, a1
372; CHECK-NEXT:    ret
373  %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl)
374  ret <16 x i8> %v
375}
376
377declare <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8>, <256 x i8>, <256 x i1>, i32)
378
379define <256 x i8> @vssubu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %evl) {
380; CHECK-LABEL: vssubu_vi_v258i8:
381; CHECK:       # %bb.0:
382; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
383; CHECK-NEXT:    vmv1r.v v24, v0
384; CHECK-NEXT:    li a2, 128
385; CHECK-NEXT:    addi a3, a1, -128
386; CHECK-NEXT:    vsetvli zero, a2, e8, m8, ta, ma
387; CHECK-NEXT:    vlm.v v0, (a0)
388; CHECK-NEXT:    sltu a0, a1, a3
389; CHECK-NEXT:    addi a0, a0, -1
390; CHECK-NEXT:    and a3, a0, a3
391; CHECK-NEXT:    li a0, -1
392; CHECK-NEXT:    vsetvli zero, a3, e8, m8, ta, ma
393; CHECK-NEXT:    vssubu.vx v16, v16, a0, v0.t
394; CHECK-NEXT:    bltu a1, a2, .LBB32_2
395; CHECK-NEXT:  # %bb.1:
396; CHECK-NEXT:    li a1, 128
397; CHECK-NEXT:  .LBB32_2:
398; CHECK-NEXT:    vmv1r.v v0, v24
399; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
400; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t
401; CHECK-NEXT:    ret
402  %v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 %evl)
403  ret <256 x i8> %v
404}
405
406define <256 x i8> @vssubu_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) {
407; CHECK-LABEL: vssubu_vi_v258i8_unmasked:
408; CHECK:       # %bb.0:
409; CHECK-NEXT:    li a2, 128
410; CHECK-NEXT:    mv a1, a0
411; CHECK-NEXT:    bltu a0, a2, .LBB33_2
412; CHECK-NEXT:  # %bb.1:
413; CHECK-NEXT:    li a1, 128
414; CHECK-NEXT:  .LBB33_2:
415; CHECK-NEXT:    li a2, -1
416; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
417; CHECK-NEXT:    vssubu.vx v8, v8, a2
418; CHECK-NEXT:    addi a1, a0, -128
419; CHECK-NEXT:    sltu a0, a0, a1
420; CHECK-NEXT:    addi a0, a0, -1
421; CHECK-NEXT:    and a0, a0, a1
422; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
423; CHECK-NEXT:    vssubu.vx v16, v16, a2
424; CHECK-NEXT:    ret
425  %v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> splat (i1 true), i32 %evl)
426  ret <256 x i8> %v
427}
428
429; Test splitting when the %evl is a known constant.
430
431define <256 x i8> @vssubu_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
432; CHECK-LABEL: vssubu_vi_v258i8_evl129:
433; CHECK:       # %bb.0:
434; CHECK-NEXT:    li a1, 128
435; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
436; CHECK-NEXT:    vlm.v v24, (a0)
437; CHECK-NEXT:    li a0, -1
438; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t
439; CHECK-NEXT:    vmv1r.v v0, v24
440; CHECK-NEXT:    vsetivli zero, 1, e8, m8, ta, ma
441; CHECK-NEXT:    vssubu.vx v16, v16, a0, v0.t
442; CHECK-NEXT:    ret
443  %v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 129)
444  ret <256 x i8> %v
445}
446
447; FIXME: The upper half is doing nothing.
448
449define <256 x i8> @vssubu_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
450; CHECK-LABEL: vssubu_vi_v258i8_evl128:
451; CHECK:       # %bb.0:
452; CHECK-NEXT:    li a1, 128
453; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
454; CHECK-NEXT:    vlm.v v24, (a0)
455; CHECK-NEXT:    li a0, -1
456; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t
457; CHECK-NEXT:    vmv1r.v v0, v24
458; CHECK-NEXT:    vsetivli zero, 0, e8, m8, ta, ma
459; CHECK-NEXT:    vssubu.vx v16, v16, a0, v0.t
460; CHECK-NEXT:    ret
461  %v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)
462  ret <256 x i8> %v
463}
464
465declare <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16>, <2 x i16>, <2 x i1>, i32)
466
467define <2 x i16> @vssubu_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {
468; CHECK-LABEL: vssubu_vv_v2i16:
469; CHECK:       # %bb.0:
470; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
471; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t
472; CHECK-NEXT:    ret
473  %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)
474  ret <2 x i16> %v
475}
476
477define <2 x i16> @vssubu_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {
478; CHECK-LABEL: vssubu_vv_v2i16_unmasked:
479; CHECK:       # %bb.0:
480; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
481; CHECK-NEXT:    vssubu.vv v8, v8, v9
482; CHECK-NEXT:    ret
483  %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)
484  ret <2 x i16> %v
485}
486
487define <2 x i16> @vssubu_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {
488; CHECK-LABEL: vssubu_vx_v2i16:
489; CHECK:       # %bb.0:
490; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
491; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t
492; CHECK-NEXT:    ret
493  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
494  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
495  %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)
496  ret <2 x i16> %v
497}
498
499define <2 x i16> @vssubu_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {
500; CHECK-LABEL: vssubu_vx_v2i16_unmasked:
501; CHECK:       # %bb.0:
502; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
503; CHECK-NEXT:    vssubu.vx v8, v8, a0
504; CHECK-NEXT:    ret
505  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
506  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
507  %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl)
508  ret <2 x i16> %v
509}
510
511define <2 x i16> @vssubu_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
512; CHECK-LABEL: vssubu_vi_v2i16:
513; CHECK:       # %bb.0:
514; CHECK-NEXT:    li a1, -1
515; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
516; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t
517; CHECK-NEXT:    ret
518  %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl)
519  ret <2 x i16> %v
520}
521
522define <2 x i16> @vssubu_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
523; CHECK-LABEL: vssubu_vi_v2i16_unmasked:
524; CHECK:       # %bb.0:
525; CHECK-NEXT:    li a1, -1
526; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
527; CHECK-NEXT:    vssubu.vx v8, v8, a1
528; CHECK-NEXT:    ret
529  %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl)
530  ret <2 x i16> %v
531}
532
533declare <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16>, <4 x i16>, <4 x i1>, i32)
534
535define <4 x i16> @vssubu_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {
536; CHECK-LABEL: vssubu_vv_v4i16:
537; CHECK:       # %bb.0:
538; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
539; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t
540; CHECK-NEXT:    ret
541  %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)
542  ret <4 x i16> %v
543}
544
545define <4 x i16> @vssubu_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {
546; CHECK-LABEL: vssubu_vv_v4i16_unmasked:
547; CHECK:       # %bb.0:
548; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
549; CHECK-NEXT:    vssubu.vv v8, v8, v9
550; CHECK-NEXT:    ret
551  %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)
552  ret <4 x i16> %v
553}
554
555define <4 x i16> @vssubu_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {
556; CHECK-LABEL: vssubu_vx_v4i16:
557; CHECK:       # %bb.0:
558; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
559; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t
560; CHECK-NEXT:    ret
561  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
562  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
563  %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)
564  ret <4 x i16> %v
565}
566
567define <4 x i16> @vssubu_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {
568; CHECK-LABEL: vssubu_vx_v4i16_unmasked:
569; CHECK:       # %bb.0:
570; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
571; CHECK-NEXT:    vssubu.vx v8, v8, a0
572; CHECK-NEXT:    ret
573  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
574  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
575  %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl)
576  ret <4 x i16> %v
577}
578
579define <4 x i16> @vssubu_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
580; CHECK-LABEL: vssubu_vi_v4i16:
581; CHECK:       # %bb.0:
582; CHECK-NEXT:    li a1, -1
583; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
584; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t
585; CHECK-NEXT:    ret
586  %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl)
587  ret <4 x i16> %v
588}
589
590define <4 x i16> @vssubu_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
591; CHECK-LABEL: vssubu_vi_v4i16_unmasked:
592; CHECK:       # %bb.0:
593; CHECK-NEXT:    li a1, -1
594; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
595; CHECK-NEXT:    vssubu.vx v8, v8, a1
596; CHECK-NEXT:    ret
597  %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl)
598  ret <4 x i16> %v
599}
600
601declare <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16>, <8 x i16>, <8 x i1>, i32)
602
603define <8 x i16> @vssubu_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {
604; CHECK-LABEL: vssubu_vv_v8i16:
605; CHECK:       # %bb.0:
606; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
607; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t
608; CHECK-NEXT:    ret
609  %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)
610  ret <8 x i16> %v
611}
612
613define <8 x i16> @vssubu_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {
614; CHECK-LABEL: vssubu_vv_v8i16_unmasked:
615; CHECK:       # %bb.0:
616; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
617; CHECK-NEXT:    vssubu.vv v8, v8, v9
618; CHECK-NEXT:    ret
619  %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)
620  ret <8 x i16> %v
621}
622
623define <8 x i16> @vssubu_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {
624; CHECK-LABEL: vssubu_vx_v8i16:
625; CHECK:       # %bb.0:
626; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
627; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t
628; CHECK-NEXT:    ret
629  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
630  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
631  %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)
632  ret <8 x i16> %v
633}
634
635define <8 x i16> @vssubu_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {
636; CHECK-LABEL: vssubu_vx_v8i16_unmasked:
637; CHECK:       # %bb.0:
638; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
639; CHECK-NEXT:    vssubu.vx v8, v8, a0
640; CHECK-NEXT:    ret
641  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
642  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
643  %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl)
644  ret <8 x i16> %v
645}
646
647define <8 x i16> @vssubu_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
648; CHECK-LABEL: vssubu_vi_v8i16:
649; CHECK:       # %bb.0:
650; CHECK-NEXT:    li a1, -1
651; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
652; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t
653; CHECK-NEXT:    ret
654  %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl)
655  ret <8 x i16> %v
656}
657
658define <8 x i16> @vssubu_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
659; CHECK-LABEL: vssubu_vi_v8i16_unmasked:
660; CHECK:       # %bb.0:
661; CHECK-NEXT:    li a1, -1
662; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
663; CHECK-NEXT:    vssubu.vx v8, v8, a1
664; CHECK-NEXT:    ret
665  %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl)
666  ret <8 x i16> %v
667}
668
669declare <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16>, <16 x i16>, <16 x i1>, i32)
670
671define <16 x i16> @vssubu_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {
672; CHECK-LABEL: vssubu_vv_v16i16:
673; CHECK:       # %bb.0:
674; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
675; CHECK-NEXT:    vssubu.vv v8, v8, v10, v0.t
676; CHECK-NEXT:    ret
677  %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)
678  ret <16 x i16> %v
679}
680
681define <16 x i16> @vssubu_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {
682; CHECK-LABEL: vssubu_vv_v16i16_unmasked:
683; CHECK:       # %bb.0:
684; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
685; CHECK-NEXT:    vssubu.vv v8, v8, v10
686; CHECK-NEXT:    ret
687  %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)
688  ret <16 x i16> %v
689}
690
691define <16 x i16> @vssubu_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {
692; CHECK-LABEL: vssubu_vx_v16i16:
693; CHECK:       # %bb.0:
694; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
695; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t
696; CHECK-NEXT:    ret
697  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
698  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
699  %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)
700  ret <16 x i16> %v
701}
702
703define <16 x i16> @vssubu_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {
704; CHECK-LABEL: vssubu_vx_v16i16_unmasked:
705; CHECK:       # %bb.0:
706; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
707; CHECK-NEXT:    vssubu.vx v8, v8, a0
708; CHECK-NEXT:    ret
709  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
710  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
711  %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl)
712  ret <16 x i16> %v
713}
714
715define <16 x i16> @vssubu_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
716; CHECK-LABEL: vssubu_vi_v16i16:
717; CHECK:       # %bb.0:
718; CHECK-NEXT:    li a1, -1
719; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
720; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t
721; CHECK-NEXT:    ret
722  %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl)
723  ret <16 x i16> %v
724}
725
726define <16 x i16> @vssubu_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
727; CHECK-LABEL: vssubu_vi_v16i16_unmasked:
728; CHECK:       # %bb.0:
729; CHECK-NEXT:    li a1, -1
730; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
731; CHECK-NEXT:    vssubu.vx v8, v8, a1
732; CHECK-NEXT:    ret
733  %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl)
734  ret <16 x i16> %v
735}
736
737declare <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32)
738
739define <2 x i32> @vssubu_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {
740; CHECK-LABEL: vssubu_vv_v2i32:
741; CHECK:       # %bb.0:
742; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
743; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t
744; CHECK-NEXT:    ret
745  %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)
746  ret <2 x i32> %v
747}
748
749define <2 x i32> @vssubu_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {
750; CHECK-LABEL: vssubu_vv_v2i32_unmasked:
751; CHECK:       # %bb.0:
752; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
753; CHECK-NEXT:    vssubu.vv v8, v8, v9
754; CHECK-NEXT:    ret
755  %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)
756  ret <2 x i32> %v
757}
758
759define <2 x i32> @vssubu_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {
760; CHECK-LABEL: vssubu_vx_v2i32:
761; CHECK:       # %bb.0:
762; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
763; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t
764; CHECK-NEXT:    ret
765  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
766  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
767  %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)
768  ret <2 x i32> %v
769}
770
771define <2 x i32> @vssubu_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {
772; CHECK-LABEL: vssubu_vx_v2i32_unmasked:
773; CHECK:       # %bb.0:
774; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
775; CHECK-NEXT:    vssubu.vx v8, v8, a0
776; CHECK-NEXT:    ret
777  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
778  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
779  %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl)
780  ret <2 x i32> %v
781}
782
783define <2 x i32> @vssubu_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
784; CHECK-LABEL: vssubu_vi_v2i32:
785; CHECK:       # %bb.0:
786; CHECK-NEXT:    li a1, -1
787; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
788; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t
789; CHECK-NEXT:    ret
790  %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl)
791  ret <2 x i32> %v
792}
793
794define <2 x i32> @vssubu_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
795; CHECK-LABEL: vssubu_vi_v2i32_unmasked:
796; CHECK:       # %bb.0:
797; CHECK-NEXT:    li a1, -1
798; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
799; CHECK-NEXT:    vssubu.vx v8, v8, a1
800; CHECK-NEXT:    ret
801  %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl)
802  ret <2 x i32> %v
803}
804
805declare <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
806
807define <4 x i32> @vssubu_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {
808; CHECK-LABEL: vssubu_vv_v4i32:
809; CHECK:       # %bb.0:
810; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
811; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t
812; CHECK-NEXT:    ret
813  %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)
814  ret <4 x i32> %v
815}
816
817define <4 x i32> @vssubu_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {
818; CHECK-LABEL: vssubu_vv_v4i32_unmasked:
819; CHECK:       # %bb.0:
820; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
821; CHECK-NEXT:    vssubu.vv v8, v8, v9
822; CHECK-NEXT:    ret
823  %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)
824  ret <4 x i32> %v
825}
826
827define <4 x i32> @vssubu_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {
828; CHECK-LABEL: vssubu_vx_v4i32:
829; CHECK:       # %bb.0:
830; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
831; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t
832; CHECK-NEXT:    ret
833  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
834  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
835  %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)
836  ret <4 x i32> %v
837}
838
839define <4 x i32> @vssubu_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {
840; CHECK-LABEL: vssubu_vx_v4i32_unmasked:
841; CHECK:       # %bb.0:
842; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
843; CHECK-NEXT:    vssubu.vx v8, v8, a0
844; CHECK-NEXT:    ret
845  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
846  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
847  %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl)
848  ret <4 x i32> %v
849}
850
851define <4 x i32> @vssubu_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
852; CHECK-LABEL: vssubu_vi_v4i32:
853; CHECK:       # %bb.0:
854; CHECK-NEXT:    li a1, -1
855; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
856; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t
857; CHECK-NEXT:    ret
858  %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl)
859  ret <4 x i32> %v
860}
861
862define <4 x i32> @vssubu_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
863; CHECK-LABEL: vssubu_vi_v4i32_unmasked:
864; CHECK:       # %bb.0:
865; CHECK-NEXT:    li a1, -1
866; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
867; CHECK-NEXT:    vssubu.vx v8, v8, a1
868; CHECK-NEXT:    ret
869  %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl)
870  ret <4 x i32> %v
871}
872
873declare <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
874
875define <8 x i32> @vssubu_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {
876; CHECK-LABEL: vssubu_vv_v8i32:
877; CHECK:       # %bb.0:
878; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
879; CHECK-NEXT:    vssubu.vv v8, v8, v10, v0.t
880; CHECK-NEXT:    ret
881  %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)
882  ret <8 x i32> %v
883}
884
885define <8 x i32> @vssubu_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {
886; CHECK-LABEL: vssubu_vv_v8i32_unmasked:
887; CHECK:       # %bb.0:
888; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
889; CHECK-NEXT:    vssubu.vv v8, v8, v10
890; CHECK-NEXT:    ret
891  %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)
892  ret <8 x i32> %v
893}
894
895define <8 x i32> @vssubu_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {
896; CHECK-LABEL: vssubu_vx_v8i32:
897; CHECK:       # %bb.0:
898; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
899; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t
900; CHECK-NEXT:    ret
901  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
902  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
903  %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)
904  ret <8 x i32> %v
905}
906
907define <8 x i32> @vssubu_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {
908; CHECK-LABEL: vssubu_vx_v8i32_unmasked:
909; CHECK:       # %bb.0:
910; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
911; CHECK-NEXT:    vssubu.vx v8, v8, a0
912; CHECK-NEXT:    ret
913  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
914  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
915  %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl)
916  ret <8 x i32> %v
917}
918
919define <8 x i32> @vssubu_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
920; CHECK-LABEL: vssubu_vi_v8i32:
921; CHECK:       # %bb.0:
922; CHECK-NEXT:    li a1, -1
923; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
924; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t
925; CHECK-NEXT:    ret
926  %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl)
927  ret <8 x i32> %v
928}
929
930define <8 x i32> @vssubu_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
931; CHECK-LABEL: vssubu_vi_v8i32_unmasked:
932; CHECK:       # %bb.0:
933; CHECK-NEXT:    li a1, -1
934; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
935; CHECK-NEXT:    vssubu.vx v8, v8, a1
936; CHECK-NEXT:    ret
937  %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl)
938  ret <8 x i32> %v
939}
940
941declare <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32>, <16 x i32>, <16 x i1>, i32)
942
943define <16 x i32> @vssubu_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {
944; CHECK-LABEL: vssubu_vv_v16i32:
945; CHECK:       # %bb.0:
946; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
947; CHECK-NEXT:    vssubu.vv v8, v8, v12, v0.t
948; CHECK-NEXT:    ret
949  %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)
950  ret <16 x i32> %v
951}
952
953define <16 x i32> @vssubu_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {
954; CHECK-LABEL: vssubu_vv_v16i32_unmasked:
955; CHECK:       # %bb.0:
956; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
957; CHECK-NEXT:    vssubu.vv v8, v8, v12
958; CHECK-NEXT:    ret
959  %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)
960  ret <16 x i32> %v
961}
962
963define <16 x i32> @vssubu_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {
964; CHECK-LABEL: vssubu_vx_v16i32:
965; CHECK:       # %bb.0:
966; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
967; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t
968; CHECK-NEXT:    ret
969  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
970  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
971  %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)
972  ret <16 x i32> %v
973}
974
975define <16 x i32> @vssubu_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {
976; CHECK-LABEL: vssubu_vx_v16i32_unmasked:
977; CHECK:       # %bb.0:
978; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
979; CHECK-NEXT:    vssubu.vx v8, v8, a0
980; CHECK-NEXT:    ret
981  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
982  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
983  %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl)
984  ret <16 x i32> %v
985}
986
987define <16 x i32> @vssubu_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
988; CHECK-LABEL: vssubu_vi_v16i32:
989; CHECK:       # %bb.0:
990; CHECK-NEXT:    li a1, -1
991; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
992; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t
993; CHECK-NEXT:    ret
994  %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl)
995  ret <16 x i32> %v
996}
997
998define <16 x i32> @vssubu_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
999; CHECK-LABEL: vssubu_vi_v16i32_unmasked:
1000; CHECK:       # %bb.0:
1001; CHECK-NEXT:    li a1, -1
1002; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
1003; CHECK-NEXT:    vssubu.vx v8, v8, a1
1004; CHECK-NEXT:    ret
1005  %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl)
1006  ret <16 x i32> %v
1007}
1008
1009declare <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64>, <2 x i64>, <2 x i1>, i32)
1010
1011define <2 x i64> @vssubu_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {
1012; CHECK-LABEL: vssubu_vv_v2i64:
1013; CHECK:       # %bb.0:
1014; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1015; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t
1016; CHECK-NEXT:    ret
1017  %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)
1018  ret <2 x i64> %v
1019}
1020
1021define <2 x i64> @vssubu_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {
1022; CHECK-LABEL: vssubu_vv_v2i64_unmasked:
1023; CHECK:       # %bb.0:
1024; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1025; CHECK-NEXT:    vssubu.vv v8, v8, v9
1026; CHECK-NEXT:    ret
1027  %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)
1028  ret <2 x i64> %v
1029}
1030
1031define <2 x i64> @vssubu_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
1032; RV32-LABEL: vssubu_vx_v2i64:
1033; RV32:       # %bb.0:
1034; RV32-NEXT:    addi sp, sp, -16
1035; RV32-NEXT:    .cfi_def_cfa_offset 16
1036; RV32-NEXT:    sw a0, 8(sp)
1037; RV32-NEXT:    sw a1, 12(sp)
1038; RV32-NEXT:    addi a0, sp, 8
1039; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1040; RV32-NEXT:    vlse64.v v9, (a0), zero
1041; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
1042; RV32-NEXT:    vssubu.vv v8, v8, v9, v0.t
1043; RV32-NEXT:    addi sp, sp, 16
1044; RV32-NEXT:    .cfi_def_cfa_offset 0
1045; RV32-NEXT:    ret
1046;
1047; RV64-LABEL: vssubu_vx_v2i64:
1048; RV64:       # %bb.0:
1049; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
1050; RV64-NEXT:    vssubu.vx v8, v8, a0, v0.t
1051; RV64-NEXT:    ret
1052  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
1053  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
1054  %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
1055  ret <2 x i64> %v
1056}
1057
1058define <2 x i64> @vssubu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
1059; RV32-LABEL: vssubu_vx_v2i64_unmasked:
1060; RV32:       # %bb.0:
1061; RV32-NEXT:    addi sp, sp, -16
1062; RV32-NEXT:    .cfi_def_cfa_offset 16
1063; RV32-NEXT:    sw a0, 8(sp)
1064; RV32-NEXT:    sw a1, 12(sp)
1065; RV32-NEXT:    addi a0, sp, 8
1066; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1067; RV32-NEXT:    vlse64.v v9, (a0), zero
1068; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
1069; RV32-NEXT:    vssubu.vv v8, v8, v9
1070; RV32-NEXT:    addi sp, sp, 16
1071; RV32-NEXT:    .cfi_def_cfa_offset 0
1072; RV32-NEXT:    ret
1073;
1074; RV64-LABEL: vssubu_vx_v2i64_unmasked:
1075; RV64:       # %bb.0:
1076; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
1077; RV64-NEXT:    vssubu.vx v8, v8, a0
1078; RV64-NEXT:    ret
1079  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
1080  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
1081  %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl)
1082  ret <2 x i64> %v
1083}
1084
1085define <2 x i64> @vssubu_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
1086; CHECK-LABEL: vssubu_vi_v2i64:
1087; CHECK:       # %bb.0:
1088; CHECK-NEXT:    li a1, -1
1089; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1090; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t
1091; CHECK-NEXT:    ret
1092  %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl)
1093  ret <2 x i64> %v
1094}
1095
1096define <2 x i64> @vssubu_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
1097; CHECK-LABEL: vssubu_vi_v2i64_unmasked:
1098; CHECK:       # %bb.0:
1099; CHECK-NEXT:    li a1, -1
1100; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1101; CHECK-NEXT:    vssubu.vx v8, v8, a1
1102; CHECK-NEXT:    ret
1103  %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl)
1104  ret <2 x i64> %v
1105}
1106
1107declare <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64>, <4 x i64>, <4 x i1>, i32)
1108
1109define <4 x i64> @vssubu_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {
1110; CHECK-LABEL: vssubu_vv_v4i64:
1111; CHECK:       # %bb.0:
1112; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1113; CHECK-NEXT:    vssubu.vv v8, v8, v10, v0.t
1114; CHECK-NEXT:    ret
1115  %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)
1116  ret <4 x i64> %v
1117}
1118
1119define <4 x i64> @vssubu_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {
1120; CHECK-LABEL: vssubu_vv_v4i64_unmasked:
1121; CHECK:       # %bb.0:
1122; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1123; CHECK-NEXT:    vssubu.vv v8, v8, v10
1124; CHECK-NEXT:    ret
1125  %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)
1126  ret <4 x i64> %v
1127}
1128
1129define <4 x i64> @vssubu_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
1130; RV32-LABEL: vssubu_vx_v4i64:
1131; RV32:       # %bb.0:
1132; RV32-NEXT:    addi sp, sp, -16
1133; RV32-NEXT:    .cfi_def_cfa_offset 16
1134; RV32-NEXT:    sw a0, 8(sp)
1135; RV32-NEXT:    sw a1, 12(sp)
1136; RV32-NEXT:    addi a0, sp, 8
1137; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1138; RV32-NEXT:    vlse64.v v10, (a0), zero
1139; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
1140; RV32-NEXT:    vssubu.vv v8, v8, v10, v0.t
1141; RV32-NEXT:    addi sp, sp, 16
1142; RV32-NEXT:    .cfi_def_cfa_offset 0
1143; RV32-NEXT:    ret
1144;
1145; RV64-LABEL: vssubu_vx_v4i64:
1146; RV64:       # %bb.0:
1147; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
1148; RV64-NEXT:    vssubu.vx v8, v8, a0, v0.t
1149; RV64-NEXT:    ret
1150  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
1151  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
1152  %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
1153  ret <4 x i64> %v
1154}
1155
1156define <4 x i64> @vssubu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
1157; RV32-LABEL: vssubu_vx_v4i64_unmasked:
1158; RV32:       # %bb.0:
1159; RV32-NEXT:    addi sp, sp, -16
1160; RV32-NEXT:    .cfi_def_cfa_offset 16
1161; RV32-NEXT:    sw a0, 8(sp)
1162; RV32-NEXT:    sw a1, 12(sp)
1163; RV32-NEXT:    addi a0, sp, 8
1164; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1165; RV32-NEXT:    vlse64.v v10, (a0), zero
1166; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
1167; RV32-NEXT:    vssubu.vv v8, v8, v10
1168; RV32-NEXT:    addi sp, sp, 16
1169; RV32-NEXT:    .cfi_def_cfa_offset 0
1170; RV32-NEXT:    ret
1171;
1172; RV64-LABEL: vssubu_vx_v4i64_unmasked:
1173; RV64:       # %bb.0:
1174; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
1175; RV64-NEXT:    vssubu.vx v8, v8, a0
1176; RV64-NEXT:    ret
1177  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
1178  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
1179  %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl)
1180  ret <4 x i64> %v
1181}
1182
1183define <4 x i64> @vssubu_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
1184; CHECK-LABEL: vssubu_vi_v4i64:
1185; CHECK:       # %bb.0:
1186; CHECK-NEXT:    li a1, -1
1187; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1188; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t
1189; CHECK-NEXT:    ret
1190  %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl)
1191  ret <4 x i64> %v
1192}
1193
1194define <4 x i64> @vssubu_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
1195; CHECK-LABEL: vssubu_vi_v4i64_unmasked:
1196; CHECK:       # %bb.0:
1197; CHECK-NEXT:    li a1, -1
1198; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1199; CHECK-NEXT:    vssubu.vx v8, v8, a1
1200; CHECK-NEXT:    ret
1201  %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl)
1202  ret <4 x i64> %v
1203}
1204
1205declare <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64>, <8 x i64>, <8 x i1>, i32)
1206
1207define <8 x i64> @vssubu_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {
1208; CHECK-LABEL: vssubu_vv_v8i64:
1209; CHECK:       # %bb.0:
1210; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1211; CHECK-NEXT:    vssubu.vv v8, v8, v12, v0.t
1212; CHECK-NEXT:    ret
1213  %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)
1214  ret <8 x i64> %v
1215}
1216
1217define <8 x i64> @vssubu_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {
1218; CHECK-LABEL: vssubu_vv_v8i64_unmasked:
1219; CHECK:       # %bb.0:
1220; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1221; CHECK-NEXT:    vssubu.vv v8, v8, v12
1222; CHECK-NEXT:    ret
1223  %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)
1224  ret <8 x i64> %v
1225}
1226
1227define <8 x i64> @vssubu_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
1228; RV32-LABEL: vssubu_vx_v8i64:
1229; RV32:       # %bb.0:
1230; RV32-NEXT:    addi sp, sp, -16
1231; RV32-NEXT:    .cfi_def_cfa_offset 16
1232; RV32-NEXT:    sw a0, 8(sp)
1233; RV32-NEXT:    sw a1, 12(sp)
1234; RV32-NEXT:    addi a0, sp, 8
1235; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1236; RV32-NEXT:    vlse64.v v12, (a0), zero
1237; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
1238; RV32-NEXT:    vssubu.vv v8, v8, v12, v0.t
1239; RV32-NEXT:    addi sp, sp, 16
1240; RV32-NEXT:    .cfi_def_cfa_offset 0
1241; RV32-NEXT:    ret
1242;
1243; RV64-LABEL: vssubu_vx_v8i64:
1244; RV64:       # %bb.0:
1245; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
1246; RV64-NEXT:    vssubu.vx v8, v8, a0, v0.t
1247; RV64-NEXT:    ret
1248  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
1249  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
1250  %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
1251  ret <8 x i64> %v
1252}
1253
1254define <8 x i64> @vssubu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
1255; RV32-LABEL: vssubu_vx_v8i64_unmasked:
1256; RV32:       # %bb.0:
1257; RV32-NEXT:    addi sp, sp, -16
1258; RV32-NEXT:    .cfi_def_cfa_offset 16
1259; RV32-NEXT:    sw a0, 8(sp)
1260; RV32-NEXT:    sw a1, 12(sp)
1261; RV32-NEXT:    addi a0, sp, 8
1262; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1263; RV32-NEXT:    vlse64.v v12, (a0), zero
1264; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
1265; RV32-NEXT:    vssubu.vv v8, v8, v12
1266; RV32-NEXT:    addi sp, sp, 16
1267; RV32-NEXT:    .cfi_def_cfa_offset 0
1268; RV32-NEXT:    ret
1269;
1270; RV64-LABEL: vssubu_vx_v8i64_unmasked:
1271; RV64:       # %bb.0:
1272; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
1273; RV64-NEXT:    vssubu.vx v8, v8, a0
1274; RV64-NEXT:    ret
1275  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
1276  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
1277  %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl)
1278  ret <8 x i64> %v
1279}
1280
1281define <8 x i64> @vssubu_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
1282; CHECK-LABEL: vssubu_vi_v8i64:
1283; CHECK:       # %bb.0:
1284; CHECK-NEXT:    li a1, -1
1285; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1286; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t
1287; CHECK-NEXT:    ret
1288  %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl)
1289  ret <8 x i64> %v
1290}
1291
1292define <8 x i64> @vssubu_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
1293; CHECK-LABEL: vssubu_vi_v8i64_unmasked:
1294; CHECK:       # %bb.0:
1295; CHECK-NEXT:    li a1, -1
1296; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1297; CHECK-NEXT:    vssubu.vx v8, v8, a1
1298; CHECK-NEXT:    ret
1299  %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl)
1300  ret <8 x i64> %v
1301}
1302
1303declare <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64>, <16 x i64>, <16 x i1>, i32)
1304
1305define <16 x i64> @vssubu_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {
1306; CHECK-LABEL: vssubu_vv_v16i64:
1307; CHECK:       # %bb.0:
1308; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1309; CHECK-NEXT:    vssubu.vv v8, v8, v16, v0.t
1310; CHECK-NEXT:    ret
1311  %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)
1312  ret <16 x i64> %v
1313}
1314
1315define <16 x i64> @vssubu_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {
1316; CHECK-LABEL: vssubu_vv_v16i64_unmasked:
1317; CHECK:       # %bb.0:
1318; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1319; CHECK-NEXT:    vssubu.vv v8, v8, v16
1320; CHECK-NEXT:    ret
1321  %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)
1322  ret <16 x i64> %v
1323}
1324
1325define <16 x i64> @vssubu_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
1326; RV32-LABEL: vssubu_vx_v16i64:
1327; RV32:       # %bb.0:
1328; RV32-NEXT:    addi sp, sp, -16
1329; RV32-NEXT:    .cfi_def_cfa_offset 16
1330; RV32-NEXT:    sw a0, 8(sp)
1331; RV32-NEXT:    sw a1, 12(sp)
1332; RV32-NEXT:    addi a0, sp, 8
1333; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
1334; RV32-NEXT:    vlse64.v v16, (a0), zero
1335; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
1336; RV32-NEXT:    vssubu.vv v8, v8, v16, v0.t
1337; RV32-NEXT:    addi sp, sp, 16
1338; RV32-NEXT:    .cfi_def_cfa_offset 0
1339; RV32-NEXT:    ret
1340;
1341; RV64-LABEL: vssubu_vx_v16i64:
1342; RV64:       # %bb.0:
1343; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1344; RV64-NEXT:    vssubu.vx v8, v8, a0, v0.t
1345; RV64-NEXT:    ret
1346  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
1347  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
1348  %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
1349  ret <16 x i64> %v
1350}
1351
1352define <16 x i64> @vssubu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
1353; RV32-LABEL: vssubu_vx_v16i64_unmasked:
1354; RV32:       # %bb.0:
1355; RV32-NEXT:    addi sp, sp, -16
1356; RV32-NEXT:    .cfi_def_cfa_offset 16
1357; RV32-NEXT:    sw a0, 8(sp)
1358; RV32-NEXT:    sw a1, 12(sp)
1359; RV32-NEXT:    addi a0, sp, 8
1360; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
1361; RV32-NEXT:    vlse64.v v16, (a0), zero
1362; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
1363; RV32-NEXT:    vssubu.vv v8, v8, v16
1364; RV32-NEXT:    addi sp, sp, 16
1365; RV32-NEXT:    .cfi_def_cfa_offset 0
1366; RV32-NEXT:    ret
1367;
1368; RV64-LABEL: vssubu_vx_v16i64_unmasked:
1369; RV64:       # %bb.0:
1370; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1371; RV64-NEXT:    vssubu.vx v8, v8, a0
1372; RV64-NEXT:    ret
1373  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
1374  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
1375  %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl)
1376  ret <16 x i64> %v
1377}
1378
1379define <16 x i64> @vssubu_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
1380; CHECK-LABEL: vssubu_vi_v16i64:
1381; CHECK:       # %bb.0:
1382; CHECK-NEXT:    li a1, -1
1383; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1384; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t
1385; CHECK-NEXT:    ret
1386  %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl)
1387  ret <16 x i64> %v
1388}
1389
1390define <16 x i64> @vssubu_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
1391; CHECK-LABEL: vssubu_vi_v16i64_unmasked:
1392; CHECK:       # %bb.0:
1393; CHECK-NEXT:    li a1, -1
1394; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1395; CHECK-NEXT:    vssubu.vx v8, v8, a1
1396; CHECK-NEXT:    ret
1397  %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl)
1398  ret <16 x i64> %v
1399}
1400
1401; Test that split-legalization works as expected.
1402
1403declare <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64>, <32 x i64>, <32 x i1>, i32)
1404
1405define <32 x i64> @vssubu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
1406; CHECK-LABEL: vssubu_vx_v32i64:
1407; CHECK:       # %bb.0:
1408; CHECK-NEXT:    li a2, 16
1409; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
1410; CHECK-NEXT:    vslidedown.vi v24, v0, 2
1411; CHECK-NEXT:    mv a1, a0
1412; CHECK-NEXT:    bltu a0, a2, .LBB108_2
1413; CHECK-NEXT:  # %bb.1:
1414; CHECK-NEXT:    li a1, 16
1415; CHECK-NEXT:  .LBB108_2:
1416; CHECK-NEXT:    li a2, -1
1417; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1418; CHECK-NEXT:    vssubu.vx v8, v8, a2, v0.t
1419; CHECK-NEXT:    addi a1, a0, -16
1420; CHECK-NEXT:    sltu a0, a0, a1
1421; CHECK-NEXT:    addi a0, a0, -1
1422; CHECK-NEXT:    and a0, a0, a1
1423; CHECK-NEXT:    vmv1r.v v0, v24
1424; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1425; CHECK-NEXT:    vssubu.vx v16, v16, a2, v0.t
1426; CHECK-NEXT:    ret
1427  %v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)
1428  ret <32 x i64> %v
1429}
1430
1431define <32 x i64> @vssubu_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
1432; CHECK-LABEL: vssubu_vi_v32i64_unmasked:
1433; CHECK:       # %bb.0:
1434; CHECK-NEXT:    li a2, 16
1435; CHECK-NEXT:    mv a1, a0
1436; CHECK-NEXT:    bltu a0, a2, .LBB109_2
1437; CHECK-NEXT:  # %bb.1:
1438; CHECK-NEXT:    li a1, 16
1439; CHECK-NEXT:  .LBB109_2:
1440; CHECK-NEXT:    li a2, -1
1441; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1442; CHECK-NEXT:    vssubu.vx v8, v8, a2
1443; CHECK-NEXT:    addi a1, a0, -16
1444; CHECK-NEXT:    sltu a0, a0, a1
1445; CHECK-NEXT:    addi a0, a0, -1
1446; CHECK-NEXT:    and a0, a0, a1
1447; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1448; CHECK-NEXT:    vssubu.vx v16, v16, a2
1449; CHECK-NEXT:    ret
1450  %v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl)
1451  ret <32 x i64> %v
1452}
1453
1454define <32 x i64> @vssubu_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
1455; CHECK-LABEL: vssubu_vx_v32i64_evl12:
1456; CHECK:       # %bb.0:
1457; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
1458; CHECK-NEXT:    vslidedown.vi v24, v0, 2
1459; CHECK-NEXT:    li a0, -1
1460; CHECK-NEXT:    vsetivli zero, 12, e64, m8, ta, ma
1461; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t
1462; CHECK-NEXT:    vmv1r.v v0, v24
1463; CHECK-NEXT:    vsetivli zero, 0, e64, m8, ta, ma
1464; CHECK-NEXT:    vssubu.vx v16, v16, a0, v0.t
1465; CHECK-NEXT:    ret
1466  %v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12)
1467  ret <32 x i64> %v
1468}
1469
1470define <32 x i64> @vssubu_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
1471; CHECK-LABEL: vssubu_vx_v32i64_evl27:
1472; CHECK:       # %bb.0:
1473; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
1474; CHECK-NEXT:    vslidedown.vi v24, v0, 2
1475; CHECK-NEXT:    li a0, -1
1476; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
1477; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t
1478; CHECK-NEXT:    vmv1r.v v0, v24
1479; CHECK-NEXT:    vsetivli zero, 11, e64, m8, ta, ma
1480; CHECK-NEXT:    vssubu.vx v16, v16, a0, v0.t
1481; CHECK-NEXT:    ret
1482  %v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 27)
1483  ret <32 x i64> %v
1484}
1485