xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64
6
7declare <8 x i7> @llvm.vp.ssub.sat.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32)
8
9define <8 x i7> @vssub_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
10; CHECK-LABEL: vssub_vv_v8i7:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
13; CHECK-NEXT:    vadd.vv v9, v9, v9
14; CHECK-NEXT:    vadd.vv v8, v8, v8
15; CHECK-NEXT:    li a1, 63
16; CHECK-NEXT:    vsra.vi v9, v9, 1
17; CHECK-NEXT:    vsra.vi v8, v8, 1
18; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
19; CHECK-NEXT:    vsub.vv v8, v8, v9, v0.t
20; CHECK-NEXT:    vmin.vx v8, v8, a1, v0.t
21; CHECK-NEXT:    li a0, 192
22; CHECK-NEXT:    vmax.vx v8, v8, a0, v0.t
23; CHECK-NEXT:    ret
24  %v = call <8 x i7> @llvm.vp.ssub.sat.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
25  ret <8 x i7> %v
26}
27
28declare <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32)
29
30define <2 x i8> @vssub_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {
31; CHECK-LABEL: vssub_vv_v2i8:
32; CHECK:       # %bb.0:
33; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
34; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
35; CHECK-NEXT:    ret
36  %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)
37  ret <2 x i8> %v
38}
39
40define <2 x i8> @vssub_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {
41; CHECK-LABEL: vssub_vv_v2i8_unmasked:
42; CHECK:       # %bb.0:
43; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
44; CHECK-NEXT:    vssub.vv v8, v8, v9
45; CHECK-NEXT:    ret
46  %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)
47  ret <2 x i8> %v
48}
49
50define <2 x i8> @vssub_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
51; CHECK-LABEL: vssub_vx_v2i8:
52; CHECK:       # %bb.0:
53; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
54; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
55; CHECK-NEXT:    ret
56  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
57  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
58  %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)
59  ret <2 x i8> %v
60}
61
62define <2 x i8> @vssub_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
63; CHECK-LABEL: vssub_vx_v2i8_unmasked:
64; CHECK:       # %bb.0:
65; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
66; CHECK-NEXT:    vssub.vx v8, v8, a0
67; CHECK-NEXT:    ret
68  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
69  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
70  %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl)
71  ret <2 x i8> %v
72}
73
74define <2 x i8> @vssub_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
75; CHECK-LABEL: vssub_vi_v2i8:
76; CHECK:       # %bb.0:
77; CHECK-NEXT:    li a1, -1
78; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
79; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
80; CHECK-NEXT:    ret
81  %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl)
82  ret <2 x i8> %v
83}
84
85define <2 x i8> @vssub_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
86; CHECK-LABEL: vssub_vi_v2i8_unmasked:
87; CHECK:       # %bb.0:
88; CHECK-NEXT:    li a1, -1
89; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
90; CHECK-NEXT:    vssub.vx v8, v8, a1
91; CHECK-NEXT:    ret
92  %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl)
93  ret <2 x i8> %v
94}
95
96declare <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8>, <4 x i8>, <4 x i1>, i32)
97
98define <4 x i8> @vssub_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {
99; CHECK-LABEL: vssub_vv_v4i8:
100; CHECK:       # %bb.0:
101; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
102; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
103; CHECK-NEXT:    ret
104  %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)
105  ret <4 x i8> %v
106}
107
108define <4 x i8> @vssub_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {
109; CHECK-LABEL: vssub_vv_v4i8_unmasked:
110; CHECK:       # %bb.0:
111; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
112; CHECK-NEXT:    vssub.vv v8, v8, v9
113; CHECK-NEXT:    ret
114  %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)
115  ret <4 x i8> %v
116}
117
118define <4 x i8> @vssub_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
119; CHECK-LABEL: vssub_vx_v4i8:
120; CHECK:       # %bb.0:
121; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
122; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
123; CHECK-NEXT:    ret
124  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
125  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
126  %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)
127  ret <4 x i8> %v
128}
129
130define <4 x i8> @vssub_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
131; CHECK-LABEL: vssub_vx_v4i8_commute:
132; CHECK:       # %bb.0:
133; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
134; CHECK-NEXT:    vmv.v.x v9, a0
135; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
136; CHECK-NEXT:    vssub.vv v8, v9, v8, v0.t
137; CHECK-NEXT:    ret
138  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
139  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
140  %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl)
141  ret <4 x i8> %v
142}
143
144define <4 x i8> @vssub_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
145; CHECK-LABEL: vssub_vx_v4i8_unmasked:
146; CHECK:       # %bb.0:
147; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
148; CHECK-NEXT:    vssub.vx v8, v8, a0
149; CHECK-NEXT:    ret
150  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
151  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
152  %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl)
153  ret <4 x i8> %v
154}
155
156define <4 x i8> @vssub_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
157; CHECK-LABEL: vssub_vi_v4i8:
158; CHECK:       # %bb.0:
159; CHECK-NEXT:    li a1, -1
160; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
161; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
162; CHECK-NEXT:    ret
163  %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl)
164  ret <4 x i8> %v
165}
166
167define <4 x i8> @vssub_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
168; CHECK-LABEL: vssub_vi_v4i8_unmasked:
169; CHECK:       # %bb.0:
170; CHECK-NEXT:    li a1, -1
171; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
172; CHECK-NEXT:    vssub.vx v8, v8, a1
173; CHECK-NEXT:    ret
174  %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl)
175  ret <4 x i8> %v
176}
177
178declare <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8>, <5 x i8>, <5 x i1>, i32)
179
180define <5 x i8> @vssub_vv_v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 zeroext %evl) {
181; CHECK-LABEL: vssub_vv_v5i8:
182; CHECK:       # %bb.0:
183; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
184; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
185; CHECK-NEXT:    ret
186  %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl)
187  ret <5 x i8> %v
188}
189
190define <5 x i8> @vssub_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %evl) {
191; CHECK-LABEL: vssub_vv_v5i8_unmasked:
192; CHECK:       # %bb.0:
193; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
194; CHECK-NEXT:    vssub.vv v8, v8, v9
195; CHECK-NEXT:    ret
196  %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl)
197  ret <5 x i8> %v
198}
199
200define <5 x i8> @vssub_vx_v5i8(<5 x i8> %va, i8 %b, <5 x i1> %m, i32 zeroext %evl) {
201; CHECK-LABEL: vssub_vx_v5i8:
202; CHECK:       # %bb.0:
203; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
204; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
205; CHECK-NEXT:    ret
206  %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
207  %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer
208  %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl)
209  ret <5 x i8> %v
210}
211
212define <5 x i8> @vssub_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) {
213; CHECK-LABEL: vssub_vx_v5i8_unmasked:
214; CHECK:       # %bb.0:
215; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
216; CHECK-NEXT:    vssub.vx v8, v8, a0
217; CHECK-NEXT:    ret
218  %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
219  %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer
220  %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl)
221  ret <5 x i8> %v
222}
223
224define <5 x i8> @vssub_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) {
225; CHECK-LABEL: vssub_vi_v5i8:
226; CHECK:       # %bb.0:
227; CHECK-NEXT:    li a1, -1
228; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
229; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
230; CHECK-NEXT:    ret
231  %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> %m, i32 %evl)
232  ret <5 x i8> %v
233}
234
235define <5 x i8> @vssub_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) {
236; CHECK-LABEL: vssub_vi_v5i8_unmasked:
237; CHECK:       # %bb.0:
238; CHECK-NEXT:    li a1, -1
239; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
240; CHECK-NEXT:    vssub.vx v8, v8, a1
241; CHECK-NEXT:    ret
242  %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> splat (i1 true), i32 %evl)
243  ret <5 x i8> %v
244}
245
246declare <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8>, <8 x i8>, <8 x i1>, i32)
247
248define <8 x i8> @vssub_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {
249; CHECK-LABEL: vssub_vv_v8i8:
250; CHECK:       # %bb.0:
251; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
252; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
253; CHECK-NEXT:    ret
254  %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)
255  ret <8 x i8> %v
256}
257
258define <8 x i8> @vssub_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {
259; CHECK-LABEL: vssub_vv_v8i8_unmasked:
260; CHECK:       # %bb.0:
261; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
262; CHECK-NEXT:    vssub.vv v8, v8, v9
263; CHECK-NEXT:    ret
264  %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)
265  ret <8 x i8> %v
266}
267
268define <8 x i8> @vssub_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {
269; CHECK-LABEL: vssub_vx_v8i8:
270; CHECK:       # %bb.0:
271; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
272; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
273; CHECK-NEXT:    ret
274  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
275  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
276  %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)
277  ret <8 x i8> %v
278}
279
280define <8 x i8> @vssub_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
281; CHECK-LABEL: vssub_vx_v8i8_unmasked:
282; CHECK:       # %bb.0:
283; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
284; CHECK-NEXT:    vssub.vx v8, v8, a0
285; CHECK-NEXT:    ret
286  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
287  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
288  %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl)
289  ret <8 x i8> %v
290}
291
292define <8 x i8> @vssub_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
293; CHECK-LABEL: vssub_vi_v8i8:
294; CHECK:       # %bb.0:
295; CHECK-NEXT:    li a1, -1
296; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
297; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
298; CHECK-NEXT:    ret
299  %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl)
300  ret <8 x i8> %v
301}
302
303define <8 x i8> @vssub_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
304; CHECK-LABEL: vssub_vi_v8i8_unmasked:
305; CHECK:       # %bb.0:
306; CHECK-NEXT:    li a1, -1
307; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
308; CHECK-NEXT:    vssub.vx v8, v8, a1
309; CHECK-NEXT:    ret
310  %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl)
311  ret <8 x i8> %v
312}
313
314declare <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8>, <16 x i8>, <16 x i1>, i32)
315
316define <16 x i8> @vssub_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {
317; CHECK-LABEL: vssub_vv_v16i8:
318; CHECK:       # %bb.0:
319; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
320; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
321; CHECK-NEXT:    ret
322  %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)
323  ret <16 x i8> %v
324}
325
326define <16 x i8> @vssub_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {
327; CHECK-LABEL: vssub_vv_v16i8_unmasked:
328; CHECK:       # %bb.0:
329; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
330; CHECK-NEXT:    vssub.vv v8, v8, v9
331; CHECK-NEXT:    ret
332  %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)
333  ret <16 x i8> %v
334}
335
336define <16 x i8> @vssub_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {
337; CHECK-LABEL: vssub_vx_v16i8:
338; CHECK:       # %bb.0:
339; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
340; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
341; CHECK-NEXT:    ret
342  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
343  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
344  %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)
345  ret <16 x i8> %v
346}
347
348define <16 x i8> @vssub_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {
349; CHECK-LABEL: vssub_vx_v16i8_unmasked:
350; CHECK:       # %bb.0:
351; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
352; CHECK-NEXT:    vssub.vx v8, v8, a0
353; CHECK-NEXT:    ret
354  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
355  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
356  %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl)
357  ret <16 x i8> %v
358}
359
360define <16 x i8> @vssub_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
361; CHECK-LABEL: vssub_vi_v16i8:
362; CHECK:       # %bb.0:
363; CHECK-NEXT:    li a1, -1
364; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
365; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
366; CHECK-NEXT:    ret
367  %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl)
368  ret <16 x i8> %v
369}
370
371define <16 x i8> @vssub_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
372; CHECK-LABEL: vssub_vi_v16i8_unmasked:
373; CHECK:       # %bb.0:
374; CHECK-NEXT:    li a1, -1
375; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
376; CHECK-NEXT:    vssub.vx v8, v8, a1
377; CHECK-NEXT:    ret
378  %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl)
379  ret <16 x i8> %v
380}
381
382declare <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8>, <256 x i8>, <256 x i1>, i32)
383
384define <256 x i8> @vssub_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %evl) {
385; CHECK-LABEL: vssub_vi_v258i8:
386; CHECK:       # %bb.0:
387; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
388; CHECK-NEXT:    vmv1r.v v24, v0
389; CHECK-NEXT:    li a2, 128
390; CHECK-NEXT:    addi a3, a1, -128
391; CHECK-NEXT:    vsetvli zero, a2, e8, m8, ta, ma
392; CHECK-NEXT:    vlm.v v0, (a0)
393; CHECK-NEXT:    sltu a0, a1, a3
394; CHECK-NEXT:    addi a0, a0, -1
395; CHECK-NEXT:    and a3, a0, a3
396; CHECK-NEXT:    li a0, -1
397; CHECK-NEXT:    vsetvli zero, a3, e8, m8, ta, ma
398; CHECK-NEXT:    vssub.vx v16, v16, a0, v0.t
399; CHECK-NEXT:    bltu a1, a2, .LBB32_2
400; CHECK-NEXT:  # %bb.1:
401; CHECK-NEXT:    li a1, 128
402; CHECK-NEXT:  .LBB32_2:
403; CHECK-NEXT:    vmv1r.v v0, v24
404; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
405; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
406; CHECK-NEXT:    ret
407  %v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 %evl)
408  ret <256 x i8> %v
409}
410
411define <256 x i8> @vssub_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) {
412; CHECK-LABEL: vssub_vi_v258i8_unmasked:
413; CHECK:       # %bb.0:
414; CHECK-NEXT:    li a2, 128
415; CHECK-NEXT:    mv a1, a0
416; CHECK-NEXT:    bltu a0, a2, .LBB33_2
417; CHECK-NEXT:  # %bb.1:
418; CHECK-NEXT:    li a1, 128
419; CHECK-NEXT:  .LBB33_2:
420; CHECK-NEXT:    li a2, -1
421; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
422; CHECK-NEXT:    vssub.vx v8, v8, a2
423; CHECK-NEXT:    addi a1, a0, -128
424; CHECK-NEXT:    sltu a0, a0, a1
425; CHECK-NEXT:    addi a0, a0, -1
426; CHECK-NEXT:    and a0, a0, a1
427; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
428; CHECK-NEXT:    vssub.vx v16, v16, a2
429; CHECK-NEXT:    ret
430  %v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> splat (i1 true), i32 %evl)
431  ret <256 x i8> %v
432}
433
434; Test splitting when the %evl is a known constant.
435
436define <256 x i8> @vssub_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
437; CHECK-LABEL: vssub_vi_v258i8_evl129:
438; CHECK:       # %bb.0:
439; CHECK-NEXT:    li a1, 128
440; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
441; CHECK-NEXT:    vlm.v v24, (a0)
442; CHECK-NEXT:    li a0, -1
443; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
444; CHECK-NEXT:    vmv1r.v v0, v24
445; CHECK-NEXT:    vsetivli zero, 1, e8, m8, ta, ma
446; CHECK-NEXT:    vssub.vx v16, v16, a0, v0.t
447; CHECK-NEXT:    ret
448  %v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 129)
449  ret <256 x i8> %v
450}
451
452; FIXME: The upper half is doing nothing.
453
454define <256 x i8> @vssub_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
455; CHECK-LABEL: vssub_vi_v258i8_evl128:
456; CHECK:       # %bb.0:
457; CHECK-NEXT:    li a1, 128
458; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
459; CHECK-NEXT:    vlm.v v24, (a0)
460; CHECK-NEXT:    li a0, -1
461; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
462; CHECK-NEXT:    vmv1r.v v0, v24
463; CHECK-NEXT:    vsetivli zero, 0, e8, m8, ta, ma
464; CHECK-NEXT:    vssub.vx v16, v16, a0, v0.t
465; CHECK-NEXT:    ret
466  %v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)
467  ret <256 x i8> %v
468}
469
470declare <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16>, <2 x i16>, <2 x i1>, i32)
471
472define <2 x i16> @vssub_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {
473; CHECK-LABEL: vssub_vv_v2i16:
474; CHECK:       # %bb.0:
475; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
476; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
477; CHECK-NEXT:    ret
478  %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)
479  ret <2 x i16> %v
480}
481
482define <2 x i16> @vssub_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {
483; CHECK-LABEL: vssub_vv_v2i16_unmasked:
484; CHECK:       # %bb.0:
485; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
486; CHECK-NEXT:    vssub.vv v8, v8, v9
487; CHECK-NEXT:    ret
488  %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)
489  ret <2 x i16> %v
490}
491
492define <2 x i16> @vssub_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {
493; CHECK-LABEL: vssub_vx_v2i16:
494; CHECK:       # %bb.0:
495; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
496; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
497; CHECK-NEXT:    ret
498  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
499  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
500  %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)
501  ret <2 x i16> %v
502}
503
504define <2 x i16> @vssub_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {
505; CHECK-LABEL: vssub_vx_v2i16_unmasked:
506; CHECK:       # %bb.0:
507; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
508; CHECK-NEXT:    vssub.vx v8, v8, a0
509; CHECK-NEXT:    ret
510  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
511  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
512  %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl)
513  ret <2 x i16> %v
514}
515
516define <2 x i16> @vssub_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
517; CHECK-LABEL: vssub_vi_v2i16:
518; CHECK:       # %bb.0:
519; CHECK-NEXT:    li a1, -1
520; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
521; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
522; CHECK-NEXT:    ret
523  %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl)
524  ret <2 x i16> %v
525}
526
527define <2 x i16> @vssub_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
528; CHECK-LABEL: vssub_vi_v2i16_unmasked:
529; CHECK:       # %bb.0:
530; CHECK-NEXT:    li a1, -1
531; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
532; CHECK-NEXT:    vssub.vx v8, v8, a1
533; CHECK-NEXT:    ret
534  %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl)
535  ret <2 x i16> %v
536}
537
538declare <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16>, <4 x i16>, <4 x i1>, i32)
539
540define <4 x i16> @vssub_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {
541; CHECK-LABEL: vssub_vv_v4i16:
542; CHECK:       # %bb.0:
543; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
544; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
545; CHECK-NEXT:    ret
546  %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)
547  ret <4 x i16> %v
548}
549
550define <4 x i16> @vssub_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {
551; CHECK-LABEL: vssub_vv_v4i16_unmasked:
552; CHECK:       # %bb.0:
553; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
554; CHECK-NEXT:    vssub.vv v8, v8, v9
555; CHECK-NEXT:    ret
556  %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)
557  ret <4 x i16> %v
558}
559
560define <4 x i16> @vssub_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {
561; CHECK-LABEL: vssub_vx_v4i16:
562; CHECK:       # %bb.0:
563; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
564; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
565; CHECK-NEXT:    ret
566  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
567  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
568  %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)
569  ret <4 x i16> %v
570}
571
572define <4 x i16> @vssub_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {
573; CHECK-LABEL: vssub_vx_v4i16_unmasked:
574; CHECK:       # %bb.0:
575; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
576; CHECK-NEXT:    vssub.vx v8, v8, a0
577; CHECK-NEXT:    ret
578  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
579  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
580  %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl)
581  ret <4 x i16> %v
582}
583
584define <4 x i16> @vssub_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
585; CHECK-LABEL: vssub_vi_v4i16:
586; CHECK:       # %bb.0:
587; CHECK-NEXT:    li a1, -1
588; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
589; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
590; CHECK-NEXT:    ret
591  %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl)
592  ret <4 x i16> %v
593}
594
595define <4 x i16> @vssub_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
596; CHECK-LABEL: vssub_vi_v4i16_unmasked:
597; CHECK:       # %bb.0:
598; CHECK-NEXT:    li a1, -1
599; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
600; CHECK-NEXT:    vssub.vx v8, v8, a1
601; CHECK-NEXT:    ret
602  %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl)
603  ret <4 x i16> %v
604}
605
606declare <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16>, <8 x i16>, <8 x i1>, i32)
607
608define <8 x i16> @vssub_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {
609; CHECK-LABEL: vssub_vv_v8i16:
610; CHECK:       # %bb.0:
611; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
612; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
613; CHECK-NEXT:    ret
614  %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)
615  ret <8 x i16> %v
616}
617
618define <8 x i16> @vssub_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {
619; CHECK-LABEL: vssub_vv_v8i16_unmasked:
620; CHECK:       # %bb.0:
621; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
622; CHECK-NEXT:    vssub.vv v8, v8, v9
623; CHECK-NEXT:    ret
624  %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)
625  ret <8 x i16> %v
626}
627
628define <8 x i16> @vssub_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {
629; CHECK-LABEL: vssub_vx_v8i16:
630; CHECK:       # %bb.0:
631; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
632; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
633; CHECK-NEXT:    ret
634  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
635  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
636  %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)
637  ret <8 x i16> %v
638}
639
640define <8 x i16> @vssub_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {
641; CHECK-LABEL: vssub_vx_v8i16_unmasked:
642; CHECK:       # %bb.0:
643; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
644; CHECK-NEXT:    vssub.vx v8, v8, a0
645; CHECK-NEXT:    ret
646  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
647  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
648  %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl)
649  ret <8 x i16> %v
650}
651
652define <8 x i16> @vssub_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
653; CHECK-LABEL: vssub_vi_v8i16:
654; CHECK:       # %bb.0:
655; CHECK-NEXT:    li a1, -1
656; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
657; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
658; CHECK-NEXT:    ret
659  %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl)
660  ret <8 x i16> %v
661}
662
663define <8 x i16> @vssub_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
664; CHECK-LABEL: vssub_vi_v8i16_unmasked:
665; CHECK:       # %bb.0:
666; CHECK-NEXT:    li a1, -1
667; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
668; CHECK-NEXT:    vssub.vx v8, v8, a1
669; CHECK-NEXT:    ret
670  %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl)
671  ret <8 x i16> %v
672}
673
674declare <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16>, <16 x i16>, <16 x i1>, i32)
675
676define <16 x i16> @vssub_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {
677; CHECK-LABEL: vssub_vv_v16i16:
678; CHECK:       # %bb.0:
679; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
680; CHECK-NEXT:    vssub.vv v8, v8, v10, v0.t
681; CHECK-NEXT:    ret
682  %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)
683  ret <16 x i16> %v
684}
685
686define <16 x i16> @vssub_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {
687; CHECK-LABEL: vssub_vv_v16i16_unmasked:
688; CHECK:       # %bb.0:
689; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
690; CHECK-NEXT:    vssub.vv v8, v8, v10
691; CHECK-NEXT:    ret
692  %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)
693  ret <16 x i16> %v
694}
695
696define <16 x i16> @vssub_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {
697; CHECK-LABEL: vssub_vx_v16i16:
698; CHECK:       # %bb.0:
699; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
700; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
701; CHECK-NEXT:    ret
702  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
703  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
704  %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)
705  ret <16 x i16> %v
706}
707
708define <16 x i16> @vssub_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {
709; CHECK-LABEL: vssub_vx_v16i16_unmasked:
710; CHECK:       # %bb.0:
711; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
712; CHECK-NEXT:    vssub.vx v8, v8, a0
713; CHECK-NEXT:    ret
714  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
715  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
716  %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl)
717  ret <16 x i16> %v
718}
719
720define <16 x i16> @vssub_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
721; CHECK-LABEL: vssub_vi_v16i16:
722; CHECK:       # %bb.0:
723; CHECK-NEXT:    li a1, -1
724; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
725; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
726; CHECK-NEXT:    ret
727  %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl)
728  ret <16 x i16> %v
729}
730
731define <16 x i16> @vssub_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
732; CHECK-LABEL: vssub_vi_v16i16_unmasked:
733; CHECK:       # %bb.0:
734; CHECK-NEXT:    li a1, -1
735; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
736; CHECK-NEXT:    vssub.vx v8, v8, a1
737; CHECK-NEXT:    ret
738  %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl)
739  ret <16 x i16> %v
740}
741
742declare <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32)
743
744define <2 x i32> @vssub_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {
745; CHECK-LABEL: vssub_vv_v2i32:
746; CHECK:       # %bb.0:
747; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
748; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
749; CHECK-NEXT:    ret
750  %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)
751  ret <2 x i32> %v
752}
753
754define <2 x i32> @vssub_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {
755; CHECK-LABEL: vssub_vv_v2i32_unmasked:
756; CHECK:       # %bb.0:
757; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
758; CHECK-NEXT:    vssub.vv v8, v8, v9
759; CHECK-NEXT:    ret
760  %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)
761  ret <2 x i32> %v
762}
763
764define <2 x i32> @vssub_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {
765; CHECK-LABEL: vssub_vx_v2i32:
766; CHECK:       # %bb.0:
767; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
768; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
769; CHECK-NEXT:    ret
770  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
771  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
772  %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)
773  ret <2 x i32> %v
774}
775
776define <2 x i32> @vssub_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {
777; CHECK-LABEL: vssub_vx_v2i32_unmasked:
778; CHECK:       # %bb.0:
779; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
780; CHECK-NEXT:    vssub.vx v8, v8, a0
781; CHECK-NEXT:    ret
782  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
783  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
784  %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl)
785  ret <2 x i32> %v
786}
787
788define <2 x i32> @vssub_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
789; CHECK-LABEL: vssub_vi_v2i32:
790; CHECK:       # %bb.0:
791; CHECK-NEXT:    li a1, -1
792; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
793; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
794; CHECK-NEXT:    ret
795  %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl)
796  ret <2 x i32> %v
797}
798
799define <2 x i32> @vssub_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
800; CHECK-LABEL: vssub_vi_v2i32_unmasked:
801; CHECK:       # %bb.0:
802; CHECK-NEXT:    li a1, -1
803; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
804; CHECK-NEXT:    vssub.vx v8, v8, a1
805; CHECK-NEXT:    ret
806  %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl)
807  ret <2 x i32> %v
808}
809
810declare <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
811
812define <4 x i32> @vssub_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {
813; CHECK-LABEL: vssub_vv_v4i32:
814; CHECK:       # %bb.0:
815; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
816; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
817; CHECK-NEXT:    ret
818  %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)
819  ret <4 x i32> %v
820}
821
822define <4 x i32> @vssub_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {
823; CHECK-LABEL: vssub_vv_v4i32_unmasked:
824; CHECK:       # %bb.0:
825; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
826; CHECK-NEXT:    vssub.vv v8, v8, v9
827; CHECK-NEXT:    ret
828  %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)
829  ret <4 x i32> %v
830}
831
832define <4 x i32> @vssub_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {
833; CHECK-LABEL: vssub_vx_v4i32:
834; CHECK:       # %bb.0:
835; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
836; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
837; CHECK-NEXT:    ret
838  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
839  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
840  %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)
841  ret <4 x i32> %v
842}
843
844define <4 x i32> @vssub_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {
845; CHECK-LABEL: vssub_vx_v4i32_unmasked:
846; CHECK:       # %bb.0:
847; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
848; CHECK-NEXT:    vssub.vx v8, v8, a0
849; CHECK-NEXT:    ret
850  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
851  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
852  %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl)
853  ret <4 x i32> %v
854}
855
856define <4 x i32> @vssub_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
857; CHECK-LABEL: vssub_vi_v4i32:
858; CHECK:       # %bb.0:
859; CHECK-NEXT:    li a1, -1
860; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
861; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
862; CHECK-NEXT:    ret
863  %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl)
864  ret <4 x i32> %v
865}
866
867define <4 x i32> @vssub_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
868; CHECK-LABEL: vssub_vi_v4i32_unmasked:
869; CHECK:       # %bb.0:
870; CHECK-NEXT:    li a1, -1
871; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
872; CHECK-NEXT:    vssub.vx v8, v8, a1
873; CHECK-NEXT:    ret
874  %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl)
875  ret <4 x i32> %v
876}
877
878declare <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
879
880define <8 x i32> @vssub_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {
881; CHECK-LABEL: vssub_vv_v8i32:
882; CHECK:       # %bb.0:
883; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
884; CHECK-NEXT:    vssub.vv v8, v8, v10, v0.t
885; CHECK-NEXT:    ret
886  %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)
887  ret <8 x i32> %v
888}
889
890define <8 x i32> @vssub_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {
891; CHECK-LABEL: vssub_vv_v8i32_unmasked:
892; CHECK:       # %bb.0:
893; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
894; CHECK-NEXT:    vssub.vv v8, v8, v10
895; CHECK-NEXT:    ret
896  %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)
897  ret <8 x i32> %v
898}
899
900define <8 x i32> @vssub_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {
901; CHECK-LABEL: vssub_vx_v8i32:
902; CHECK:       # %bb.0:
903; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
904; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
905; CHECK-NEXT:    ret
906  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
907  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
908  %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)
909  ret <8 x i32> %v
910}
911
912define <8 x i32> @vssub_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {
913; CHECK-LABEL: vssub_vx_v8i32_unmasked:
914; CHECK:       # %bb.0:
915; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
916; CHECK-NEXT:    vssub.vx v8, v8, a0
917; CHECK-NEXT:    ret
918  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
919  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
920  %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl)
921  ret <8 x i32> %v
922}
923
924define <8 x i32> @vssub_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
925; CHECK-LABEL: vssub_vi_v8i32:
926; CHECK:       # %bb.0:
927; CHECK-NEXT:    li a1, -1
928; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
929; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
930; CHECK-NEXT:    ret
931  %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl)
932  ret <8 x i32> %v
933}
934
935define <8 x i32> @vssub_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
936; CHECK-LABEL: vssub_vi_v8i32_unmasked:
937; CHECK:       # %bb.0:
938; CHECK-NEXT:    li a1, -1
939; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
940; CHECK-NEXT:    vssub.vx v8, v8, a1
941; CHECK-NEXT:    ret
942  %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl)
943  ret <8 x i32> %v
944}
945
946declare <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32>, <16 x i32>, <16 x i1>, i32)
947
948define <16 x i32> @vssub_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {
949; CHECK-LABEL: vssub_vv_v16i32:
950; CHECK:       # %bb.0:
951; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
952; CHECK-NEXT:    vssub.vv v8, v8, v12, v0.t
953; CHECK-NEXT:    ret
954  %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)
955  ret <16 x i32> %v
956}
957
958define <16 x i32> @vssub_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {
959; CHECK-LABEL: vssub_vv_v16i32_unmasked:
960; CHECK:       # %bb.0:
961; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
962; CHECK-NEXT:    vssub.vv v8, v8, v12
963; CHECK-NEXT:    ret
964  %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)
965  ret <16 x i32> %v
966}
967
968define <16 x i32> @vssub_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {
969; CHECK-LABEL: vssub_vx_v16i32:
970; CHECK:       # %bb.0:
971; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
972; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
973; CHECK-NEXT:    ret
974  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
975  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
976  %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)
977  ret <16 x i32> %v
978}
979
980define <16 x i32> @vssub_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {
981; CHECK-LABEL: vssub_vx_v16i32_unmasked:
982; CHECK:       # %bb.0:
983; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
984; CHECK-NEXT:    vssub.vx v8, v8, a0
985; CHECK-NEXT:    ret
986  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
987  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
988  %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl)
989  ret <16 x i32> %v
990}
991
992define <16 x i32> @vssub_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
993; CHECK-LABEL: vssub_vi_v16i32:
994; CHECK:       # %bb.0:
995; CHECK-NEXT:    li a1, -1
996; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
997; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
998; CHECK-NEXT:    ret
999  %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl)
1000  ret <16 x i32> %v
1001}
1002
1003define <16 x i32> @vssub_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
1004; CHECK-LABEL: vssub_vi_v16i32_unmasked:
1005; CHECK:       # %bb.0:
1006; CHECK-NEXT:    li a1, -1
1007; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
1008; CHECK-NEXT:    vssub.vx v8, v8, a1
1009; CHECK-NEXT:    ret
1010  %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl)
1011  ret <16 x i32> %v
1012}
1013
1014declare <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64>, <2 x i64>, <2 x i1>, i32)
1015
1016define <2 x i64> @vssub_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {
1017; CHECK-LABEL: vssub_vv_v2i64:
1018; CHECK:       # %bb.0:
1019; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1020; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t
1021; CHECK-NEXT:    ret
1022  %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)
1023  ret <2 x i64> %v
1024}
1025
1026define <2 x i64> @vssub_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {
1027; CHECK-LABEL: vssub_vv_v2i64_unmasked:
1028; CHECK:       # %bb.0:
1029; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1030; CHECK-NEXT:    vssub.vv v8, v8, v9
1031; CHECK-NEXT:    ret
1032  %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)
1033  ret <2 x i64> %v
1034}
1035
1036define <2 x i64> @vssub_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
1037; RV32-LABEL: vssub_vx_v2i64:
1038; RV32:       # %bb.0:
1039; RV32-NEXT:    addi sp, sp, -16
1040; RV32-NEXT:    .cfi_def_cfa_offset 16
1041; RV32-NEXT:    sw a0, 8(sp)
1042; RV32-NEXT:    sw a1, 12(sp)
1043; RV32-NEXT:    addi a0, sp, 8
1044; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1045; RV32-NEXT:    vlse64.v v9, (a0), zero
1046; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
1047; RV32-NEXT:    vssub.vv v8, v8, v9, v0.t
1048; RV32-NEXT:    addi sp, sp, 16
1049; RV32-NEXT:    .cfi_def_cfa_offset 0
1050; RV32-NEXT:    ret
1051;
1052; RV64-LABEL: vssub_vx_v2i64:
1053; RV64:       # %bb.0:
1054; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
1055; RV64-NEXT:    vssub.vx v8, v8, a0, v0.t
1056; RV64-NEXT:    ret
1057  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
1058  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
1059  %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
1060  ret <2 x i64> %v
1061}
1062
1063define <2 x i64> @vssub_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
1064; RV32-LABEL: vssub_vx_v2i64_unmasked:
1065; RV32:       # %bb.0:
1066; RV32-NEXT:    addi sp, sp, -16
1067; RV32-NEXT:    .cfi_def_cfa_offset 16
1068; RV32-NEXT:    sw a0, 8(sp)
1069; RV32-NEXT:    sw a1, 12(sp)
1070; RV32-NEXT:    addi a0, sp, 8
1071; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1072; RV32-NEXT:    vlse64.v v9, (a0), zero
1073; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
1074; RV32-NEXT:    vssub.vv v8, v8, v9
1075; RV32-NEXT:    addi sp, sp, 16
1076; RV32-NEXT:    .cfi_def_cfa_offset 0
1077; RV32-NEXT:    ret
1078;
1079; RV64-LABEL: vssub_vx_v2i64_unmasked:
1080; RV64:       # %bb.0:
1081; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
1082; RV64-NEXT:    vssub.vx v8, v8, a0
1083; RV64-NEXT:    ret
1084  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
1085  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
1086  %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl)
1087  ret <2 x i64> %v
1088}
1089
1090define <2 x i64> @vssub_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
1091; CHECK-LABEL: vssub_vi_v2i64:
1092; CHECK:       # %bb.0:
1093; CHECK-NEXT:    li a1, -1
1094; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1095; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
1096; CHECK-NEXT:    ret
1097  %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl)
1098  ret <2 x i64> %v
1099}
1100
1101define <2 x i64> @vssub_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
1102; CHECK-LABEL: vssub_vi_v2i64_unmasked:
1103; CHECK:       # %bb.0:
1104; CHECK-NEXT:    li a1, -1
1105; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1106; CHECK-NEXT:    vssub.vx v8, v8, a1
1107; CHECK-NEXT:    ret
1108  %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl)
1109  ret <2 x i64> %v
1110}
1111
1112declare <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64>, <4 x i64>, <4 x i1>, i32)
1113
1114define <4 x i64> @vssub_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {
1115; CHECK-LABEL: vssub_vv_v4i64:
1116; CHECK:       # %bb.0:
1117; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1118; CHECK-NEXT:    vssub.vv v8, v8, v10, v0.t
1119; CHECK-NEXT:    ret
1120  %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)
1121  ret <4 x i64> %v
1122}
1123
1124define <4 x i64> @vssub_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {
1125; CHECK-LABEL: vssub_vv_v4i64_unmasked:
1126; CHECK:       # %bb.0:
1127; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1128; CHECK-NEXT:    vssub.vv v8, v8, v10
1129; CHECK-NEXT:    ret
1130  %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)
1131  ret <4 x i64> %v
1132}
1133
1134define <4 x i64> @vssub_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
1135; RV32-LABEL: vssub_vx_v4i64:
1136; RV32:       # %bb.0:
1137; RV32-NEXT:    addi sp, sp, -16
1138; RV32-NEXT:    .cfi_def_cfa_offset 16
1139; RV32-NEXT:    sw a0, 8(sp)
1140; RV32-NEXT:    sw a1, 12(sp)
1141; RV32-NEXT:    addi a0, sp, 8
1142; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1143; RV32-NEXT:    vlse64.v v10, (a0), zero
1144; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
1145; RV32-NEXT:    vssub.vv v8, v8, v10, v0.t
1146; RV32-NEXT:    addi sp, sp, 16
1147; RV32-NEXT:    .cfi_def_cfa_offset 0
1148; RV32-NEXT:    ret
1149;
1150; RV64-LABEL: vssub_vx_v4i64:
1151; RV64:       # %bb.0:
1152; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
1153; RV64-NEXT:    vssub.vx v8, v8, a0, v0.t
1154; RV64-NEXT:    ret
1155  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
1156  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
1157  %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
1158  ret <4 x i64> %v
1159}
1160
1161define <4 x i64> @vssub_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
1162; RV32-LABEL: vssub_vx_v4i64_unmasked:
1163; RV32:       # %bb.0:
1164; RV32-NEXT:    addi sp, sp, -16
1165; RV32-NEXT:    .cfi_def_cfa_offset 16
1166; RV32-NEXT:    sw a0, 8(sp)
1167; RV32-NEXT:    sw a1, 12(sp)
1168; RV32-NEXT:    addi a0, sp, 8
1169; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1170; RV32-NEXT:    vlse64.v v10, (a0), zero
1171; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
1172; RV32-NEXT:    vssub.vv v8, v8, v10
1173; RV32-NEXT:    addi sp, sp, 16
1174; RV32-NEXT:    .cfi_def_cfa_offset 0
1175; RV32-NEXT:    ret
1176;
1177; RV64-LABEL: vssub_vx_v4i64_unmasked:
1178; RV64:       # %bb.0:
1179; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
1180; RV64-NEXT:    vssub.vx v8, v8, a0
1181; RV64-NEXT:    ret
1182  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
1183  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
1184  %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl)
1185  ret <4 x i64> %v
1186}
1187
1188define <4 x i64> @vssub_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
1189; CHECK-LABEL: vssub_vi_v4i64:
1190; CHECK:       # %bb.0:
1191; CHECK-NEXT:    li a1, -1
1192; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1193; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
1194; CHECK-NEXT:    ret
1195  %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl)
1196  ret <4 x i64> %v
1197}
1198
1199define <4 x i64> @vssub_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
1200; CHECK-LABEL: vssub_vi_v4i64_unmasked:
1201; CHECK:       # %bb.0:
1202; CHECK-NEXT:    li a1, -1
1203; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1204; CHECK-NEXT:    vssub.vx v8, v8, a1
1205; CHECK-NEXT:    ret
1206  %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl)
1207  ret <4 x i64> %v
1208}
1209
1210declare <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64>, <8 x i64>, <8 x i1>, i32)
1211
1212define <8 x i64> @vssub_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {
1213; CHECK-LABEL: vssub_vv_v8i64:
1214; CHECK:       # %bb.0:
1215; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1216; CHECK-NEXT:    vssub.vv v8, v8, v12, v0.t
1217; CHECK-NEXT:    ret
1218  %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)
1219  ret <8 x i64> %v
1220}
1221
1222define <8 x i64> @vssub_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {
1223; CHECK-LABEL: vssub_vv_v8i64_unmasked:
1224; CHECK:       # %bb.0:
1225; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1226; CHECK-NEXT:    vssub.vv v8, v8, v12
1227; CHECK-NEXT:    ret
1228  %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)
1229  ret <8 x i64> %v
1230}
1231
1232define <8 x i64> @vssub_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
1233; RV32-LABEL: vssub_vx_v8i64:
1234; RV32:       # %bb.0:
1235; RV32-NEXT:    addi sp, sp, -16
1236; RV32-NEXT:    .cfi_def_cfa_offset 16
1237; RV32-NEXT:    sw a0, 8(sp)
1238; RV32-NEXT:    sw a1, 12(sp)
1239; RV32-NEXT:    addi a0, sp, 8
1240; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1241; RV32-NEXT:    vlse64.v v12, (a0), zero
1242; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
1243; RV32-NEXT:    vssub.vv v8, v8, v12, v0.t
1244; RV32-NEXT:    addi sp, sp, 16
1245; RV32-NEXT:    .cfi_def_cfa_offset 0
1246; RV32-NEXT:    ret
1247;
1248; RV64-LABEL: vssub_vx_v8i64:
1249; RV64:       # %bb.0:
1250; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
1251; RV64-NEXT:    vssub.vx v8, v8, a0, v0.t
1252; RV64-NEXT:    ret
1253  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
1254  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
1255  %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
1256  ret <8 x i64> %v
1257}
1258
1259define <8 x i64> @vssub_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
1260; RV32-LABEL: vssub_vx_v8i64_unmasked:
1261; RV32:       # %bb.0:
1262; RV32-NEXT:    addi sp, sp, -16
1263; RV32-NEXT:    .cfi_def_cfa_offset 16
1264; RV32-NEXT:    sw a0, 8(sp)
1265; RV32-NEXT:    sw a1, 12(sp)
1266; RV32-NEXT:    addi a0, sp, 8
1267; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1268; RV32-NEXT:    vlse64.v v12, (a0), zero
1269; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
1270; RV32-NEXT:    vssub.vv v8, v8, v12
1271; RV32-NEXT:    addi sp, sp, 16
1272; RV32-NEXT:    .cfi_def_cfa_offset 0
1273; RV32-NEXT:    ret
1274;
1275; RV64-LABEL: vssub_vx_v8i64_unmasked:
1276; RV64:       # %bb.0:
1277; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
1278; RV64-NEXT:    vssub.vx v8, v8, a0
1279; RV64-NEXT:    ret
1280  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
1281  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
1282  %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl)
1283  ret <8 x i64> %v
1284}
1285
1286define <8 x i64> @vssub_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
1287; CHECK-LABEL: vssub_vi_v8i64:
1288; CHECK:       # %bb.0:
1289; CHECK-NEXT:    li a1, -1
1290; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1291; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
1292; CHECK-NEXT:    ret
1293  %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl)
1294  ret <8 x i64> %v
1295}
1296
1297define <8 x i64> @vssub_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
1298; CHECK-LABEL: vssub_vi_v8i64_unmasked:
1299; CHECK:       # %bb.0:
1300; CHECK-NEXT:    li a1, -1
1301; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1302; CHECK-NEXT:    vssub.vx v8, v8, a1
1303; CHECK-NEXT:    ret
1304  %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl)
1305  ret <8 x i64> %v
1306}
1307
1308declare <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64>, <16 x i64>, <16 x i1>, i32)
1309
1310define <16 x i64> @vssub_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {
1311; CHECK-LABEL: vssub_vv_v16i64:
1312; CHECK:       # %bb.0:
1313; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1314; CHECK-NEXT:    vssub.vv v8, v8, v16, v0.t
1315; CHECK-NEXT:    ret
1316  %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)
1317  ret <16 x i64> %v
1318}
1319
1320define <16 x i64> @vssub_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {
1321; CHECK-LABEL: vssub_vv_v16i64_unmasked:
1322; CHECK:       # %bb.0:
1323; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1324; CHECK-NEXT:    vssub.vv v8, v8, v16
1325; CHECK-NEXT:    ret
1326  %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)
1327  ret <16 x i64> %v
1328}
1329
1330define <16 x i64> @vssub_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
1331; RV32-LABEL: vssub_vx_v16i64:
1332; RV32:       # %bb.0:
1333; RV32-NEXT:    addi sp, sp, -16
1334; RV32-NEXT:    .cfi_def_cfa_offset 16
1335; RV32-NEXT:    sw a0, 8(sp)
1336; RV32-NEXT:    sw a1, 12(sp)
1337; RV32-NEXT:    addi a0, sp, 8
1338; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
1339; RV32-NEXT:    vlse64.v v16, (a0), zero
1340; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
1341; RV32-NEXT:    vssub.vv v8, v8, v16, v0.t
1342; RV32-NEXT:    addi sp, sp, 16
1343; RV32-NEXT:    .cfi_def_cfa_offset 0
1344; RV32-NEXT:    ret
1345;
1346; RV64-LABEL: vssub_vx_v16i64:
1347; RV64:       # %bb.0:
1348; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1349; RV64-NEXT:    vssub.vx v8, v8, a0, v0.t
1350; RV64-NEXT:    ret
1351  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
1352  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
1353  %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
1354  ret <16 x i64> %v
1355}
1356
1357define <16 x i64> @vssub_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
1358; RV32-LABEL: vssub_vx_v16i64_unmasked:
1359; RV32:       # %bb.0:
1360; RV32-NEXT:    addi sp, sp, -16
1361; RV32-NEXT:    .cfi_def_cfa_offset 16
1362; RV32-NEXT:    sw a0, 8(sp)
1363; RV32-NEXT:    sw a1, 12(sp)
1364; RV32-NEXT:    addi a0, sp, 8
1365; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
1366; RV32-NEXT:    vlse64.v v16, (a0), zero
1367; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
1368; RV32-NEXT:    vssub.vv v8, v8, v16
1369; RV32-NEXT:    addi sp, sp, 16
1370; RV32-NEXT:    .cfi_def_cfa_offset 0
1371; RV32-NEXT:    ret
1372;
1373; RV64-LABEL: vssub_vx_v16i64_unmasked:
1374; RV64:       # %bb.0:
1375; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1376; RV64-NEXT:    vssub.vx v8, v8, a0
1377; RV64-NEXT:    ret
1378  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
1379  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
1380  %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl)
1381  ret <16 x i64> %v
1382}
1383
1384define <16 x i64> @vssub_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
1385; CHECK-LABEL: vssub_vi_v16i64:
1386; CHECK:       # %bb.0:
1387; CHECK-NEXT:    li a1, -1
1388; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1389; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t
1390; CHECK-NEXT:    ret
1391  %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl)
1392  ret <16 x i64> %v
1393}
1394
1395define <16 x i64> @vssub_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
1396; CHECK-LABEL: vssub_vi_v16i64_unmasked:
1397; CHECK:       # %bb.0:
1398; CHECK-NEXT:    li a1, -1
1399; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1400; CHECK-NEXT:    vssub.vx v8, v8, a1
1401; CHECK-NEXT:    ret
1402  %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl)
1403  ret <16 x i64> %v
1404}
1405
1406; Test that split-legalization works as expected.
1407
1408declare <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64>, <32 x i64>, <32 x i1>, i32)
1409
1410define <32 x i64> @vssub_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
1411; CHECK-LABEL: vssub_vx_v32i64:
1412; CHECK:       # %bb.0:
1413; CHECK-NEXT:    li a2, 16
1414; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
1415; CHECK-NEXT:    vslidedown.vi v24, v0, 2
1416; CHECK-NEXT:    mv a1, a0
1417; CHECK-NEXT:    bltu a0, a2, .LBB108_2
1418; CHECK-NEXT:  # %bb.1:
1419; CHECK-NEXT:    li a1, 16
1420; CHECK-NEXT:  .LBB108_2:
1421; CHECK-NEXT:    li a2, -1
1422; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1423; CHECK-NEXT:    vssub.vx v8, v8, a2, v0.t
1424; CHECK-NEXT:    addi a1, a0, -16
1425; CHECK-NEXT:    sltu a0, a0, a1
1426; CHECK-NEXT:    addi a0, a0, -1
1427; CHECK-NEXT:    and a0, a0, a1
1428; CHECK-NEXT:    vmv1r.v v0, v24
1429; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1430; CHECK-NEXT:    vssub.vx v16, v16, a2, v0.t
1431; CHECK-NEXT:    ret
1432  %v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)
1433  ret <32 x i64> %v
1434}
1435
1436define <32 x i64> @vssub_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
1437; CHECK-LABEL: vssub_vi_v32i64_unmasked:
1438; CHECK:       # %bb.0:
1439; CHECK-NEXT:    li a2, 16
1440; CHECK-NEXT:    mv a1, a0
1441; CHECK-NEXT:    bltu a0, a2, .LBB109_2
1442; CHECK-NEXT:  # %bb.1:
1443; CHECK-NEXT:    li a1, 16
1444; CHECK-NEXT:  .LBB109_2:
1445; CHECK-NEXT:    li a2, -1
1446; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1447; CHECK-NEXT:    vssub.vx v8, v8, a2
1448; CHECK-NEXT:    addi a1, a0, -16
1449; CHECK-NEXT:    sltu a0, a0, a1
1450; CHECK-NEXT:    addi a0, a0, -1
1451; CHECK-NEXT:    and a0, a0, a1
1452; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1453; CHECK-NEXT:    vssub.vx v16, v16, a2
1454; CHECK-NEXT:    ret
1455  %v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl)
1456  ret <32 x i64> %v
1457}
1458
1459define <32 x i64> @vssub_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
1460; CHECK-LABEL: vssub_vx_v32i64_evl12:
1461; CHECK:       # %bb.0:
1462; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
1463; CHECK-NEXT:    vslidedown.vi v24, v0, 2
1464; CHECK-NEXT:    li a0, -1
1465; CHECK-NEXT:    vsetivli zero, 12, e64, m8, ta, ma
1466; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
1467; CHECK-NEXT:    vmv1r.v v0, v24
1468; CHECK-NEXT:    vsetivli zero, 0, e64, m8, ta, ma
1469; CHECK-NEXT:    vssub.vx v16, v16, a0, v0.t
1470; CHECK-NEXT:    ret
1471  %v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12)
1472  ret <32 x i64> %v
1473}
1474
1475define <32 x i64> @vssub_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
1476; CHECK-LABEL: vssub_vx_v32i64_evl27:
1477; CHECK:       # %bb.0:
1478; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
1479; CHECK-NEXT:    vslidedown.vi v24, v0, 2
1480; CHECK-NEXT:    li a0, -1
1481; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
1482; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t
1483; CHECK-NEXT:    vmv1r.v v0, v24
1484; CHECK-NEXT:    vsetivli zero, 11, e64, m8, ta, ma
1485; CHECK-NEXT:    vssub.vx v16, v16, a0, v0.t
1486; CHECK-NEXT:    ret
1487  %v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 27)
1488  ret <32 x i64> %v
1489}
1490