xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp-bf16.ll (revision 9d068f7137a2ad732d008df46eb71aadb0cd8a8e) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+v,+m,+zvfbfmin -target-abi=ilp32d \
3; RUN:   -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+d,+v,+m,+zvfbfmin -target-abi=lp64d \
5; RUN:   -verify-machineinstrs < %s | FileCheck %s
6
7declare <2 x bfloat> @llvm.vp.select.v2bf16(<2 x i1>, <2 x bfloat>, <2 x bfloat>, i32)
8
9define <2 x bfloat> @select_v2bf16(<2 x i1> %a, <2 x bfloat> %b, <2 x bfloat> %c, i32 zeroext %evl) {
10; CHECK-LABEL: select_v2bf16:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
13; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
14; CHECK-NEXT:    ret
15  %v = call <2 x bfloat> @llvm.vp.select.v2bf16(<2 x i1> %a, <2 x bfloat> %b, <2 x bfloat> %c, i32 %evl)
16  ret <2 x bfloat> %v
17}
18
19declare <4 x bfloat> @llvm.vp.select.v4bf16(<4 x i1>, <4 x bfloat>, <4 x bfloat>, i32)
20
21define <4 x bfloat> @select_v4bf16(<4 x i1> %a, <4 x bfloat> %b, <4 x bfloat> %c, i32 zeroext %evl) {
22; CHECK-LABEL: select_v4bf16:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
25; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
26; CHECK-NEXT:    ret
27  %v = call <4 x bfloat> @llvm.vp.select.v4bf16(<4 x i1> %a, <4 x bfloat> %b, <4 x bfloat> %c, i32 %evl)
28  ret <4 x bfloat> %v
29}
30
31declare <8 x bfloat> @llvm.vp.select.v8bf16(<8 x i1>, <8 x bfloat>, <8 x bfloat>, i32)
32
33define <8 x bfloat> @select_v8bf16(<8 x i1> %a, <8 x bfloat> %b, <8 x bfloat> %c, i32 zeroext %evl) {
34; CHECK-LABEL: select_v8bf16:
35; CHECK:       # %bb.0:
36; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
37; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
38; CHECK-NEXT:    ret
39  %v = call <8 x bfloat> @llvm.vp.select.v8bf16(<8 x i1> %a, <8 x bfloat> %b, <8 x bfloat> %c, i32 %evl)
40  ret <8 x bfloat> %v
41}
42
43declare <16 x bfloat> @llvm.vp.select.v16bf16(<16 x i1>, <16 x bfloat>, <16 x bfloat>, i32)
44
45define <16 x bfloat> @select_v16bf16(<16 x i1> %a, <16 x bfloat> %b, <16 x bfloat> %c, i32 zeroext %evl) {
46; CHECK-LABEL: select_v16bf16:
47; CHECK:       # %bb.0:
48; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
49; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
50; CHECK-NEXT:    ret
51  %v = call <16 x bfloat> @llvm.vp.select.v16bf16(<16 x i1> %a, <16 x bfloat> %b, <16 x bfloat> %c, i32 %evl)
52  ret <16 x bfloat> %v
53}
54