xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64
6
7declare <8 x i7> @llvm.vp.uadd.sat.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32)
8
9define <8 x i7> @vsaddu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
10; CHECK-LABEL: vsaddu_vv_v8i7:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    li a1, 127
13; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
14; CHECK-NEXT:    vand.vx v9, v9, a1
15; CHECK-NEXT:    vand.vx v8, v8, a1
16; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
17; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t
18; CHECK-NEXT:    vminu.vx v8, v8, a1, v0.t
19; CHECK-NEXT:    ret
20  %v = call <8 x i7> @llvm.vp.uadd.sat.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
21  ret <8 x i7> %v
22}
23
24declare <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32)
25
26define <2 x i8> @vsaddu_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {
27; CHECK-LABEL: vsaddu_vv_v2i8:
28; CHECK:       # %bb.0:
29; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
30; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t
31; CHECK-NEXT:    ret
32  %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)
33  ret <2 x i8> %v
34}
35
36define <2 x i8> @vsaddu_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {
37; CHECK-LABEL: vsaddu_vv_v2i8_unmasked:
38; CHECK:       # %bb.0:
39; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
40; CHECK-NEXT:    vsaddu.vv v8, v8, v9
41; CHECK-NEXT:    ret
42  %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)
43  ret <2 x i8> %v
44}
45
46define <2 x i8> @vsaddu_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
47; CHECK-LABEL: vsaddu_vx_v2i8:
48; CHECK:       # %bb.0:
49; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
50; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t
51; CHECK-NEXT:    ret
52  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
53  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
54  %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)
55  ret <2 x i8> %v
56}
57
58define <2 x i8> @vsaddu_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
59; CHECK-LABEL: vsaddu_vx_v2i8_unmasked:
60; CHECK:       # %bb.0:
61; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
62; CHECK-NEXT:    vsaddu.vx v8, v8, a0
63; CHECK-NEXT:    ret
64  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
65  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
66  %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl)
67  ret <2 x i8> %v
68}
69
70define <2 x i8> @vsaddu_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
71; CHECK-LABEL: vsaddu_vi_v2i8:
72; CHECK:       # %bb.0:
73; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
74; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
75; CHECK-NEXT:    ret
76  %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl)
77  ret <2 x i8> %v
78}
79
80define <2 x i8> @vsaddu_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
81; CHECK-LABEL: vsaddu_vi_v2i8_unmasked:
82; CHECK:       # %bb.0:
83; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
84; CHECK-NEXT:    vsaddu.vi v8, v8, -1
85; CHECK-NEXT:    ret
86  %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl)
87  ret <2 x i8> %v
88}
89
90declare <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8>, <4 x i8>, <4 x i1>, i32)
91
92define <4 x i8> @vsaddu_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {
93; CHECK-LABEL: vsaddu_vv_v4i8:
94; CHECK:       # %bb.0:
95; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
96; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t
97; CHECK-NEXT:    ret
98  %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)
99  ret <4 x i8> %v
100}
101
102define <4 x i8> @vsaddu_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {
103; CHECK-LABEL: vsaddu_vv_v4i8_unmasked:
104; CHECK:       # %bb.0:
105; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
106; CHECK-NEXT:    vsaddu.vv v8, v8, v9
107; CHECK-NEXT:    ret
108  %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)
109  ret <4 x i8> %v
110}
111
112define <4 x i8> @vsaddu_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
113; CHECK-LABEL: vsaddu_vx_v4i8:
114; CHECK:       # %bb.0:
115; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
116; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t
117; CHECK-NEXT:    ret
118  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
119  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
120  %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)
121  ret <4 x i8> %v
122}
123
124define <4 x i8> @vsaddu_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
125; CHECK-LABEL: vsaddu_vx_v4i8_commute:
126; CHECK:       # %bb.0:
127; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
128; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t
129; CHECK-NEXT:    ret
130  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
131  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
132  %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl)
133  ret <4 x i8> %v
134}
135
136define <4 x i8> @vsaddu_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
137; CHECK-LABEL: vsaddu_vx_v4i8_unmasked:
138; CHECK:       # %bb.0:
139; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
140; CHECK-NEXT:    vsaddu.vx v8, v8, a0
141; CHECK-NEXT:    ret
142  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
143  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
144  %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl)
145  ret <4 x i8> %v
146}
147
148define <4 x i8> @vsaddu_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
149; CHECK-LABEL: vsaddu_vi_v4i8:
150; CHECK:       # %bb.0:
151; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
152; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
153; CHECK-NEXT:    ret
154  %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl)
155  ret <4 x i8> %v
156}
157
158define <4 x i8> @vsaddu_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
159; CHECK-LABEL: vsaddu_vi_v4i8_unmasked:
160; CHECK:       # %bb.0:
161; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
162; CHECK-NEXT:    vsaddu.vi v8, v8, -1
163; CHECK-NEXT:    ret
164  %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl)
165  ret <4 x i8> %v
166}
167
168declare <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8>, <5 x i8>, <5 x i1>, i32)
169
170define <5 x i8> @vsaddu_vv_v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 zeroext %evl) {
171; CHECK-LABEL: vsaddu_vv_v5i8:
172; CHECK:       # %bb.0:
173; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
174; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t
175; CHECK-NEXT:    ret
176  %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl)
177  ret <5 x i8> %v
178}
179
180define <5 x i8> @vsaddu_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %evl) {
181; CHECK-LABEL: vsaddu_vv_v5i8_unmasked:
182; CHECK:       # %bb.0:
183; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
184; CHECK-NEXT:    vsaddu.vv v8, v8, v9
185; CHECK-NEXT:    ret
186  %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl)
187  ret <5 x i8> %v
188}
189
190define <5 x i8> @vsaddu_vx_v5i8(<5 x i8> %va, i8 %b, <5 x i1> %m, i32 zeroext %evl) {
191; CHECK-LABEL: vsaddu_vx_v5i8:
192; CHECK:       # %bb.0:
193; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
194; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t
195; CHECK-NEXT:    ret
196  %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
197  %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer
198  %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl)
199  ret <5 x i8> %v
200}
201
202define <5 x i8> @vsaddu_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) {
203; CHECK-LABEL: vsaddu_vx_v5i8_unmasked:
204; CHECK:       # %bb.0:
205; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
206; CHECK-NEXT:    vsaddu.vx v8, v8, a0
207; CHECK-NEXT:    ret
208  %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
209  %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer
210  %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl)
211  ret <5 x i8> %v
212}
213
214define <5 x i8> @vsaddu_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) {
215; CHECK-LABEL: vsaddu_vi_v5i8:
216; CHECK:       # %bb.0:
217; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
218; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
219; CHECK-NEXT:    ret
220  %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> %m, i32 %evl)
221  ret <5 x i8> %v
222}
223
224define <5 x i8> @vsaddu_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) {
225; CHECK-LABEL: vsaddu_vi_v5i8_unmasked:
226; CHECK:       # %bb.0:
227; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
228; CHECK-NEXT:    vsaddu.vi v8, v8, -1
229; CHECK-NEXT:    ret
230  %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> splat (i1 true), i32 %evl)
231  ret <5 x i8> %v
232}
233
234declare <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8>, <8 x i8>, <8 x i1>, i32)
235
236define <8 x i8> @vsaddu_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {
237; CHECK-LABEL: vsaddu_vv_v8i8:
238; CHECK:       # %bb.0:
239; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
240; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t
241; CHECK-NEXT:    ret
242  %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)
243  ret <8 x i8> %v
244}
245
246define <8 x i8> @vsaddu_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {
247; CHECK-LABEL: vsaddu_vv_v8i8_unmasked:
248; CHECK:       # %bb.0:
249; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
250; CHECK-NEXT:    vsaddu.vv v8, v8, v9
251; CHECK-NEXT:    ret
252  %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)
253  ret <8 x i8> %v
254}
255
256define <8 x i8> @vsaddu_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {
257; CHECK-LABEL: vsaddu_vx_v8i8:
258; CHECK:       # %bb.0:
259; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
260; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t
261; CHECK-NEXT:    ret
262  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
263  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
264  %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)
265  ret <8 x i8> %v
266}
267
268define <8 x i8> @vsaddu_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
269; CHECK-LABEL: vsaddu_vx_v8i8_unmasked:
270; CHECK:       # %bb.0:
271; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
272; CHECK-NEXT:    vsaddu.vx v8, v8, a0
273; CHECK-NEXT:    ret
274  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
275  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
276  %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl)
277  ret <8 x i8> %v
278}
279
280define <8 x i8> @vsaddu_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
281; CHECK-LABEL: vsaddu_vi_v8i8:
282; CHECK:       # %bb.0:
283; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
284; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
285; CHECK-NEXT:    ret
286  %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl)
287  ret <8 x i8> %v
288}
289
290define <8 x i8> @vsaddu_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
291; CHECK-LABEL: vsaddu_vi_v8i8_unmasked:
292; CHECK:       # %bb.0:
293; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
294; CHECK-NEXT:    vsaddu.vi v8, v8, -1
295; CHECK-NEXT:    ret
296  %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl)
297  ret <8 x i8> %v
298}
299
300declare <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8>, <16 x i8>, <16 x i1>, i32)
301
302define <16 x i8> @vsaddu_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {
303; CHECK-LABEL: vsaddu_vv_v16i8:
304; CHECK:       # %bb.0:
305; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
306; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t
307; CHECK-NEXT:    ret
308  %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)
309  ret <16 x i8> %v
310}
311
312define <16 x i8> @vsaddu_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {
313; CHECK-LABEL: vsaddu_vv_v16i8_unmasked:
314; CHECK:       # %bb.0:
315; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
316; CHECK-NEXT:    vsaddu.vv v8, v8, v9
317; CHECK-NEXT:    ret
318  %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)
319  ret <16 x i8> %v
320}
321
322define <16 x i8> @vsaddu_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {
323; CHECK-LABEL: vsaddu_vx_v16i8:
324; CHECK:       # %bb.0:
325; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
326; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t
327; CHECK-NEXT:    ret
328  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
329  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
330  %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)
331  ret <16 x i8> %v
332}
333
334define <16 x i8> @vsaddu_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {
335; CHECK-LABEL: vsaddu_vx_v16i8_unmasked:
336; CHECK:       # %bb.0:
337; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
338; CHECK-NEXT:    vsaddu.vx v8, v8, a0
339; CHECK-NEXT:    ret
340  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
341  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
342  %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl)
343  ret <16 x i8> %v
344}
345
346define <16 x i8> @vsaddu_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
347; CHECK-LABEL: vsaddu_vi_v16i8:
348; CHECK:       # %bb.0:
349; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
350; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
351; CHECK-NEXT:    ret
352  %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl)
353  ret <16 x i8> %v
354}
355
356define <16 x i8> @vsaddu_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
357; CHECK-LABEL: vsaddu_vi_v16i8_unmasked:
358; CHECK:       # %bb.0:
359; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
360; CHECK-NEXT:    vsaddu.vi v8, v8, -1
361; CHECK-NEXT:    ret
362  %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl)
363  ret <16 x i8> %v
364}
365
366declare <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8>, <256 x i8>, <256 x i1>, i32)
367
368define <256 x i8> @vsaddu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %evl) {
369; CHECK-LABEL: vsaddu_vi_v258i8:
370; CHECK:       # %bb.0:
371; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
372; CHECK-NEXT:    vmv1r.v v24, v0
373; CHECK-NEXT:    li a2, 128
374; CHECK-NEXT:    vsetvli zero, a2, e8, m8, ta, ma
375; CHECK-NEXT:    vlm.v v0, (a0)
376; CHECK-NEXT:    addi a0, a1, -128
377; CHECK-NEXT:    sltu a3, a1, a0
378; CHECK-NEXT:    addi a3, a3, -1
379; CHECK-NEXT:    and a0, a3, a0
380; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
381; CHECK-NEXT:    vsaddu.vi v16, v16, -1, v0.t
382; CHECK-NEXT:    bltu a1, a2, .LBB32_2
383; CHECK-NEXT:  # %bb.1:
384; CHECK-NEXT:    li a1, 128
385; CHECK-NEXT:  .LBB32_2:
386; CHECK-NEXT:    vmv1r.v v0, v24
387; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
388; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
389; CHECK-NEXT:    ret
390  %v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 %evl)
391  ret <256 x i8> %v
392}
393
394define <256 x i8> @vsaddu_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) {
395; CHECK-LABEL: vsaddu_vi_v258i8_unmasked:
396; CHECK:       # %bb.0:
397; CHECK-NEXT:    li a2, 128
398; CHECK-NEXT:    mv a1, a0
399; CHECK-NEXT:    bltu a0, a2, .LBB33_2
400; CHECK-NEXT:  # %bb.1:
401; CHECK-NEXT:    li a1, 128
402; CHECK-NEXT:  .LBB33_2:
403; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
404; CHECK-NEXT:    vsaddu.vi v8, v8, -1
405; CHECK-NEXT:    addi a1, a0, -128
406; CHECK-NEXT:    sltu a0, a0, a1
407; CHECK-NEXT:    addi a0, a0, -1
408; CHECK-NEXT:    and a0, a0, a1
409; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
410; CHECK-NEXT:    vsaddu.vi v16, v16, -1
411; CHECK-NEXT:    ret
412  %v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> splat (i1 true), i32 %evl)
413  ret <256 x i8> %v
414}
415
416; Test splitting when the %evl is a known constant.
417
418define <256 x i8> @vsaddu_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
419; CHECK-LABEL: vsaddu_vi_v258i8_evl129:
420; CHECK:       # %bb.0:
421; CHECK-NEXT:    li a1, 128
422; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
423; CHECK-NEXT:    vlm.v v24, (a0)
424; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
425; CHECK-NEXT:    vmv1r.v v0, v24
426; CHECK-NEXT:    vsetivli zero, 1, e8, m8, ta, ma
427; CHECK-NEXT:    vsaddu.vi v16, v16, -1, v0.t
428; CHECK-NEXT:    ret
429  %v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 129)
430  ret <256 x i8> %v
431}
432
433; FIXME: The upper half is doing nothing.
434
435define <256 x i8> @vsaddu_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
436; CHECK-LABEL: vsaddu_vi_v258i8_evl128:
437; CHECK:       # %bb.0:
438; CHECK-NEXT:    li a1, 128
439; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
440; CHECK-NEXT:    vlm.v v24, (a0)
441; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
442; CHECK-NEXT:    vmv1r.v v0, v24
443; CHECK-NEXT:    vsetivli zero, 0, e8, m8, ta, ma
444; CHECK-NEXT:    vsaddu.vi v16, v16, -1, v0.t
445; CHECK-NEXT:    ret
446  %v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)
447  ret <256 x i8> %v
448}
449
450declare <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16>, <2 x i16>, <2 x i1>, i32)
451
452define <2 x i16> @vsaddu_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {
453; CHECK-LABEL: vsaddu_vv_v2i16:
454; CHECK:       # %bb.0:
455; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
456; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t
457; CHECK-NEXT:    ret
458  %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)
459  ret <2 x i16> %v
460}
461
462define <2 x i16> @vsaddu_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {
463; CHECK-LABEL: vsaddu_vv_v2i16_unmasked:
464; CHECK:       # %bb.0:
465; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
466; CHECK-NEXT:    vsaddu.vv v8, v8, v9
467; CHECK-NEXT:    ret
468  %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)
469  ret <2 x i16> %v
470}
471
472define <2 x i16> @vsaddu_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {
473; CHECK-LABEL: vsaddu_vx_v2i16:
474; CHECK:       # %bb.0:
475; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
476; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t
477; CHECK-NEXT:    ret
478  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
479  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
480  %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)
481  ret <2 x i16> %v
482}
483
484define <2 x i16> @vsaddu_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {
485; CHECK-LABEL: vsaddu_vx_v2i16_unmasked:
486; CHECK:       # %bb.0:
487; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
488; CHECK-NEXT:    vsaddu.vx v8, v8, a0
489; CHECK-NEXT:    ret
490  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
491  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
492  %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl)
493  ret <2 x i16> %v
494}
495
496define <2 x i16> @vsaddu_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
497; CHECK-LABEL: vsaddu_vi_v2i16:
498; CHECK:       # %bb.0:
499; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
500; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
501; CHECK-NEXT:    ret
502  %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl)
503  ret <2 x i16> %v
504}
505
506define <2 x i16> @vsaddu_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
507; CHECK-LABEL: vsaddu_vi_v2i16_unmasked:
508; CHECK:       # %bb.0:
509; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
510; CHECK-NEXT:    vsaddu.vi v8, v8, -1
511; CHECK-NEXT:    ret
512  %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl)
513  ret <2 x i16> %v
514}
515
516declare <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16>, <4 x i16>, <4 x i1>, i32)
517
518define <4 x i16> @vsaddu_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {
519; CHECK-LABEL: vsaddu_vv_v4i16:
520; CHECK:       # %bb.0:
521; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
522; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t
523; CHECK-NEXT:    ret
524  %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)
525  ret <4 x i16> %v
526}
527
528define <4 x i16> @vsaddu_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {
529; CHECK-LABEL: vsaddu_vv_v4i16_unmasked:
530; CHECK:       # %bb.0:
531; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
532; CHECK-NEXT:    vsaddu.vv v8, v8, v9
533; CHECK-NEXT:    ret
534  %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)
535  ret <4 x i16> %v
536}
537
538define <4 x i16> @vsaddu_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {
539; CHECK-LABEL: vsaddu_vx_v4i16:
540; CHECK:       # %bb.0:
541; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
542; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t
543; CHECK-NEXT:    ret
544  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
545  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
546  %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)
547  ret <4 x i16> %v
548}
549
550define <4 x i16> @vsaddu_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {
551; CHECK-LABEL: vsaddu_vx_v4i16_unmasked:
552; CHECK:       # %bb.0:
553; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
554; CHECK-NEXT:    vsaddu.vx v8, v8, a0
555; CHECK-NEXT:    ret
556  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
557  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
558  %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl)
559  ret <4 x i16> %v
560}
561
562define <4 x i16> @vsaddu_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
563; CHECK-LABEL: vsaddu_vi_v4i16:
564; CHECK:       # %bb.0:
565; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
566; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
567; CHECK-NEXT:    ret
568  %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl)
569  ret <4 x i16> %v
570}
571
572define <4 x i16> @vsaddu_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
573; CHECK-LABEL: vsaddu_vi_v4i16_unmasked:
574; CHECK:       # %bb.0:
575; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
576; CHECK-NEXT:    vsaddu.vi v8, v8, -1
577; CHECK-NEXT:    ret
578  %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl)
579  ret <4 x i16> %v
580}
581
582declare <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16>, <8 x i16>, <8 x i1>, i32)
583
584define <8 x i16> @vsaddu_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {
585; CHECK-LABEL: vsaddu_vv_v8i16:
586; CHECK:       # %bb.0:
587; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
588; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t
589; CHECK-NEXT:    ret
590  %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)
591  ret <8 x i16> %v
592}
593
594define <8 x i16> @vsaddu_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {
595; CHECK-LABEL: vsaddu_vv_v8i16_unmasked:
596; CHECK:       # %bb.0:
597; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
598; CHECK-NEXT:    vsaddu.vv v8, v8, v9
599; CHECK-NEXT:    ret
600  %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)
601  ret <8 x i16> %v
602}
603
604define <8 x i16> @vsaddu_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {
605; CHECK-LABEL: vsaddu_vx_v8i16:
606; CHECK:       # %bb.0:
607; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
608; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t
609; CHECK-NEXT:    ret
610  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
611  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
612  %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)
613  ret <8 x i16> %v
614}
615
616define <8 x i16> @vsaddu_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {
617; CHECK-LABEL: vsaddu_vx_v8i16_unmasked:
618; CHECK:       # %bb.0:
619; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
620; CHECK-NEXT:    vsaddu.vx v8, v8, a0
621; CHECK-NEXT:    ret
622  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
623  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
624  %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl)
625  ret <8 x i16> %v
626}
627
628define <8 x i16> @vsaddu_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
629; CHECK-LABEL: vsaddu_vi_v8i16:
630; CHECK:       # %bb.0:
631; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
632; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
633; CHECK-NEXT:    ret
634  %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl)
635  ret <8 x i16> %v
636}
637
638define <8 x i16> @vsaddu_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
639; CHECK-LABEL: vsaddu_vi_v8i16_unmasked:
640; CHECK:       # %bb.0:
641; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
642; CHECK-NEXT:    vsaddu.vi v8, v8, -1
643; CHECK-NEXT:    ret
644  %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl)
645  ret <8 x i16> %v
646}
647
648declare <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16>, <16 x i16>, <16 x i1>, i32)
649
650define <16 x i16> @vsaddu_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {
651; CHECK-LABEL: vsaddu_vv_v16i16:
652; CHECK:       # %bb.0:
653; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
654; CHECK-NEXT:    vsaddu.vv v8, v8, v10, v0.t
655; CHECK-NEXT:    ret
656  %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)
657  ret <16 x i16> %v
658}
659
660define <16 x i16> @vsaddu_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {
661; CHECK-LABEL: vsaddu_vv_v16i16_unmasked:
662; CHECK:       # %bb.0:
663; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
664; CHECK-NEXT:    vsaddu.vv v8, v8, v10
665; CHECK-NEXT:    ret
666  %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)
667  ret <16 x i16> %v
668}
669
670define <16 x i16> @vsaddu_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {
671; CHECK-LABEL: vsaddu_vx_v16i16:
672; CHECK:       # %bb.0:
673; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
674; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t
675; CHECK-NEXT:    ret
676  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
677  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
678  %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)
679  ret <16 x i16> %v
680}
681
682define <16 x i16> @vsaddu_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {
683; CHECK-LABEL: vsaddu_vx_v16i16_unmasked:
684; CHECK:       # %bb.0:
685; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
686; CHECK-NEXT:    vsaddu.vx v8, v8, a0
687; CHECK-NEXT:    ret
688  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
689  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
690  %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl)
691  ret <16 x i16> %v
692}
693
694define <16 x i16> @vsaddu_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
695; CHECK-LABEL: vsaddu_vi_v16i16:
696; CHECK:       # %bb.0:
697; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
698; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
699; CHECK-NEXT:    ret
700  %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl)
701  ret <16 x i16> %v
702}
703
704define <16 x i16> @vsaddu_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
705; CHECK-LABEL: vsaddu_vi_v16i16_unmasked:
706; CHECK:       # %bb.0:
707; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
708; CHECK-NEXT:    vsaddu.vi v8, v8, -1
709; CHECK-NEXT:    ret
710  %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl)
711  ret <16 x i16> %v
712}
713
714declare <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32)
715
716define <2 x i32> @vsaddu_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {
717; CHECK-LABEL: vsaddu_vv_v2i32:
718; CHECK:       # %bb.0:
719; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
720; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t
721; CHECK-NEXT:    ret
722  %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)
723  ret <2 x i32> %v
724}
725
726define <2 x i32> @vsaddu_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {
727; CHECK-LABEL: vsaddu_vv_v2i32_unmasked:
728; CHECK:       # %bb.0:
729; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
730; CHECK-NEXT:    vsaddu.vv v8, v8, v9
731; CHECK-NEXT:    ret
732  %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)
733  ret <2 x i32> %v
734}
735
736define <2 x i32> @vsaddu_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {
737; CHECK-LABEL: vsaddu_vx_v2i32:
738; CHECK:       # %bb.0:
739; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
740; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t
741; CHECK-NEXT:    ret
742  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
743  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
744  %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)
745  ret <2 x i32> %v
746}
747
748define <2 x i32> @vsaddu_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {
749; CHECK-LABEL: vsaddu_vx_v2i32_unmasked:
750; CHECK:       # %bb.0:
751; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
752; CHECK-NEXT:    vsaddu.vx v8, v8, a0
753; CHECK-NEXT:    ret
754  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
755  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
756  %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl)
757  ret <2 x i32> %v
758}
759
760define <2 x i32> @vsaddu_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
761; CHECK-LABEL: vsaddu_vi_v2i32:
762; CHECK:       # %bb.0:
763; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
764; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
765; CHECK-NEXT:    ret
766  %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl)
767  ret <2 x i32> %v
768}
769
770define <2 x i32> @vsaddu_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
771; CHECK-LABEL: vsaddu_vi_v2i32_unmasked:
772; CHECK:       # %bb.0:
773; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
774; CHECK-NEXT:    vsaddu.vi v8, v8, -1
775; CHECK-NEXT:    ret
776  %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl)
777  ret <2 x i32> %v
778}
779
780declare <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
781
782define <4 x i32> @vsaddu_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {
783; CHECK-LABEL: vsaddu_vv_v4i32:
784; CHECK:       # %bb.0:
785; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
786; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t
787; CHECK-NEXT:    ret
788  %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)
789  ret <4 x i32> %v
790}
791
792define <4 x i32> @vsaddu_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {
793; CHECK-LABEL: vsaddu_vv_v4i32_unmasked:
794; CHECK:       # %bb.0:
795; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
796; CHECK-NEXT:    vsaddu.vv v8, v8, v9
797; CHECK-NEXT:    ret
798  %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)
799  ret <4 x i32> %v
800}
801
802define <4 x i32> @vsaddu_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {
803; CHECK-LABEL: vsaddu_vx_v4i32:
804; CHECK:       # %bb.0:
805; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
806; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t
807; CHECK-NEXT:    ret
808  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
809  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
810  %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)
811  ret <4 x i32> %v
812}
813
814define <4 x i32> @vsaddu_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {
815; CHECK-LABEL: vsaddu_vx_v4i32_unmasked:
816; CHECK:       # %bb.0:
817; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
818; CHECK-NEXT:    vsaddu.vx v8, v8, a0
819; CHECK-NEXT:    ret
820  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
821  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
822  %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl)
823  ret <4 x i32> %v
824}
825
826define <4 x i32> @vsaddu_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
827; CHECK-LABEL: vsaddu_vi_v4i32:
828; CHECK:       # %bb.0:
829; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
830; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
831; CHECK-NEXT:    ret
832  %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl)
833  ret <4 x i32> %v
834}
835
836define <4 x i32> @vsaddu_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
837; CHECK-LABEL: vsaddu_vi_v4i32_unmasked:
838; CHECK:       # %bb.0:
839; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
840; CHECK-NEXT:    vsaddu.vi v8, v8, -1
841; CHECK-NEXT:    ret
842  %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl)
843  ret <4 x i32> %v
844}
845
846declare <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
847
848define <8 x i32> @vsaddu_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {
849; CHECK-LABEL: vsaddu_vv_v8i32:
850; CHECK:       # %bb.0:
851; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
852; CHECK-NEXT:    vsaddu.vv v8, v8, v10, v0.t
853; CHECK-NEXT:    ret
854  %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)
855  ret <8 x i32> %v
856}
857
858define <8 x i32> @vsaddu_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {
859; CHECK-LABEL: vsaddu_vv_v8i32_unmasked:
860; CHECK:       # %bb.0:
861; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
862; CHECK-NEXT:    vsaddu.vv v8, v8, v10
863; CHECK-NEXT:    ret
864  %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)
865  ret <8 x i32> %v
866}
867
868define <8 x i32> @vsaddu_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {
869; CHECK-LABEL: vsaddu_vx_v8i32:
870; CHECK:       # %bb.0:
871; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
872; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t
873; CHECK-NEXT:    ret
874  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
875  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
876  %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)
877  ret <8 x i32> %v
878}
879
880define <8 x i32> @vsaddu_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {
881; CHECK-LABEL: vsaddu_vx_v8i32_unmasked:
882; CHECK:       # %bb.0:
883; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
884; CHECK-NEXT:    vsaddu.vx v8, v8, a0
885; CHECK-NEXT:    ret
886  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
887  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
888  %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl)
889  ret <8 x i32> %v
890}
891
892define <8 x i32> @vsaddu_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
893; CHECK-LABEL: vsaddu_vi_v8i32:
894; CHECK:       # %bb.0:
895; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
896; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
897; CHECK-NEXT:    ret
898  %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl)
899  ret <8 x i32> %v
900}
901
902define <8 x i32> @vsaddu_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
903; CHECK-LABEL: vsaddu_vi_v8i32_unmasked:
904; CHECK:       # %bb.0:
905; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
906; CHECK-NEXT:    vsaddu.vi v8, v8, -1
907; CHECK-NEXT:    ret
908  %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl)
909  ret <8 x i32> %v
910}
911
912declare <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32>, <16 x i32>, <16 x i1>, i32)
913
914define <16 x i32> @vsaddu_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {
915; CHECK-LABEL: vsaddu_vv_v16i32:
916; CHECK:       # %bb.0:
917; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
918; CHECK-NEXT:    vsaddu.vv v8, v8, v12, v0.t
919; CHECK-NEXT:    ret
920  %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)
921  ret <16 x i32> %v
922}
923
924define <16 x i32> @vsaddu_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {
925; CHECK-LABEL: vsaddu_vv_v16i32_unmasked:
926; CHECK:       # %bb.0:
927; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
928; CHECK-NEXT:    vsaddu.vv v8, v8, v12
929; CHECK-NEXT:    ret
930  %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)
931  ret <16 x i32> %v
932}
933
934define <16 x i32> @vsaddu_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {
935; CHECK-LABEL: vsaddu_vx_v16i32:
936; CHECK:       # %bb.0:
937; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
938; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t
939; CHECK-NEXT:    ret
940  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
941  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
942  %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)
943  ret <16 x i32> %v
944}
945
946define <16 x i32> @vsaddu_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {
947; CHECK-LABEL: vsaddu_vx_v16i32_unmasked:
948; CHECK:       # %bb.0:
949; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
950; CHECK-NEXT:    vsaddu.vx v8, v8, a0
951; CHECK-NEXT:    ret
952  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
953  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
954  %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl)
955  ret <16 x i32> %v
956}
957
958define <16 x i32> @vsaddu_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
959; CHECK-LABEL: vsaddu_vi_v16i32:
960; CHECK:       # %bb.0:
961; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
962; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
963; CHECK-NEXT:    ret
964  %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl)
965  ret <16 x i32> %v
966}
967
968define <16 x i32> @vsaddu_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
969; CHECK-LABEL: vsaddu_vi_v16i32_unmasked:
970; CHECK:       # %bb.0:
971; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
972; CHECK-NEXT:    vsaddu.vi v8, v8, -1
973; CHECK-NEXT:    ret
974  %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl)
975  ret <16 x i32> %v
976}
977
978declare <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64>, <2 x i64>, <2 x i1>, i32)
979
980define <2 x i64> @vsaddu_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {
981; CHECK-LABEL: vsaddu_vv_v2i64:
982; CHECK:       # %bb.0:
983; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
984; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t
985; CHECK-NEXT:    ret
986  %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)
987  ret <2 x i64> %v
988}
989
990define <2 x i64> @vsaddu_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {
991; CHECK-LABEL: vsaddu_vv_v2i64_unmasked:
992; CHECK:       # %bb.0:
993; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
994; CHECK-NEXT:    vsaddu.vv v8, v8, v9
995; CHECK-NEXT:    ret
996  %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)
997  ret <2 x i64> %v
998}
999
1000define <2 x i64> @vsaddu_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
1001; RV32-LABEL: vsaddu_vx_v2i64:
1002; RV32:       # %bb.0:
1003; RV32-NEXT:    addi sp, sp, -16
1004; RV32-NEXT:    .cfi_def_cfa_offset 16
1005; RV32-NEXT:    sw a0, 8(sp)
1006; RV32-NEXT:    sw a1, 12(sp)
1007; RV32-NEXT:    addi a0, sp, 8
1008; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1009; RV32-NEXT:    vlse64.v v9, (a0), zero
1010; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
1011; RV32-NEXT:    vsaddu.vv v8, v8, v9, v0.t
1012; RV32-NEXT:    addi sp, sp, 16
1013; RV32-NEXT:    .cfi_def_cfa_offset 0
1014; RV32-NEXT:    ret
1015;
1016; RV64-LABEL: vsaddu_vx_v2i64:
1017; RV64:       # %bb.0:
1018; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
1019; RV64-NEXT:    vsaddu.vx v8, v8, a0, v0.t
1020; RV64-NEXT:    ret
1021  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
1022  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
1023  %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
1024  ret <2 x i64> %v
1025}
1026
1027define <2 x i64> @vsaddu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
1028; RV32-LABEL: vsaddu_vx_v2i64_unmasked:
1029; RV32:       # %bb.0:
1030; RV32-NEXT:    addi sp, sp, -16
1031; RV32-NEXT:    .cfi_def_cfa_offset 16
1032; RV32-NEXT:    sw a0, 8(sp)
1033; RV32-NEXT:    sw a1, 12(sp)
1034; RV32-NEXT:    addi a0, sp, 8
1035; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
1036; RV32-NEXT:    vlse64.v v9, (a0), zero
1037; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
1038; RV32-NEXT:    vsaddu.vv v8, v8, v9
1039; RV32-NEXT:    addi sp, sp, 16
1040; RV32-NEXT:    .cfi_def_cfa_offset 0
1041; RV32-NEXT:    ret
1042;
1043; RV64-LABEL: vsaddu_vx_v2i64_unmasked:
1044; RV64:       # %bb.0:
1045; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
1046; RV64-NEXT:    vsaddu.vx v8, v8, a0
1047; RV64-NEXT:    ret
1048  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
1049  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
1050  %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl)
1051  ret <2 x i64> %v
1052}
1053
1054define <2 x i64> @vsaddu_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
1055; CHECK-LABEL: vsaddu_vi_v2i64:
1056; CHECK:       # %bb.0:
1057; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1058; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
1059; CHECK-NEXT:    ret
1060  %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl)
1061  ret <2 x i64> %v
1062}
1063
1064define <2 x i64> @vsaddu_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
1065; CHECK-LABEL: vsaddu_vi_v2i64_unmasked:
1066; CHECK:       # %bb.0:
1067; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
1068; CHECK-NEXT:    vsaddu.vi v8, v8, -1
1069; CHECK-NEXT:    ret
1070  %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl)
1071  ret <2 x i64> %v
1072}
1073
1074declare <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64>, <4 x i64>, <4 x i1>, i32)
1075
1076define <4 x i64> @vsaddu_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {
1077; CHECK-LABEL: vsaddu_vv_v4i64:
1078; CHECK:       # %bb.0:
1079; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1080; CHECK-NEXT:    vsaddu.vv v8, v8, v10, v0.t
1081; CHECK-NEXT:    ret
1082  %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)
1083  ret <4 x i64> %v
1084}
1085
1086define <4 x i64> @vsaddu_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {
1087; CHECK-LABEL: vsaddu_vv_v4i64_unmasked:
1088; CHECK:       # %bb.0:
1089; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1090; CHECK-NEXT:    vsaddu.vv v8, v8, v10
1091; CHECK-NEXT:    ret
1092  %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)
1093  ret <4 x i64> %v
1094}
1095
1096define <4 x i64> @vsaddu_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
1097; RV32-LABEL: vsaddu_vx_v4i64:
1098; RV32:       # %bb.0:
1099; RV32-NEXT:    addi sp, sp, -16
1100; RV32-NEXT:    .cfi_def_cfa_offset 16
1101; RV32-NEXT:    sw a0, 8(sp)
1102; RV32-NEXT:    sw a1, 12(sp)
1103; RV32-NEXT:    addi a0, sp, 8
1104; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1105; RV32-NEXT:    vlse64.v v10, (a0), zero
1106; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
1107; RV32-NEXT:    vsaddu.vv v8, v8, v10, v0.t
1108; RV32-NEXT:    addi sp, sp, 16
1109; RV32-NEXT:    .cfi_def_cfa_offset 0
1110; RV32-NEXT:    ret
1111;
1112; RV64-LABEL: vsaddu_vx_v4i64:
1113; RV64:       # %bb.0:
1114; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
1115; RV64-NEXT:    vsaddu.vx v8, v8, a0, v0.t
1116; RV64-NEXT:    ret
1117  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
1118  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
1119  %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
1120  ret <4 x i64> %v
1121}
1122
1123define <4 x i64> @vsaddu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
1124; RV32-LABEL: vsaddu_vx_v4i64_unmasked:
1125; RV32:       # %bb.0:
1126; RV32-NEXT:    addi sp, sp, -16
1127; RV32-NEXT:    .cfi_def_cfa_offset 16
1128; RV32-NEXT:    sw a0, 8(sp)
1129; RV32-NEXT:    sw a1, 12(sp)
1130; RV32-NEXT:    addi a0, sp, 8
1131; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1132; RV32-NEXT:    vlse64.v v10, (a0), zero
1133; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
1134; RV32-NEXT:    vsaddu.vv v8, v8, v10
1135; RV32-NEXT:    addi sp, sp, 16
1136; RV32-NEXT:    .cfi_def_cfa_offset 0
1137; RV32-NEXT:    ret
1138;
1139; RV64-LABEL: vsaddu_vx_v4i64_unmasked:
1140; RV64:       # %bb.0:
1141; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
1142; RV64-NEXT:    vsaddu.vx v8, v8, a0
1143; RV64-NEXT:    ret
1144  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
1145  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
1146  %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl)
1147  ret <4 x i64> %v
1148}
1149
1150define <4 x i64> @vsaddu_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
1151; CHECK-LABEL: vsaddu_vi_v4i64:
1152; CHECK:       # %bb.0:
1153; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1154; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
1155; CHECK-NEXT:    ret
1156  %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl)
1157  ret <4 x i64> %v
1158}
1159
1160define <4 x i64> @vsaddu_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
1161; CHECK-LABEL: vsaddu_vi_v4i64_unmasked:
1162; CHECK:       # %bb.0:
1163; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1164; CHECK-NEXT:    vsaddu.vi v8, v8, -1
1165; CHECK-NEXT:    ret
1166  %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl)
1167  ret <4 x i64> %v
1168}
1169
1170declare <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64>, <8 x i64>, <8 x i1>, i32)
1171
1172define <8 x i64> @vsaddu_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {
1173; CHECK-LABEL: vsaddu_vv_v8i64:
1174; CHECK:       # %bb.0:
1175; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1176; CHECK-NEXT:    vsaddu.vv v8, v8, v12, v0.t
1177; CHECK-NEXT:    ret
1178  %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)
1179  ret <8 x i64> %v
1180}
1181
1182define <8 x i64> @vsaddu_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {
1183; CHECK-LABEL: vsaddu_vv_v8i64_unmasked:
1184; CHECK:       # %bb.0:
1185; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1186; CHECK-NEXT:    vsaddu.vv v8, v8, v12
1187; CHECK-NEXT:    ret
1188  %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)
1189  ret <8 x i64> %v
1190}
1191
1192define <8 x i64> @vsaddu_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
1193; RV32-LABEL: vsaddu_vx_v8i64:
1194; RV32:       # %bb.0:
1195; RV32-NEXT:    addi sp, sp, -16
1196; RV32-NEXT:    .cfi_def_cfa_offset 16
1197; RV32-NEXT:    sw a0, 8(sp)
1198; RV32-NEXT:    sw a1, 12(sp)
1199; RV32-NEXT:    addi a0, sp, 8
1200; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1201; RV32-NEXT:    vlse64.v v12, (a0), zero
1202; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
1203; RV32-NEXT:    vsaddu.vv v8, v8, v12, v0.t
1204; RV32-NEXT:    addi sp, sp, 16
1205; RV32-NEXT:    .cfi_def_cfa_offset 0
1206; RV32-NEXT:    ret
1207;
1208; RV64-LABEL: vsaddu_vx_v8i64:
1209; RV64:       # %bb.0:
1210; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
1211; RV64-NEXT:    vsaddu.vx v8, v8, a0, v0.t
1212; RV64-NEXT:    ret
1213  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
1214  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
1215  %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
1216  ret <8 x i64> %v
1217}
1218
1219define <8 x i64> @vsaddu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
1220; RV32-LABEL: vsaddu_vx_v8i64_unmasked:
1221; RV32:       # %bb.0:
1222; RV32-NEXT:    addi sp, sp, -16
1223; RV32-NEXT:    .cfi_def_cfa_offset 16
1224; RV32-NEXT:    sw a0, 8(sp)
1225; RV32-NEXT:    sw a1, 12(sp)
1226; RV32-NEXT:    addi a0, sp, 8
1227; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1228; RV32-NEXT:    vlse64.v v12, (a0), zero
1229; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
1230; RV32-NEXT:    vsaddu.vv v8, v8, v12
1231; RV32-NEXT:    addi sp, sp, 16
1232; RV32-NEXT:    .cfi_def_cfa_offset 0
1233; RV32-NEXT:    ret
1234;
1235; RV64-LABEL: vsaddu_vx_v8i64_unmasked:
1236; RV64:       # %bb.0:
1237; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
1238; RV64-NEXT:    vsaddu.vx v8, v8, a0
1239; RV64-NEXT:    ret
1240  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
1241  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
1242  %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl)
1243  ret <8 x i64> %v
1244}
1245
1246define <8 x i64> @vsaddu_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
1247; CHECK-LABEL: vsaddu_vi_v8i64:
1248; CHECK:       # %bb.0:
1249; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1250; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
1251; CHECK-NEXT:    ret
1252  %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl)
1253  ret <8 x i64> %v
1254}
1255
1256define <8 x i64> @vsaddu_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
1257; CHECK-LABEL: vsaddu_vi_v8i64_unmasked:
1258; CHECK:       # %bb.0:
1259; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1260; CHECK-NEXT:    vsaddu.vi v8, v8, -1
1261; CHECK-NEXT:    ret
1262  %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl)
1263  ret <8 x i64> %v
1264}
1265
1266declare <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64>, <16 x i64>, <16 x i1>, i32)
1267
1268define <16 x i64> @vsaddu_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {
1269; CHECK-LABEL: vsaddu_vv_v16i64:
1270; CHECK:       # %bb.0:
1271; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1272; CHECK-NEXT:    vsaddu.vv v8, v8, v16, v0.t
1273; CHECK-NEXT:    ret
1274  %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)
1275  ret <16 x i64> %v
1276}
1277
1278define <16 x i64> @vsaddu_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {
1279; CHECK-LABEL: vsaddu_vv_v16i64_unmasked:
1280; CHECK:       # %bb.0:
1281; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1282; CHECK-NEXT:    vsaddu.vv v8, v8, v16
1283; CHECK-NEXT:    ret
1284  %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)
1285  ret <16 x i64> %v
1286}
1287
1288define <16 x i64> @vsaddu_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
1289; RV32-LABEL: vsaddu_vx_v16i64:
1290; RV32:       # %bb.0:
1291; RV32-NEXT:    addi sp, sp, -16
1292; RV32-NEXT:    .cfi_def_cfa_offset 16
1293; RV32-NEXT:    sw a0, 8(sp)
1294; RV32-NEXT:    sw a1, 12(sp)
1295; RV32-NEXT:    addi a0, sp, 8
1296; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
1297; RV32-NEXT:    vlse64.v v16, (a0), zero
1298; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
1299; RV32-NEXT:    vsaddu.vv v8, v8, v16, v0.t
1300; RV32-NEXT:    addi sp, sp, 16
1301; RV32-NEXT:    .cfi_def_cfa_offset 0
1302; RV32-NEXT:    ret
1303;
1304; RV64-LABEL: vsaddu_vx_v16i64:
1305; RV64:       # %bb.0:
1306; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1307; RV64-NEXT:    vsaddu.vx v8, v8, a0, v0.t
1308; RV64-NEXT:    ret
1309  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
1310  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
1311  %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
1312  ret <16 x i64> %v
1313}
1314
1315define <16 x i64> @vsaddu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
1316; RV32-LABEL: vsaddu_vx_v16i64_unmasked:
1317; RV32:       # %bb.0:
1318; RV32-NEXT:    addi sp, sp, -16
1319; RV32-NEXT:    .cfi_def_cfa_offset 16
1320; RV32-NEXT:    sw a0, 8(sp)
1321; RV32-NEXT:    sw a1, 12(sp)
1322; RV32-NEXT:    addi a0, sp, 8
1323; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
1324; RV32-NEXT:    vlse64.v v16, (a0), zero
1325; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
1326; RV32-NEXT:    vsaddu.vv v8, v8, v16
1327; RV32-NEXT:    addi sp, sp, 16
1328; RV32-NEXT:    .cfi_def_cfa_offset 0
1329; RV32-NEXT:    ret
1330;
1331; RV64-LABEL: vsaddu_vx_v16i64_unmasked:
1332; RV64:       # %bb.0:
1333; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1334; RV64-NEXT:    vsaddu.vx v8, v8, a0
1335; RV64-NEXT:    ret
1336  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
1337  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
1338  %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl)
1339  ret <16 x i64> %v
1340}
1341
1342define <16 x i64> @vsaddu_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
1343; CHECK-LABEL: vsaddu_vi_v16i64:
1344; CHECK:       # %bb.0:
1345; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1346; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
1347; CHECK-NEXT:    ret
1348  %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl)
1349  ret <16 x i64> %v
1350}
1351
1352define <16 x i64> @vsaddu_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
1353; CHECK-LABEL: vsaddu_vi_v16i64_unmasked:
1354; CHECK:       # %bb.0:
1355; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1356; CHECK-NEXT:    vsaddu.vi v8, v8, -1
1357; CHECK-NEXT:    ret
1358  %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl)
1359  ret <16 x i64> %v
1360}
1361
1362; Test that split-legalization works as expected.
1363
1364declare <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64>, <32 x i64>, <32 x i1>, i32)
1365
1366define <32 x i64> @vsaddu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
1367; CHECK-LABEL: vsaddu_vx_v32i64:
1368; CHECK:       # %bb.0:
1369; CHECK-NEXT:    li a2, 16
1370; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
1371; CHECK-NEXT:    vslidedown.vi v24, v0, 2
1372; CHECK-NEXT:    mv a1, a0
1373; CHECK-NEXT:    bltu a0, a2, .LBB108_2
1374; CHECK-NEXT:  # %bb.1:
1375; CHECK-NEXT:    li a1, 16
1376; CHECK-NEXT:  .LBB108_2:
1377; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1378; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
1379; CHECK-NEXT:    addi a1, a0, -16
1380; CHECK-NEXT:    sltu a0, a0, a1
1381; CHECK-NEXT:    addi a0, a0, -1
1382; CHECK-NEXT:    and a0, a0, a1
1383; CHECK-NEXT:    vmv1r.v v0, v24
1384; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1385; CHECK-NEXT:    vsaddu.vi v16, v16, -1, v0.t
1386; CHECK-NEXT:    ret
1387  %v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)
1388  ret <32 x i64> %v
1389}
1390
1391define <32 x i64> @vsaddu_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
1392; CHECK-LABEL: vsaddu_vi_v32i64_unmasked:
1393; CHECK:       # %bb.0:
1394; CHECK-NEXT:    li a2, 16
1395; CHECK-NEXT:    mv a1, a0
1396; CHECK-NEXT:    bltu a0, a2, .LBB109_2
1397; CHECK-NEXT:  # %bb.1:
1398; CHECK-NEXT:    li a1, 16
1399; CHECK-NEXT:  .LBB109_2:
1400; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1401; CHECK-NEXT:    vsaddu.vi v8, v8, -1
1402; CHECK-NEXT:    addi a1, a0, -16
1403; CHECK-NEXT:    sltu a0, a0, a1
1404; CHECK-NEXT:    addi a0, a0, -1
1405; CHECK-NEXT:    and a0, a0, a1
1406; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1407; CHECK-NEXT:    vsaddu.vi v16, v16, -1
1408; CHECK-NEXT:    ret
1409  %v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl)
1410  ret <32 x i64> %v
1411}
1412
1413define <32 x i64> @vsaddu_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
1414; CHECK-LABEL: vsaddu_vx_v32i64_evl12:
1415; CHECK:       # %bb.0:
1416; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
1417; CHECK-NEXT:    vslidedown.vi v24, v0, 2
1418; CHECK-NEXT:    vsetivli zero, 12, e64, m8, ta, ma
1419; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
1420; CHECK-NEXT:    vmv1r.v v0, v24
1421; CHECK-NEXT:    vsetivli zero, 0, e64, m8, ta, ma
1422; CHECK-NEXT:    vsaddu.vi v16, v16, -1, v0.t
1423; CHECK-NEXT:    ret
1424  %v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12)
1425  ret <32 x i64> %v
1426}
1427
1428define <32 x i64> @vsaddu_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
1429; CHECK-LABEL: vsaddu_vx_v32i64_evl27:
1430; CHECK:       # %bb.0:
1431; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
1432; CHECK-NEXT:    vslidedown.vi v24, v0, 2
1433; CHECK-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
1434; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t
1435; CHECK-NEXT:    vmv1r.v v0, v24
1436; CHECK-NEXT:    vsetivli zero, 11, e64, m8, ta, ma
1437; CHECK-NEXT:    vsaddu.vi v16, v16, -1, v0.t
1438; CHECK-NEXT:    ret
1439  %v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 27)
1440  ret <32 x i64> %v
1441}
1442