xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll (revision 97982a8c605fac7c86d02e641a6cd7898b3ca343) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64
6
7declare <8 x i7> @llvm.vp.urem.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32)
8
9define <8 x i7> @vremu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
10; CHECK-LABEL: vremu_vv_v8i7:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    li a1, 127
13; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
14; CHECK-NEXT:    vand.vx v9, v9, a1, v0.t
15; CHECK-NEXT:    vand.vx v8, v8, a1, v0.t
16; CHECK-NEXT:    vremu.vv v8, v8, v9, v0.t
17; CHECK-NEXT:    ret
18  %v = call <8 x i7> @llvm.vp.urem.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
19  ret <8 x i7> %v
20}
21
22declare <2 x i8> @llvm.vp.urem.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32)
23
24define <2 x i8> @vremu_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {
25; CHECK-LABEL: vremu_vv_v2i8:
26; CHECK:       # %bb.0:
27; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
28; CHECK-NEXT:    vremu.vv v8, v8, v9, v0.t
29; CHECK-NEXT:    ret
30  %v = call <2 x i8> @llvm.vp.urem.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)
31  ret <2 x i8> %v
32}
33
34define <2 x i8> @vremu_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {
35; CHECK-LABEL: vremu_vv_v2i8_unmasked:
36; CHECK:       # %bb.0:
37; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
38; CHECK-NEXT:    vremu.vv v8, v8, v9
39; CHECK-NEXT:    ret
40  %v = call <2 x i8> @llvm.vp.urem.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)
41  ret <2 x i8> %v
42}
43
44define <2 x i8> @vremu_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
45; CHECK-LABEL: vremu_vx_v2i8:
46; CHECK:       # %bb.0:
47; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
48; CHECK-NEXT:    vremu.vx v8, v8, a0, v0.t
49; CHECK-NEXT:    ret
50  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
51  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
52  %v = call <2 x i8> @llvm.vp.urem.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)
53  ret <2 x i8> %v
54}
55
56define <2 x i8> @vremu_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
57; CHECK-LABEL: vremu_vx_v2i8_unmasked:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
60; CHECK-NEXT:    vremu.vx v8, v8, a0
61; CHECK-NEXT:    ret
62  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
63  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
64  %v = call <2 x i8> @llvm.vp.urem.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl)
65  ret <2 x i8> %v
66}
67
68declare <4 x i8> @llvm.vp.urem.v4i8(<4 x i8>, <4 x i8>, <4 x i1>, i32)
69
70define <4 x i8> @vremu_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {
71; CHECK-LABEL: vremu_vv_v4i8:
72; CHECK:       # %bb.0:
73; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
74; CHECK-NEXT:    vremu.vv v8, v8, v9, v0.t
75; CHECK-NEXT:    ret
76  %v = call <4 x i8> @llvm.vp.urem.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)
77  ret <4 x i8> %v
78}
79
80define <4 x i8> @vremu_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {
81; CHECK-LABEL: vremu_vv_v4i8_unmasked:
82; CHECK:       # %bb.0:
83; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
84; CHECK-NEXT:    vremu.vv v8, v8, v9
85; CHECK-NEXT:    ret
86  %v = call <4 x i8> @llvm.vp.urem.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)
87  ret <4 x i8> %v
88}
89
90define <4 x i8> @vremu_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
91; CHECK-LABEL: vremu_vx_v4i8:
92; CHECK:       # %bb.0:
93; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
94; CHECK-NEXT:    vremu.vx v8, v8, a0, v0.t
95; CHECK-NEXT:    ret
96  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
97  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
98  %v = call <4 x i8> @llvm.vp.urem.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)
99  ret <4 x i8> %v
100}
101
102define <4 x i8> @vremu_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
103; CHECK-LABEL: vremu_vx_v4i8_unmasked:
104; CHECK:       # %bb.0:
105; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
106; CHECK-NEXT:    vremu.vx v8, v8, a0
107; CHECK-NEXT:    ret
108  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
109  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
110  %v = call <4 x i8> @llvm.vp.urem.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl)
111  ret <4 x i8> %v
112}
113
114declare <6 x i8> @llvm.vp.urem.v6i8(<6 x i8>, <6 x i8>, <6 x i1>, i32)
115
116define <6 x i8> @vremu_vv_v6i8(<6 x i8> %va, <6 x i8> %b, <6 x i1> %m, i32 zeroext %evl) {
117; CHECK-LABEL: vremu_vv_v6i8:
118; CHECK:       # %bb.0:
119; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
120; CHECK-NEXT:    vremu.vv v8, v8, v9, v0.t
121; CHECK-NEXT:    ret
122  %v = call <6 x i8> @llvm.vp.urem.v6i8(<6 x i8> %va, <6 x i8> %b, <6 x i1> %m, i32 %evl)
123  ret <6 x i8> %v
124}
125
126declare <8 x i8> @llvm.vp.urem.v8i8(<8 x i8>, <8 x i8>, <8 x i1>, i32)
127
128define <8 x i8> @vremu_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {
129; CHECK-LABEL: vremu_vv_v8i8:
130; CHECK:       # %bb.0:
131; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
132; CHECK-NEXT:    vremu.vv v8, v8, v9, v0.t
133; CHECK-NEXT:    ret
134  %v = call <8 x i8> @llvm.vp.urem.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)
135  ret <8 x i8> %v
136}
137
138define <8 x i8> @vremu_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {
139; CHECK-LABEL: vremu_vv_v8i8_unmasked:
140; CHECK:       # %bb.0:
141; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
142; CHECK-NEXT:    vremu.vv v8, v8, v9
143; CHECK-NEXT:    ret
144  %v = call <8 x i8> @llvm.vp.urem.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)
145  ret <8 x i8> %v
146}
147
148define <8 x i8> @vremu_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {
149; CHECK-LABEL: vremu_vx_v8i8:
150; CHECK:       # %bb.0:
151; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
152; CHECK-NEXT:    vremu.vx v8, v8, a0, v0.t
153; CHECK-NEXT:    ret
154  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
155  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
156  %v = call <8 x i8> @llvm.vp.urem.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)
157  ret <8 x i8> %v
158}
159
160define <8 x i8> @vremu_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
161; CHECK-LABEL: vremu_vx_v8i8_unmasked:
162; CHECK:       # %bb.0:
163; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
164; CHECK-NEXT:    vremu.vx v8, v8, a0
165; CHECK-NEXT:    ret
166  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
167  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
168  %v = call <8 x i8> @llvm.vp.urem.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl)
169  ret <8 x i8> %v
170}
171
172declare <16 x i8> @llvm.vp.urem.v16i8(<16 x i8>, <16 x i8>, <16 x i1>, i32)
173
174define <16 x i8> @vremu_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {
175; CHECK-LABEL: vremu_vv_v16i8:
176; CHECK:       # %bb.0:
177; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
178; CHECK-NEXT:    vremu.vv v8, v8, v9, v0.t
179; CHECK-NEXT:    ret
180  %v = call <16 x i8> @llvm.vp.urem.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)
181  ret <16 x i8> %v
182}
183
184define <16 x i8> @vremu_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {
185; CHECK-LABEL: vremu_vv_v16i8_unmasked:
186; CHECK:       # %bb.0:
187; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
188; CHECK-NEXT:    vremu.vv v8, v8, v9
189; CHECK-NEXT:    ret
190  %v = call <16 x i8> @llvm.vp.urem.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)
191  ret <16 x i8> %v
192}
193
194define <16 x i8> @vremu_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {
195; CHECK-LABEL: vremu_vx_v16i8:
196; CHECK:       # %bb.0:
197; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
198; CHECK-NEXT:    vremu.vx v8, v8, a0, v0.t
199; CHECK-NEXT:    ret
200  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
201  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
202  %v = call <16 x i8> @llvm.vp.urem.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)
203  ret <16 x i8> %v
204}
205
206define <16 x i8> @vremu_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {
207; CHECK-LABEL: vremu_vx_v16i8_unmasked:
208; CHECK:       # %bb.0:
209; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
210; CHECK-NEXT:    vremu.vx v8, v8, a0
211; CHECK-NEXT:    ret
212  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
213  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
214  %v = call <16 x i8> @llvm.vp.urem.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl)
215  ret <16 x i8> %v
216}
217
218declare <2 x i16> @llvm.vp.urem.v2i16(<2 x i16>, <2 x i16>, <2 x i1>, i32)
219
220define <2 x i16> @vremu_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {
221; CHECK-LABEL: vremu_vv_v2i16:
222; CHECK:       # %bb.0:
223; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
224; CHECK-NEXT:    vremu.vv v8, v8, v9, v0.t
225; CHECK-NEXT:    ret
226  %v = call <2 x i16> @llvm.vp.urem.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)
227  ret <2 x i16> %v
228}
229
230define <2 x i16> @vremu_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {
231; CHECK-LABEL: vremu_vv_v2i16_unmasked:
232; CHECK:       # %bb.0:
233; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
234; CHECK-NEXT:    vremu.vv v8, v8, v9
235; CHECK-NEXT:    ret
236  %v = call <2 x i16> @llvm.vp.urem.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)
237  ret <2 x i16> %v
238}
239
240define <2 x i16> @vremu_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {
241; CHECK-LABEL: vremu_vx_v2i16:
242; CHECK:       # %bb.0:
243; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
244; CHECK-NEXT:    vremu.vx v8, v8, a0, v0.t
245; CHECK-NEXT:    ret
246  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
247  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
248  %v = call <2 x i16> @llvm.vp.urem.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)
249  ret <2 x i16> %v
250}
251
252define <2 x i16> @vremu_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {
253; CHECK-LABEL: vremu_vx_v2i16_unmasked:
254; CHECK:       # %bb.0:
255; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
256; CHECK-NEXT:    vremu.vx v8, v8, a0
257; CHECK-NEXT:    ret
258  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
259  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
260  %v = call <2 x i16> @llvm.vp.urem.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl)
261  ret <2 x i16> %v
262}
263
264declare <4 x i16> @llvm.vp.urem.v4i16(<4 x i16>, <4 x i16>, <4 x i1>, i32)
265
266define <4 x i16> @vremu_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {
267; CHECK-LABEL: vremu_vv_v4i16:
268; CHECK:       # %bb.0:
269; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
270; CHECK-NEXT:    vremu.vv v8, v8, v9, v0.t
271; CHECK-NEXT:    ret
272  %v = call <4 x i16> @llvm.vp.urem.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)
273  ret <4 x i16> %v
274}
275
276define <4 x i16> @vremu_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {
277; CHECK-LABEL: vremu_vv_v4i16_unmasked:
278; CHECK:       # %bb.0:
279; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
280; CHECK-NEXT:    vremu.vv v8, v8, v9
281; CHECK-NEXT:    ret
282  %v = call <4 x i16> @llvm.vp.urem.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)
283  ret <4 x i16> %v
284}
285
286define <4 x i16> @vremu_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {
287; CHECK-LABEL: vremu_vx_v4i16:
288; CHECK:       # %bb.0:
289; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
290; CHECK-NEXT:    vremu.vx v8, v8, a0, v0.t
291; CHECK-NEXT:    ret
292  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
293  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
294  %v = call <4 x i16> @llvm.vp.urem.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)
295  ret <4 x i16> %v
296}
297
298define <4 x i16> @vremu_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {
299; CHECK-LABEL: vremu_vx_v4i16_unmasked:
300; CHECK:       # %bb.0:
301; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
302; CHECK-NEXT:    vremu.vx v8, v8, a0
303; CHECK-NEXT:    ret
304  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
305  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
306  %v = call <4 x i16> @llvm.vp.urem.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl)
307  ret <4 x i16> %v
308}
309
310declare <8 x i16> @llvm.vp.urem.v8i16(<8 x i16>, <8 x i16>, <8 x i1>, i32)
311
312define <8 x i16> @vremu_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {
313; CHECK-LABEL: vremu_vv_v8i16:
314; CHECK:       # %bb.0:
315; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
316; CHECK-NEXT:    vremu.vv v8, v8, v9, v0.t
317; CHECK-NEXT:    ret
318  %v = call <8 x i16> @llvm.vp.urem.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)
319  ret <8 x i16> %v
320}
321
322define <8 x i16> @vremu_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {
323; CHECK-LABEL: vremu_vv_v8i16_unmasked:
324; CHECK:       # %bb.0:
325; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
326; CHECK-NEXT:    vremu.vv v8, v8, v9
327; CHECK-NEXT:    ret
328  %v = call <8 x i16> @llvm.vp.urem.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)
329  ret <8 x i16> %v
330}
331
332define <8 x i16> @vremu_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {
333; CHECK-LABEL: vremu_vx_v8i16:
334; CHECK:       # %bb.0:
335; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
336; CHECK-NEXT:    vremu.vx v8, v8, a0, v0.t
337; CHECK-NEXT:    ret
338  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
339  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
340  %v = call <8 x i16> @llvm.vp.urem.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)
341  ret <8 x i16> %v
342}
343
344define <8 x i16> @vremu_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {
345; CHECK-LABEL: vremu_vx_v8i16_unmasked:
346; CHECK:       # %bb.0:
347; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
348; CHECK-NEXT:    vremu.vx v8, v8, a0
349; CHECK-NEXT:    ret
350  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
351  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
352  %v = call <8 x i16> @llvm.vp.urem.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl)
353  ret <8 x i16> %v
354}
355
356declare <16 x i16> @llvm.vp.urem.v16i16(<16 x i16>, <16 x i16>, <16 x i1>, i32)
357
358define <16 x i16> @vremu_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {
359; CHECK-LABEL: vremu_vv_v16i16:
360; CHECK:       # %bb.0:
361; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
362; CHECK-NEXT:    vremu.vv v8, v8, v10, v0.t
363; CHECK-NEXT:    ret
364  %v = call <16 x i16> @llvm.vp.urem.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)
365  ret <16 x i16> %v
366}
367
368define <16 x i16> @vremu_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {
369; CHECK-LABEL: vremu_vv_v16i16_unmasked:
370; CHECK:       # %bb.0:
371; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
372; CHECK-NEXT:    vremu.vv v8, v8, v10
373; CHECK-NEXT:    ret
374  %v = call <16 x i16> @llvm.vp.urem.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)
375  ret <16 x i16> %v
376}
377
378define <16 x i16> @vremu_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {
379; CHECK-LABEL: vremu_vx_v16i16:
380; CHECK:       # %bb.0:
381; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
382; CHECK-NEXT:    vremu.vx v8, v8, a0, v0.t
383; CHECK-NEXT:    ret
384  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
385  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
386  %v = call <16 x i16> @llvm.vp.urem.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)
387  ret <16 x i16> %v
388}
389
390define <16 x i16> @vremu_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {
391; CHECK-LABEL: vremu_vx_v16i16_unmasked:
392; CHECK:       # %bb.0:
393; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
394; CHECK-NEXT:    vremu.vx v8, v8, a0
395; CHECK-NEXT:    ret
396  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
397  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
398  %v = call <16 x i16> @llvm.vp.urem.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl)
399  ret <16 x i16> %v
400}
401
402declare <2 x i32> @llvm.vp.urem.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32)
403
404define <2 x i32> @vremu_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {
405; CHECK-LABEL: vremu_vv_v2i32:
406; CHECK:       # %bb.0:
407; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
408; CHECK-NEXT:    vremu.vv v8, v8, v9, v0.t
409; CHECK-NEXT:    ret
410  %v = call <2 x i32> @llvm.vp.urem.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)
411  ret <2 x i32> %v
412}
413
414define <2 x i32> @vremu_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {
415; CHECK-LABEL: vremu_vv_v2i32_unmasked:
416; CHECK:       # %bb.0:
417; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
418; CHECK-NEXT:    vremu.vv v8, v8, v9
419; CHECK-NEXT:    ret
420  %v = call <2 x i32> @llvm.vp.urem.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)
421  ret <2 x i32> %v
422}
423
424define <2 x i32> @vremu_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {
425; CHECK-LABEL: vremu_vx_v2i32:
426; CHECK:       # %bb.0:
427; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
428; CHECK-NEXT:    vremu.vx v8, v8, a0, v0.t
429; CHECK-NEXT:    ret
430  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
431  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
432  %v = call <2 x i32> @llvm.vp.urem.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)
433  ret <2 x i32> %v
434}
435
436define <2 x i32> @vremu_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {
437; CHECK-LABEL: vremu_vx_v2i32_unmasked:
438; CHECK:       # %bb.0:
439; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
440; CHECK-NEXT:    vremu.vx v8, v8, a0
441; CHECK-NEXT:    ret
442  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
443  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
444  %v = call <2 x i32> @llvm.vp.urem.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl)
445  ret <2 x i32> %v
446}
447
448declare <4 x i32> @llvm.vp.urem.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
449
450define <4 x i32> @vremu_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {
451; CHECK-LABEL: vremu_vv_v4i32:
452; CHECK:       # %bb.0:
453; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
454; CHECK-NEXT:    vremu.vv v8, v8, v9, v0.t
455; CHECK-NEXT:    ret
456  %v = call <4 x i32> @llvm.vp.urem.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)
457  ret <4 x i32> %v
458}
459
460define <4 x i32> @vremu_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {
461; CHECK-LABEL: vremu_vv_v4i32_unmasked:
462; CHECK:       # %bb.0:
463; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
464; CHECK-NEXT:    vremu.vv v8, v8, v9
465; CHECK-NEXT:    ret
466  %v = call <4 x i32> @llvm.vp.urem.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)
467  ret <4 x i32> %v
468}
469
470define <4 x i32> @vremu_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {
471; CHECK-LABEL: vremu_vx_v4i32:
472; CHECK:       # %bb.0:
473; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
474; CHECK-NEXT:    vremu.vx v8, v8, a0, v0.t
475; CHECK-NEXT:    ret
476  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
477  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
478  %v = call <4 x i32> @llvm.vp.urem.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)
479  ret <4 x i32> %v
480}
481
482define <4 x i32> @vremu_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {
483; CHECK-LABEL: vremu_vx_v4i32_unmasked:
484; CHECK:       # %bb.0:
485; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
486; CHECK-NEXT:    vremu.vx v8, v8, a0
487; CHECK-NEXT:    ret
488  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
489  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
490  %v = call <4 x i32> @llvm.vp.urem.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl)
491  ret <4 x i32> %v
492}
493
494declare <8 x i32> @llvm.vp.urem.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
495
496define <8 x i32> @vremu_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {
497; CHECK-LABEL: vremu_vv_v8i32:
498; CHECK:       # %bb.0:
499; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
500; CHECK-NEXT:    vremu.vv v8, v8, v10, v0.t
501; CHECK-NEXT:    ret
502  %v = call <8 x i32> @llvm.vp.urem.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)
503  ret <8 x i32> %v
504}
505
506define <8 x i32> @vremu_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {
507; CHECK-LABEL: vremu_vv_v8i32_unmasked:
508; CHECK:       # %bb.0:
509; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
510; CHECK-NEXT:    vremu.vv v8, v8, v10
511; CHECK-NEXT:    ret
512  %v = call <8 x i32> @llvm.vp.urem.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)
513  ret <8 x i32> %v
514}
515
516define <8 x i32> @vremu_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {
517; CHECK-LABEL: vremu_vx_v8i32:
518; CHECK:       # %bb.0:
519; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
520; CHECK-NEXT:    vremu.vx v8, v8, a0, v0.t
521; CHECK-NEXT:    ret
522  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
523  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
524  %v = call <8 x i32> @llvm.vp.urem.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)
525  ret <8 x i32> %v
526}
527
528define <8 x i32> @vremu_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {
529; CHECK-LABEL: vremu_vx_v8i32_unmasked:
530; CHECK:       # %bb.0:
531; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
532; CHECK-NEXT:    vremu.vx v8, v8, a0
533; CHECK-NEXT:    ret
534  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
535  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
536  %v = call <8 x i32> @llvm.vp.urem.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl)
537  ret <8 x i32> %v
538}
539
540declare <16 x i32> @llvm.vp.urem.v16i32(<16 x i32>, <16 x i32>, <16 x i1>, i32)
541
542define <16 x i32> @vremu_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {
543; CHECK-LABEL: vremu_vv_v16i32:
544; CHECK:       # %bb.0:
545; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
546; CHECK-NEXT:    vremu.vv v8, v8, v12, v0.t
547; CHECK-NEXT:    ret
548  %v = call <16 x i32> @llvm.vp.urem.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)
549  ret <16 x i32> %v
550}
551
552define <16 x i32> @vremu_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {
553; CHECK-LABEL: vremu_vv_v16i32_unmasked:
554; CHECK:       # %bb.0:
555; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
556; CHECK-NEXT:    vremu.vv v8, v8, v12
557; CHECK-NEXT:    ret
558  %v = call <16 x i32> @llvm.vp.urem.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)
559  ret <16 x i32> %v
560}
561
562define <16 x i32> @vremu_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {
563; CHECK-LABEL: vremu_vx_v16i32:
564; CHECK:       # %bb.0:
565; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
566; CHECK-NEXT:    vremu.vx v8, v8, a0, v0.t
567; CHECK-NEXT:    ret
568  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
569  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
570  %v = call <16 x i32> @llvm.vp.urem.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)
571  ret <16 x i32> %v
572}
573
574define <16 x i32> @vremu_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {
575; CHECK-LABEL: vremu_vx_v16i32_unmasked:
576; CHECK:       # %bb.0:
577; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
578; CHECK-NEXT:    vremu.vx v8, v8, a0
579; CHECK-NEXT:    ret
580  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
581  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
582  %v = call <16 x i32> @llvm.vp.urem.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl)
583  ret <16 x i32> %v
584}
585
586declare <2 x i64> @llvm.vp.urem.v2i64(<2 x i64>, <2 x i64>, <2 x i1>, i32)
587
588define <2 x i64> @vremu_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {
589; CHECK-LABEL: vremu_vv_v2i64:
590; CHECK:       # %bb.0:
591; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
592; CHECK-NEXT:    vremu.vv v8, v8, v9, v0.t
593; CHECK-NEXT:    ret
594  %v = call <2 x i64> @llvm.vp.urem.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)
595  ret <2 x i64> %v
596}
597
598define <2 x i64> @vremu_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {
599; CHECK-LABEL: vremu_vv_v2i64_unmasked:
600; CHECK:       # %bb.0:
601; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
602; CHECK-NEXT:    vremu.vv v8, v8, v9
603; CHECK-NEXT:    ret
604  %v = call <2 x i64> @llvm.vp.urem.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)
605  ret <2 x i64> %v
606}
607
608define <2 x i64> @vremu_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
609; RV32-LABEL: vremu_vx_v2i64:
610; RV32:       # %bb.0:
611; RV32-NEXT:    addi sp, sp, -16
612; RV32-NEXT:    .cfi_def_cfa_offset 16
613; RV32-NEXT:    sw a0, 8(sp)
614; RV32-NEXT:    sw a1, 12(sp)
615; RV32-NEXT:    addi a0, sp, 8
616; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
617; RV32-NEXT:    vlse64.v v9, (a0), zero
618; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
619; RV32-NEXT:    vremu.vv v8, v8, v9, v0.t
620; RV32-NEXT:    addi sp, sp, 16
621; RV32-NEXT:    .cfi_def_cfa_offset 0
622; RV32-NEXT:    ret
623;
624; RV64-LABEL: vremu_vx_v2i64:
625; RV64:       # %bb.0:
626; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
627; RV64-NEXT:    vremu.vx v8, v8, a0, v0.t
628; RV64-NEXT:    ret
629  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
630  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
631  %v = call <2 x i64> @llvm.vp.urem.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
632  ret <2 x i64> %v
633}
634
635define <2 x i64> @vremu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
636; RV32-LABEL: vremu_vx_v2i64_unmasked:
637; RV32:       # %bb.0:
638; RV32-NEXT:    addi sp, sp, -16
639; RV32-NEXT:    .cfi_def_cfa_offset 16
640; RV32-NEXT:    sw a0, 8(sp)
641; RV32-NEXT:    sw a1, 12(sp)
642; RV32-NEXT:    addi a0, sp, 8
643; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
644; RV32-NEXT:    vlse64.v v9, (a0), zero
645; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
646; RV32-NEXT:    vremu.vv v8, v8, v9
647; RV32-NEXT:    addi sp, sp, 16
648; RV32-NEXT:    .cfi_def_cfa_offset 0
649; RV32-NEXT:    ret
650;
651; RV64-LABEL: vremu_vx_v2i64_unmasked:
652; RV64:       # %bb.0:
653; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
654; RV64-NEXT:    vremu.vx v8, v8, a0
655; RV64-NEXT:    ret
656  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
657  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
658  %v = call <2 x i64> @llvm.vp.urem.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl)
659  ret <2 x i64> %v
660}
661
662declare <4 x i64> @llvm.vp.urem.v4i64(<4 x i64>, <4 x i64>, <4 x i1>, i32)
663
664define <4 x i64> @vremu_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {
665; CHECK-LABEL: vremu_vv_v4i64:
666; CHECK:       # %bb.0:
667; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
668; CHECK-NEXT:    vremu.vv v8, v8, v10, v0.t
669; CHECK-NEXT:    ret
670  %v = call <4 x i64> @llvm.vp.urem.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)
671  ret <4 x i64> %v
672}
673
674define <4 x i64> @vremu_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {
675; CHECK-LABEL: vremu_vv_v4i64_unmasked:
676; CHECK:       # %bb.0:
677; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
678; CHECK-NEXT:    vremu.vv v8, v8, v10
679; CHECK-NEXT:    ret
680  %v = call <4 x i64> @llvm.vp.urem.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)
681  ret <4 x i64> %v
682}
683
684define <4 x i64> @vremu_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
685; RV32-LABEL: vremu_vx_v4i64:
686; RV32:       # %bb.0:
687; RV32-NEXT:    addi sp, sp, -16
688; RV32-NEXT:    .cfi_def_cfa_offset 16
689; RV32-NEXT:    sw a0, 8(sp)
690; RV32-NEXT:    sw a1, 12(sp)
691; RV32-NEXT:    addi a0, sp, 8
692; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
693; RV32-NEXT:    vlse64.v v10, (a0), zero
694; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
695; RV32-NEXT:    vremu.vv v8, v8, v10, v0.t
696; RV32-NEXT:    addi sp, sp, 16
697; RV32-NEXT:    .cfi_def_cfa_offset 0
698; RV32-NEXT:    ret
699;
700; RV64-LABEL: vremu_vx_v4i64:
701; RV64:       # %bb.0:
702; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
703; RV64-NEXT:    vremu.vx v8, v8, a0, v0.t
704; RV64-NEXT:    ret
705  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
706  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
707  %v = call <4 x i64> @llvm.vp.urem.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
708  ret <4 x i64> %v
709}
710
711define <4 x i64> @vremu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
712; RV32-LABEL: vremu_vx_v4i64_unmasked:
713; RV32:       # %bb.0:
714; RV32-NEXT:    addi sp, sp, -16
715; RV32-NEXT:    .cfi_def_cfa_offset 16
716; RV32-NEXT:    sw a0, 8(sp)
717; RV32-NEXT:    sw a1, 12(sp)
718; RV32-NEXT:    addi a0, sp, 8
719; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
720; RV32-NEXT:    vlse64.v v10, (a0), zero
721; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
722; RV32-NEXT:    vremu.vv v8, v8, v10
723; RV32-NEXT:    addi sp, sp, 16
724; RV32-NEXT:    .cfi_def_cfa_offset 0
725; RV32-NEXT:    ret
726;
727; RV64-LABEL: vremu_vx_v4i64_unmasked:
728; RV64:       # %bb.0:
729; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
730; RV64-NEXT:    vremu.vx v8, v8, a0
731; RV64-NEXT:    ret
732  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
733  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
734  %v = call <4 x i64> @llvm.vp.urem.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl)
735  ret <4 x i64> %v
736}
737
738declare <8 x i64> @llvm.vp.urem.v8i64(<8 x i64>, <8 x i64>, <8 x i1>, i32)
739
740define <8 x i64> @vremu_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {
741; CHECK-LABEL: vremu_vv_v8i64:
742; CHECK:       # %bb.0:
743; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
744; CHECK-NEXT:    vremu.vv v8, v8, v12, v0.t
745; CHECK-NEXT:    ret
746  %v = call <8 x i64> @llvm.vp.urem.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)
747  ret <8 x i64> %v
748}
749
750define <8 x i64> @vremu_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {
751; CHECK-LABEL: vremu_vv_v8i64_unmasked:
752; CHECK:       # %bb.0:
753; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
754; CHECK-NEXT:    vremu.vv v8, v8, v12
755; CHECK-NEXT:    ret
756  %v = call <8 x i64> @llvm.vp.urem.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)
757  ret <8 x i64> %v
758}
759
760define <8 x i64> @vremu_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
761; RV32-LABEL: vremu_vx_v8i64:
762; RV32:       # %bb.0:
763; RV32-NEXT:    addi sp, sp, -16
764; RV32-NEXT:    .cfi_def_cfa_offset 16
765; RV32-NEXT:    sw a0, 8(sp)
766; RV32-NEXT:    sw a1, 12(sp)
767; RV32-NEXT:    addi a0, sp, 8
768; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
769; RV32-NEXT:    vlse64.v v12, (a0), zero
770; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
771; RV32-NEXT:    vremu.vv v8, v8, v12, v0.t
772; RV32-NEXT:    addi sp, sp, 16
773; RV32-NEXT:    .cfi_def_cfa_offset 0
774; RV32-NEXT:    ret
775;
776; RV64-LABEL: vremu_vx_v8i64:
777; RV64:       # %bb.0:
778; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
779; RV64-NEXT:    vremu.vx v8, v8, a0, v0.t
780; RV64-NEXT:    ret
781  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
782  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
783  %v = call <8 x i64> @llvm.vp.urem.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
784  ret <8 x i64> %v
785}
786
787define <8 x i64> @vremu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
788; RV32-LABEL: vremu_vx_v8i64_unmasked:
789; RV32:       # %bb.0:
790; RV32-NEXT:    addi sp, sp, -16
791; RV32-NEXT:    .cfi_def_cfa_offset 16
792; RV32-NEXT:    sw a0, 8(sp)
793; RV32-NEXT:    sw a1, 12(sp)
794; RV32-NEXT:    addi a0, sp, 8
795; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
796; RV32-NEXT:    vlse64.v v12, (a0), zero
797; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
798; RV32-NEXT:    vremu.vv v8, v8, v12
799; RV32-NEXT:    addi sp, sp, 16
800; RV32-NEXT:    .cfi_def_cfa_offset 0
801; RV32-NEXT:    ret
802;
803; RV64-LABEL: vremu_vx_v8i64_unmasked:
804; RV64:       # %bb.0:
805; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
806; RV64-NEXT:    vremu.vx v8, v8, a0
807; RV64-NEXT:    ret
808  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
809  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
810  %v = call <8 x i64> @llvm.vp.urem.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl)
811  ret <8 x i64> %v
812}
813
814declare <16 x i64> @llvm.vp.urem.v16i64(<16 x i64>, <16 x i64>, <16 x i1>, i32)
815
816define <16 x i64> @vremu_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {
817; CHECK-LABEL: vremu_vv_v16i64:
818; CHECK:       # %bb.0:
819; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
820; CHECK-NEXT:    vremu.vv v8, v8, v16, v0.t
821; CHECK-NEXT:    ret
822  %v = call <16 x i64> @llvm.vp.urem.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)
823  ret <16 x i64> %v
824}
825
826define <16 x i64> @vremu_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {
827; CHECK-LABEL: vremu_vv_v16i64_unmasked:
828; CHECK:       # %bb.0:
829; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
830; CHECK-NEXT:    vremu.vv v8, v8, v16
831; CHECK-NEXT:    ret
832  %v = call <16 x i64> @llvm.vp.urem.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)
833  ret <16 x i64> %v
834}
835
836define <16 x i64> @vremu_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
837; RV32-LABEL: vremu_vx_v16i64:
838; RV32:       # %bb.0:
839; RV32-NEXT:    addi sp, sp, -16
840; RV32-NEXT:    .cfi_def_cfa_offset 16
841; RV32-NEXT:    sw a0, 8(sp)
842; RV32-NEXT:    sw a1, 12(sp)
843; RV32-NEXT:    addi a0, sp, 8
844; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
845; RV32-NEXT:    vlse64.v v16, (a0), zero
846; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
847; RV32-NEXT:    vremu.vv v8, v8, v16, v0.t
848; RV32-NEXT:    addi sp, sp, 16
849; RV32-NEXT:    .cfi_def_cfa_offset 0
850; RV32-NEXT:    ret
851;
852; RV64-LABEL: vremu_vx_v16i64:
853; RV64:       # %bb.0:
854; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
855; RV64-NEXT:    vremu.vx v8, v8, a0, v0.t
856; RV64-NEXT:    ret
857  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
858  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
859  %v = call <16 x i64> @llvm.vp.urem.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
860  ret <16 x i64> %v
861}
862
863define <16 x i64> @vremu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
864; RV32-LABEL: vremu_vx_v16i64_unmasked:
865; RV32:       # %bb.0:
866; RV32-NEXT:    addi sp, sp, -16
867; RV32-NEXT:    .cfi_def_cfa_offset 16
868; RV32-NEXT:    sw a0, 8(sp)
869; RV32-NEXT:    sw a1, 12(sp)
870; RV32-NEXT:    addi a0, sp, 8
871; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
872; RV32-NEXT:    vlse64.v v16, (a0), zero
873; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
874; RV32-NEXT:    vremu.vv v8, v8, v16
875; RV32-NEXT:    addi sp, sp, 16
876; RV32-NEXT:    .cfi_def_cfa_offset 0
877; RV32-NEXT:    ret
878;
879; RV64-LABEL: vremu_vx_v16i64_unmasked:
880; RV64:       # %bb.0:
881; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
882; RV64-NEXT:    vremu.vx v8, v8, a0
883; RV64-NEXT:    ret
884  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
885  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
886  %v = call <16 x i64> @llvm.vp.urem.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl)
887  ret <16 x i64> %v
888}
889
890
891declare <3 x i8> @llvm.vp.urem.v3i8(<3 x i8>, <3 x i8>, <3 x i1>, i32)
892
893define <3 x i8> @vremu_vv_v3i8_unmasked(<3 x i8> %va, <3 x i8> %b, i32 zeroext %evl) {
894; CHECK-LABEL: vremu_vv_v3i8_unmasked:
895; CHECK:       # %bb.0:
896; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
897; CHECK-NEXT:    vremu.vv v8, v8, v9
898; CHECK-NEXT:    ret
899  %v = call <3 x i8> @llvm.vp.urem.v3i8(<3 x i8> %va, <3 x i8> %b, <3 x i1> splat (i1 true), i32 %evl)
900  ret <3 x i8> %v
901}
902
903define <3 x i8> @vremu_vv_v3i8_unmasked_avl3(<3 x i8> %va, <3 x i8> %b) {
904; CHECK-LABEL: vremu_vv_v3i8_unmasked_avl3:
905; CHECK:       # %bb.0:
906; CHECK-NEXT:    vsetivli zero, 3, e8, mf4, ta, ma
907; CHECK-NEXT:    vremu.vv v8, v8, v9
908; CHECK-NEXT:    ret
909  %v = call <3 x i8> @llvm.vp.urem.v3i8(<3 x i8> %va, <3 x i8> %b, <3 x i1> splat (i1 true), i32 3)
910  ret <3 x i8> %v
911}
912
913declare <7 x i8> @llvm.vp.urem.v7i8(<7 x i8>, <7 x i8>, <7 x i1>, i32)
914
915define <7 x i8> @vremu_vv_v7i8_unmasked(<7 x i8> %va, <7 x i8> %b, i32 zeroext %evl) {
916; CHECK-LABEL: vremu_vv_v7i8_unmasked:
917; CHECK:       # %bb.0:
918; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
919; CHECK-NEXT:    vremu.vv v8, v8, v9
920; CHECK-NEXT:    ret
921  %v = call <7 x i8> @llvm.vp.urem.v7i8(<7 x i8> %va, <7 x i8> %b, <7 x i1> splat (i1 true), i32 %evl)
922  ret <7 x i8> %v
923}
924
925define <7 x i8> @vremu_vv_v7i8_unmasked_avl7(<7 x i8> %va, <7 x i8> %b) {
926; CHECK-LABEL: vremu_vv_v7i8_unmasked_avl7:
927; CHECK:       # %bb.0:
928; CHECK-NEXT:    vsetivli zero, 7, e8, mf2, ta, ma
929; CHECK-NEXT:    vremu.vv v8, v8, v9
930; CHECK-NEXT:    ret
931  %v = call <7 x i8> @llvm.vp.urem.v7i8(<7 x i8> %va, <7 x i8> %b, <7 x i1> splat (i1 true), i32 7)
932  ret <7 x i8> %v
933}
934