xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll (revision 95b6524e5c84169ecf404f755aeab2202e9916ea) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s
4
5declare i1 @llvm.vector.reduce.or.v1i1(<1 x i1>)
6
7define zeroext i1 @vreduce_or_v1i1(<1 x i1> %v) {
8; CHECK-LABEL: vreduce_or_v1i1:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
11; CHECK-NEXT:    vfirst.m a0, v0
12; CHECK-NEXT:    seqz a0, a0
13; CHECK-NEXT:    ret
14  %red = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %v)
15  ret i1 %red
16}
17
18declare i1 @llvm.vector.reduce.xor.v1i1(<1 x i1>)
19
20define zeroext i1 @vreduce_xor_v1i1(<1 x i1> %v) {
21; CHECK-LABEL: vreduce_xor_v1i1:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
24; CHECK-NEXT:    vfirst.m a0, v0
25; CHECK-NEXT:    seqz a0, a0
26; CHECK-NEXT:    ret
27  %red = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %v)
28  ret i1 %red
29}
30
31declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1>)
32
33define zeroext i1 @vreduce_and_v1i1(<1 x i1> %v) {
34; CHECK-LABEL: vreduce_and_v1i1:
35; CHECK:       # %bb.0:
36; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
37; CHECK-NEXT:    vfirst.m a0, v0
38; CHECK-NEXT:    seqz a0, a0
39; CHECK-NEXT:    ret
40  %red = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %v)
41  ret i1 %red
42}
43
44declare i1 @llvm.vector.reduce.umax.v1i1(<1 x i1>)
45
46define zeroext i1 @vreduce_umax_v1i1(<1 x i1> %v) {
47; CHECK-LABEL: vreduce_umax_v1i1:
48; CHECK:       # %bb.0:
49; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
50; CHECK-NEXT:    vfirst.m a0, v0
51; CHECK-NEXT:    seqz a0, a0
52; CHECK-NEXT:    ret
53  %red = call i1 @llvm.vector.reduce.umax.v1i1(<1 x i1> %v)
54  ret i1 %red
55}
56
57declare i1 @llvm.vector.reduce.smax.v1i1(<1 x i1>)
58
59define zeroext i1 @vreduce_smax_v1i1(<1 x i1> %v) {
60; CHECK-LABEL: vreduce_smax_v1i1:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
63; CHECK-NEXT:    vfirst.m a0, v0
64; CHECK-NEXT:    seqz a0, a0
65; CHECK-NEXT:    ret
66  %red = call i1 @llvm.vector.reduce.smax.v1i1(<1 x i1> %v)
67  ret i1 %red
68}
69
70declare i1 @llvm.vector.reduce.umin.v1i1(<1 x i1>)
71
72define zeroext i1 @vreduce_umin_v1i1(<1 x i1> %v) {
73; CHECK-LABEL: vreduce_umin_v1i1:
74; CHECK:       # %bb.0:
75; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
76; CHECK-NEXT:    vfirst.m a0, v0
77; CHECK-NEXT:    seqz a0, a0
78; CHECK-NEXT:    ret
79  %red = call i1 @llvm.vector.reduce.umin.v1i1(<1 x i1> %v)
80  ret i1 %red
81}
82
83declare i1 @llvm.vector.reduce.smin.v1i1(<1 x i1>)
84
85define zeroext i1 @vreduce_smin_v1i1(<1 x i1> %v) {
86; CHECK-LABEL: vreduce_smin_v1i1:
87; CHECK:       # %bb.0:
88; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
89; CHECK-NEXT:    vfirst.m a0, v0
90; CHECK-NEXT:    seqz a0, a0
91; CHECK-NEXT:    ret
92  %red = call i1 @llvm.vector.reduce.smin.v1i1(<1 x i1> %v)
93  ret i1 %red
94}
95
96declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>)
97
98define zeroext i1 @vreduce_or_v2i1(<2 x i1> %v) {
99; CHECK-LABEL: vreduce_or_v2i1:
100; CHECK:       # %bb.0:
101; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
102; CHECK-NEXT:    vcpop.m a0, v0
103; CHECK-NEXT:    snez a0, a0
104; CHECK-NEXT:    ret
105  %red = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %v)
106  ret i1 %red
107}
108
109declare i1 @llvm.vector.reduce.xor.v2i1(<2 x i1>)
110
111define zeroext i1 @vreduce_xor_v2i1(<2 x i1> %v) {
112; CHECK-LABEL: vreduce_xor_v2i1:
113; CHECK:       # %bb.0:
114; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
115; CHECK-NEXT:    vcpop.m a0, v0
116; CHECK-NEXT:    andi a0, a0, 1
117; CHECK-NEXT:    ret
118  %red = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> %v)
119  ret i1 %red
120}
121
122declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1>)
123
124define zeroext i1 @vreduce_and_v2i1(<2 x i1> %v) {
125; CHECK-LABEL: vreduce_and_v2i1:
126; CHECK:       # %bb.0:
127; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
128; CHECK-NEXT:    vmnot.m v8, v0
129; CHECK-NEXT:    vcpop.m a0, v8
130; CHECK-NEXT:    seqz a0, a0
131; CHECK-NEXT:    ret
132  %red = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %v)
133  ret i1 %red
134}
135
136declare i1 @llvm.vector.reduce.umax.v2i1(<2 x i1>)
137
138define zeroext i1 @vreduce_umax_v2i1(<2 x i1> %v) {
139; CHECK-LABEL: vreduce_umax_v2i1:
140; CHECK:       # %bb.0:
141; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
142; CHECK-NEXT:    vcpop.m a0, v0
143; CHECK-NEXT:    snez a0, a0
144; CHECK-NEXT:    ret
145  %red = call i1 @llvm.vector.reduce.umax.v2i1(<2 x i1> %v)
146  ret i1 %red
147}
148
149declare i1 @llvm.vector.reduce.smax.v2i1(<2 x i1>)
150
151define zeroext i1 @vreduce_smax_v2i1(<2 x i1> %v) {
152; CHECK-LABEL: vreduce_smax_v2i1:
153; CHECK:       # %bb.0:
154; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
155; CHECK-NEXT:    vmnot.m v8, v0
156; CHECK-NEXT:    vcpop.m a0, v8
157; CHECK-NEXT:    seqz a0, a0
158; CHECK-NEXT:    ret
159  %red = call i1 @llvm.vector.reduce.smax.v2i1(<2 x i1> %v)
160  ret i1 %red
161}
162
163declare i1 @llvm.vector.reduce.umin.v2i1(<2 x i1>)
164
165define zeroext i1 @vreduce_umin_v2i1(<2 x i1> %v) {
166; CHECK-LABEL: vreduce_umin_v2i1:
167; CHECK:       # %bb.0:
168; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
169; CHECK-NEXT:    vmnot.m v8, v0
170; CHECK-NEXT:    vcpop.m a0, v8
171; CHECK-NEXT:    seqz a0, a0
172; CHECK-NEXT:    ret
173  %red = call i1 @llvm.vector.reduce.umin.v2i1(<2 x i1> %v)
174  ret i1 %red
175}
176
177declare i1 @llvm.vector.reduce.smin.v2i1(<2 x i1>)
178
179define zeroext i1 @vreduce_smin_v2i1(<2 x i1> %v) {
180; CHECK-LABEL: vreduce_smin_v2i1:
181; CHECK:       # %bb.0:
182; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
183; CHECK-NEXT:    vcpop.m a0, v0
184; CHECK-NEXT:    snez a0, a0
185; CHECK-NEXT:    ret
186  %red = call i1 @llvm.vector.reduce.smin.v2i1(<2 x i1> %v)
187  ret i1 %red
188}
189
190declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1>)
191
192define zeroext i1 @vreduce_or_v4i1(<4 x i1> %v) {
193; CHECK-LABEL: vreduce_or_v4i1:
194; CHECK:       # %bb.0:
195; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
196; CHECK-NEXT:    vcpop.m a0, v0
197; CHECK-NEXT:    snez a0, a0
198; CHECK-NEXT:    ret
199  %red = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %v)
200  ret i1 %red
201}
202
203declare i1 @llvm.vector.reduce.xor.v4i1(<4 x i1>)
204
205define zeroext i1 @vreduce_xor_v4i1(<4 x i1> %v) {
206; CHECK-LABEL: vreduce_xor_v4i1:
207; CHECK:       # %bb.0:
208; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
209; CHECK-NEXT:    vcpop.m a0, v0
210; CHECK-NEXT:    andi a0, a0, 1
211; CHECK-NEXT:    ret
212  %red = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> %v)
213  ret i1 %red
214}
215
216declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1>)
217
218define zeroext i1 @vreduce_and_v4i1(<4 x i1> %v) {
219; CHECK-LABEL: vreduce_and_v4i1:
220; CHECK:       # %bb.0:
221; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
222; CHECK-NEXT:    vmnot.m v8, v0
223; CHECK-NEXT:    vcpop.m a0, v8
224; CHECK-NEXT:    seqz a0, a0
225; CHECK-NEXT:    ret
226  %red = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %v)
227  ret i1 %red
228}
229
230declare i1 @llvm.vector.reduce.umax.v4i1(<4 x i1>)
231
232define zeroext i1 @vreduce_umax_v4i1(<4 x i1> %v) {
233; CHECK-LABEL: vreduce_umax_v4i1:
234; CHECK:       # %bb.0:
235; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
236; CHECK-NEXT:    vcpop.m a0, v0
237; CHECK-NEXT:    snez a0, a0
238; CHECK-NEXT:    ret
239  %red = call i1 @llvm.vector.reduce.umax.v4i1(<4 x i1> %v)
240  ret i1 %red
241}
242
243declare i1 @llvm.vector.reduce.smax.v4i1(<4 x i1>)
244
245define zeroext i1 @vreduce_smax_v4i1(<4 x i1> %v) {
246; CHECK-LABEL: vreduce_smax_v4i1:
247; CHECK:       # %bb.0:
248; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
249; CHECK-NEXT:    vmnot.m v8, v0
250; CHECK-NEXT:    vcpop.m a0, v8
251; CHECK-NEXT:    seqz a0, a0
252; CHECK-NEXT:    ret
253  %red = call i1 @llvm.vector.reduce.smax.v4i1(<4 x i1> %v)
254  ret i1 %red
255}
256
257declare i1 @llvm.vector.reduce.umin.v4i1(<4 x i1>)
258
259define zeroext i1 @vreduce_umin_v4i1(<4 x i1> %v) {
260; CHECK-LABEL: vreduce_umin_v4i1:
261; CHECK:       # %bb.0:
262; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
263; CHECK-NEXT:    vmnot.m v8, v0
264; CHECK-NEXT:    vcpop.m a0, v8
265; CHECK-NEXT:    seqz a0, a0
266; CHECK-NEXT:    ret
267  %red = call i1 @llvm.vector.reduce.umin.v4i1(<4 x i1> %v)
268  ret i1 %red
269}
270
271declare i1 @llvm.vector.reduce.smin.v4i1(<4 x i1>)
272
273define zeroext i1 @vreduce_smin_v4i1(<4 x i1> %v) {
274; CHECK-LABEL: vreduce_smin_v4i1:
275; CHECK:       # %bb.0:
276; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
277; CHECK-NEXT:    vcpop.m a0, v0
278; CHECK-NEXT:    snez a0, a0
279; CHECK-NEXT:    ret
280  %red = call i1 @llvm.vector.reduce.smin.v4i1(<4 x i1> %v)
281  ret i1 %red
282}
283
284declare i1 @llvm.vector.reduce.or.v8i1(<8 x i1>)
285
286define zeroext i1 @vreduce_or_v8i1(<8 x i1> %v) {
287; CHECK-LABEL: vreduce_or_v8i1:
288; CHECK:       # %bb.0:
289; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
290; CHECK-NEXT:    vcpop.m a0, v0
291; CHECK-NEXT:    snez a0, a0
292; CHECK-NEXT:    ret
293  %red = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> %v)
294  ret i1 %red
295}
296
297declare i1 @llvm.vector.reduce.xor.v8i1(<8 x i1>)
298
299define zeroext i1 @vreduce_xor_v8i1(<8 x i1> %v) {
300; CHECK-LABEL: vreduce_xor_v8i1:
301; CHECK:       # %bb.0:
302; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
303; CHECK-NEXT:    vcpop.m a0, v0
304; CHECK-NEXT:    andi a0, a0, 1
305; CHECK-NEXT:    ret
306  %red = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> %v)
307  ret i1 %red
308}
309
310declare i1 @llvm.vector.reduce.and.v8i1(<8 x i1>)
311
312define zeroext i1 @vreduce_and_v8i1(<8 x i1> %v) {
313; CHECK-LABEL: vreduce_and_v8i1:
314; CHECK:       # %bb.0:
315; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
316; CHECK-NEXT:    vmnot.m v8, v0
317; CHECK-NEXT:    vcpop.m a0, v8
318; CHECK-NEXT:    seqz a0, a0
319; CHECK-NEXT:    ret
320  %red = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %v)
321  ret i1 %red
322}
323
324declare i1 @llvm.vector.reduce.umax.v8i1(<8 x i1>)
325
326define zeroext i1 @vreduce_umax_v8i1(<8 x i1> %v) {
327; CHECK-LABEL: vreduce_umax_v8i1:
328; CHECK:       # %bb.0:
329; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
330; CHECK-NEXT:    vcpop.m a0, v0
331; CHECK-NEXT:    snez a0, a0
332; CHECK-NEXT:    ret
333  %red = call i1 @llvm.vector.reduce.umax.v8i1(<8 x i1> %v)
334  ret i1 %red
335}
336
337declare i1 @llvm.vector.reduce.smax.v8i1(<8 x i1>)
338
339define zeroext i1 @vreduce_smax_v8i1(<8 x i1> %v) {
340; CHECK-LABEL: vreduce_smax_v8i1:
341; CHECK:       # %bb.0:
342; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
343; CHECK-NEXT:    vmnot.m v8, v0
344; CHECK-NEXT:    vcpop.m a0, v8
345; CHECK-NEXT:    seqz a0, a0
346; CHECK-NEXT:    ret
347  %red = call i1 @llvm.vector.reduce.smax.v8i1(<8 x i1> %v)
348  ret i1 %red
349}
350
351declare i1 @llvm.vector.reduce.umin.v8i1(<8 x i1>)
352
353define zeroext i1 @vreduce_umin_v8i1(<8 x i1> %v) {
354; CHECK-LABEL: vreduce_umin_v8i1:
355; CHECK:       # %bb.0:
356; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
357; CHECK-NEXT:    vmnot.m v8, v0
358; CHECK-NEXT:    vcpop.m a0, v8
359; CHECK-NEXT:    seqz a0, a0
360; CHECK-NEXT:    ret
361  %red = call i1 @llvm.vector.reduce.umin.v8i1(<8 x i1> %v)
362  ret i1 %red
363}
364
365declare i1 @llvm.vector.reduce.smin.v8i1(<8 x i1>)
366
367define zeroext i1 @vreduce_smin_v8i1(<8 x i1> %v) {
368; CHECK-LABEL: vreduce_smin_v8i1:
369; CHECK:       # %bb.0:
370; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
371; CHECK-NEXT:    vcpop.m a0, v0
372; CHECK-NEXT:    snez a0, a0
373; CHECK-NEXT:    ret
374  %red = call i1 @llvm.vector.reduce.smin.v8i1(<8 x i1> %v)
375  ret i1 %red
376}
377
378declare i1 @llvm.vector.reduce.or.v16i1(<16 x i1>)
379
380define zeroext i1 @vreduce_or_v16i1(<16 x i1> %v) {
381; CHECK-LABEL: vreduce_or_v16i1:
382; CHECK:       # %bb.0:
383; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
384; CHECK-NEXT:    vcpop.m a0, v0
385; CHECK-NEXT:    snez a0, a0
386; CHECK-NEXT:    ret
387  %red = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %v)
388  ret i1 %red
389}
390
391declare i1 @llvm.vector.reduce.xor.v16i1(<16 x i1>)
392
393define zeroext i1 @vreduce_xor_v16i1(<16 x i1> %v) {
394; CHECK-LABEL: vreduce_xor_v16i1:
395; CHECK:       # %bb.0:
396; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
397; CHECK-NEXT:    vcpop.m a0, v0
398; CHECK-NEXT:    andi a0, a0, 1
399; CHECK-NEXT:    ret
400  %red = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> %v)
401  ret i1 %red
402}
403
404declare i1 @llvm.vector.reduce.and.v16i1(<16 x i1>)
405
406define zeroext i1 @vreduce_and_v16i1(<16 x i1> %v) {
407; CHECK-LABEL: vreduce_and_v16i1:
408; CHECK:       # %bb.0:
409; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
410; CHECK-NEXT:    vmnot.m v8, v0
411; CHECK-NEXT:    vcpop.m a0, v8
412; CHECK-NEXT:    seqz a0, a0
413; CHECK-NEXT:    ret
414  %red = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %v)
415  ret i1 %red
416}
417
418declare i1 @llvm.vector.reduce.umax.v16i1(<16 x i1>)
419
420define zeroext i1 @vreduce_umax_v16i1(<16 x i1> %v) {
421; CHECK-LABEL: vreduce_umax_v16i1:
422; CHECK:       # %bb.0:
423; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
424; CHECK-NEXT:    vcpop.m a0, v0
425; CHECK-NEXT:    snez a0, a0
426; CHECK-NEXT:    ret
427  %red = call i1 @llvm.vector.reduce.umax.v16i1(<16 x i1> %v)
428  ret i1 %red
429}
430
431declare i1 @llvm.vector.reduce.smax.v16i1(<16 x i1>)
432
433define zeroext i1 @vreduce_smax_v16i1(<16 x i1> %v) {
434; CHECK-LABEL: vreduce_smax_v16i1:
435; CHECK:       # %bb.0:
436; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
437; CHECK-NEXT:    vmnot.m v8, v0
438; CHECK-NEXT:    vcpop.m a0, v8
439; CHECK-NEXT:    seqz a0, a0
440; CHECK-NEXT:    ret
441  %red = call i1 @llvm.vector.reduce.smax.v16i1(<16 x i1> %v)
442  ret i1 %red
443}
444
445declare i1 @llvm.vector.reduce.umin.v16i1(<16 x i1>)
446
447define zeroext i1 @vreduce_umin_v16i1(<16 x i1> %v) {
448; CHECK-LABEL: vreduce_umin_v16i1:
449; CHECK:       # %bb.0:
450; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
451; CHECK-NEXT:    vmnot.m v8, v0
452; CHECK-NEXT:    vcpop.m a0, v8
453; CHECK-NEXT:    seqz a0, a0
454; CHECK-NEXT:    ret
455  %red = call i1 @llvm.vector.reduce.umin.v16i1(<16 x i1> %v)
456  ret i1 %red
457}
458
459declare i1 @llvm.vector.reduce.smin.v16i1(<16 x i1>)
460
461define zeroext i1 @vreduce_smin_v16i1(<16 x i1> %v) {
462; CHECK-LABEL: vreduce_smin_v16i1:
463; CHECK:       # %bb.0:
464; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
465; CHECK-NEXT:    vcpop.m a0, v0
466; CHECK-NEXT:    snez a0, a0
467; CHECK-NEXT:    ret
468  %red = call i1 @llvm.vector.reduce.smin.v16i1(<16 x i1> %v)
469  ret i1 %red
470}
471
472declare i1 @llvm.vector.reduce.or.v32i1(<32 x i1>)
473
474define zeroext i1 @vreduce_or_v32i1(<32 x i1> %v) {
475; CHECK-LABEL: vreduce_or_v32i1:
476; CHECK:       # %bb.0:
477; CHECK-NEXT:    li a0, 32
478; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
479; CHECK-NEXT:    vcpop.m a0, v0
480; CHECK-NEXT:    snez a0, a0
481; CHECK-NEXT:    ret
482  %red = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> %v)
483  ret i1 %red
484}
485
486declare i1 @llvm.vector.reduce.xor.v32i1(<32 x i1>)
487
488define zeroext i1 @vreduce_xor_v32i1(<32 x i1> %v) {
489; CHECK-LABEL: vreduce_xor_v32i1:
490; CHECK:       # %bb.0:
491; CHECK-NEXT:    li a0, 32
492; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
493; CHECK-NEXT:    vcpop.m a0, v0
494; CHECK-NEXT:    andi a0, a0, 1
495; CHECK-NEXT:    ret
496  %red = call i1 @llvm.vector.reduce.xor.v32i1(<32 x i1> %v)
497  ret i1 %red
498}
499
500declare i1 @llvm.vector.reduce.and.v32i1(<32 x i1>)
501
502define zeroext i1 @vreduce_and_v32i1(<32 x i1> %v) {
503; CHECK-LABEL: vreduce_and_v32i1:
504; CHECK:       # %bb.0:
505; CHECK-NEXT:    li a0, 32
506; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
507; CHECK-NEXT:    vmnot.m v8, v0
508; CHECK-NEXT:    vcpop.m a0, v8
509; CHECK-NEXT:    seqz a0, a0
510; CHECK-NEXT:    ret
511  %red = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> %v)
512  ret i1 %red
513}
514
515declare i1 @llvm.vector.reduce.umax.v32i1(<32 x i1>)
516
517define zeroext i1 @vreduce_umax_v32i1(<32 x i1> %v) {
518; CHECK-LABEL: vreduce_umax_v32i1:
519; CHECK:       # %bb.0:
520; CHECK-NEXT:    li a0, 32
521; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
522; CHECK-NEXT:    vcpop.m a0, v0
523; CHECK-NEXT:    snez a0, a0
524; CHECK-NEXT:    ret
525  %red = call i1 @llvm.vector.reduce.umax.v32i1(<32 x i1> %v)
526  ret i1 %red
527}
528
529declare i1 @llvm.vector.reduce.smax.v32i1(<32 x i1>)
530
531define zeroext i1 @vreduce_smax_v32i1(<32 x i1> %v) {
532; CHECK-LABEL: vreduce_smax_v32i1:
533; CHECK:       # %bb.0:
534; CHECK-NEXT:    li a0, 32
535; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
536; CHECK-NEXT:    vmnot.m v8, v0
537; CHECK-NEXT:    vcpop.m a0, v8
538; CHECK-NEXT:    seqz a0, a0
539; CHECK-NEXT:    ret
540  %red = call i1 @llvm.vector.reduce.smax.v32i1(<32 x i1> %v)
541  ret i1 %red
542}
543
544declare i1 @llvm.vector.reduce.umin.v32i1(<32 x i1>)
545
546define zeroext i1 @vreduce_umin_v32i1(<32 x i1> %v) {
547; CHECK-LABEL: vreduce_umin_v32i1:
548; CHECK:       # %bb.0:
549; CHECK-NEXT:    li a0, 32
550; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
551; CHECK-NEXT:    vmnot.m v8, v0
552; CHECK-NEXT:    vcpop.m a0, v8
553; CHECK-NEXT:    seqz a0, a0
554; CHECK-NEXT:    ret
555  %red = call i1 @llvm.vector.reduce.umin.v32i1(<32 x i1> %v)
556  ret i1 %red
557}
558
559declare i1 @llvm.vector.reduce.smin.v32i1(<32 x i1>)
560
561define zeroext i1 @vreduce_smin_v32i1(<32 x i1> %v) {
562; CHECK-LABEL: vreduce_smin_v32i1:
563; CHECK:       # %bb.0:
564; CHECK-NEXT:    li a0, 32
565; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
566; CHECK-NEXT:    vcpop.m a0, v0
567; CHECK-NEXT:    snez a0, a0
568; CHECK-NEXT:    ret
569  %red = call i1 @llvm.vector.reduce.smin.v32i1(<32 x i1> %v)
570  ret i1 %red
571}
572
573declare i1 @llvm.vector.reduce.or.v64i1(<64 x i1>)
574
575define zeroext i1 @vreduce_or_v64i1(<64 x i1> %v) {
576; CHECK-LABEL: vreduce_or_v64i1:
577; CHECK:       # %bb.0:
578; CHECK-NEXT:    li a0, 64
579; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
580; CHECK-NEXT:    vcpop.m a0, v0
581; CHECK-NEXT:    snez a0, a0
582; CHECK-NEXT:    ret
583  %red = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> %v)
584  ret i1 %red
585}
586
587declare i1 @llvm.vector.reduce.xor.v64i1(<64 x i1>)
588
589define zeroext i1 @vreduce_xor_v64i1(<64 x i1> %v) {
590; CHECK-LABEL: vreduce_xor_v64i1:
591; CHECK:       # %bb.0:
592; CHECK-NEXT:    li a0, 64
593; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
594; CHECK-NEXT:    vcpop.m a0, v0
595; CHECK-NEXT:    andi a0, a0, 1
596; CHECK-NEXT:    ret
597  %red = call i1 @llvm.vector.reduce.xor.v64i1(<64 x i1> %v)
598  ret i1 %red
599}
600
601declare i1 @llvm.vector.reduce.and.v64i1(<64 x i1>)
602
603define zeroext i1 @vreduce_and_v64i1(<64 x i1> %v) {
604; CHECK-LABEL: vreduce_and_v64i1:
605; CHECK:       # %bb.0:
606; CHECK-NEXT:    li a0, 64
607; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
608; CHECK-NEXT:    vmnot.m v8, v0
609; CHECK-NEXT:    vcpop.m a0, v8
610; CHECK-NEXT:    seqz a0, a0
611; CHECK-NEXT:    ret
612  %red = call i1 @llvm.vector.reduce.and.v64i1(<64 x i1> %v)
613  ret i1 %red
614}
615
616declare i1 @llvm.vector.reduce.umax.v64i1(<64 x i1>)
617
618define zeroext i1 @vreduce_umax_v64i1(<64 x i1> %v) {
619; CHECK-LABEL: vreduce_umax_v64i1:
620; CHECK:       # %bb.0:
621; CHECK-NEXT:    li a0, 64
622; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
623; CHECK-NEXT:    vcpop.m a0, v0
624; CHECK-NEXT:    snez a0, a0
625; CHECK-NEXT:    ret
626  %red = call i1 @llvm.vector.reduce.umax.v64i1(<64 x i1> %v)
627  ret i1 %red
628}
629
630declare i1 @llvm.vector.reduce.smax.v64i1(<64 x i1>)
631
632define zeroext i1 @vreduce_smax_v64i1(<64 x i1> %v) {
633; CHECK-LABEL: vreduce_smax_v64i1:
634; CHECK:       # %bb.0:
635; CHECK-NEXT:    li a0, 64
636; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
637; CHECK-NEXT:    vmnot.m v8, v0
638; CHECK-NEXT:    vcpop.m a0, v8
639; CHECK-NEXT:    seqz a0, a0
640; CHECK-NEXT:    ret
641  %red = call i1 @llvm.vector.reduce.smax.v64i1(<64 x i1> %v)
642  ret i1 %red
643}
644
645declare i1 @llvm.vector.reduce.umin.v64i1(<64 x i1>)
646
647define zeroext i1 @vreduce_umin_v64i1(<64 x i1> %v) {
648; CHECK-LABEL: vreduce_umin_v64i1:
649; CHECK:       # %bb.0:
650; CHECK-NEXT:    li a0, 64
651; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
652; CHECK-NEXT:    vmnot.m v8, v0
653; CHECK-NEXT:    vcpop.m a0, v8
654; CHECK-NEXT:    seqz a0, a0
655; CHECK-NEXT:    ret
656  %red = call i1 @llvm.vector.reduce.umin.v64i1(<64 x i1> %v)
657  ret i1 %red
658}
659
660declare i1 @llvm.vector.reduce.smin.v64i1(<64 x i1>)
661
662define zeroext i1 @vreduce_smin_v64i1(<64 x i1> %v) {
663; CHECK-LABEL: vreduce_smin_v64i1:
664; CHECK:       # %bb.0:
665; CHECK-NEXT:    li a0, 64
666; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
667; CHECK-NEXT:    vcpop.m a0, v0
668; CHECK-NEXT:    snez a0, a0
669; CHECK-NEXT:    ret
670  %red = call i1 @llvm.vector.reduce.smin.v64i1(<64 x i1> %v)
671  ret i1 %red
672}
673
674declare i1 @llvm.vector.reduce.add.v1i1(<1 x i1>)
675
676define zeroext i1 @vreduce_add_v1i1(<1 x i1> %v) {
677; CHECK-LABEL: vreduce_add_v1i1:
678; CHECK:       # %bb.0:
679; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
680; CHECK-NEXT:    vfirst.m a0, v0
681; CHECK-NEXT:    seqz a0, a0
682; CHECK-NEXT:    ret
683  %red = call i1 @llvm.vector.reduce.add.v1i1(<1 x i1> %v)
684  ret i1 %red
685}
686
687declare i1 @llvm.vector.reduce.add.v2i1(<2 x i1>)
688
689define zeroext i1 @vreduce_add_v2i1(<2 x i1> %v) {
690; CHECK-LABEL: vreduce_add_v2i1:
691; CHECK:       # %bb.0:
692; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
693; CHECK-NEXT:    vcpop.m a0, v0
694; CHECK-NEXT:    andi a0, a0, 1
695; CHECK-NEXT:    ret
696  %red = call i1 @llvm.vector.reduce.add.v2i1(<2 x i1> %v)
697  ret i1 %red
698}
699
700declare i1 @llvm.vector.reduce.add.v4i1(<4 x i1>)
701
702define zeroext i1 @vreduce_add_v4i1(<4 x i1> %v) {
703; CHECK-LABEL: vreduce_add_v4i1:
704; CHECK:       # %bb.0:
705; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
706; CHECK-NEXT:    vcpop.m a0, v0
707; CHECK-NEXT:    andi a0, a0, 1
708; CHECK-NEXT:    ret
709  %red = call i1 @llvm.vector.reduce.add.v4i1(<4 x i1> %v)
710  ret i1 %red
711}
712
713declare i1 @llvm.vector.reduce.add.v8i1(<8 x i1>)
714
715define zeroext i1 @vreduce_add_v8i1(<8 x i1> %v) {
716; CHECK-LABEL: vreduce_add_v8i1:
717; CHECK:       # %bb.0:
718; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
719; CHECK-NEXT:    vcpop.m a0, v0
720; CHECK-NEXT:    andi a0, a0, 1
721; CHECK-NEXT:    ret
722  %red = call i1 @llvm.vector.reduce.add.v8i1(<8 x i1> %v)
723  ret i1 %red
724}
725
726declare i1 @llvm.vector.reduce.add.v16i1(<16 x i1>)
727
728define zeroext i1 @vreduce_add_v16i1(<16 x i1> %v) {
729; CHECK-LABEL: vreduce_add_v16i1:
730; CHECK:       # %bb.0:
731; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
732; CHECK-NEXT:    vcpop.m a0, v0
733; CHECK-NEXT:    andi a0, a0, 1
734; CHECK-NEXT:    ret
735  %red = call i1 @llvm.vector.reduce.add.v16i1(<16 x i1> %v)
736  ret i1 %red
737}
738
739declare i1 @llvm.vector.reduce.add.v32i1(<32 x i1>)
740
741define zeroext i1 @vreduce_add_v32i1(<32 x i1> %v) {
742; CHECK-LABEL: vreduce_add_v32i1:
743; CHECK:       # %bb.0:
744; CHECK-NEXT:    li a0, 32
745; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
746; CHECK-NEXT:    vcpop.m a0, v0
747; CHECK-NEXT:    andi a0, a0, 1
748; CHECK-NEXT:    ret
749  %red = call i1 @llvm.vector.reduce.add.v32i1(<32 x i1> %v)
750  ret i1 %red
751}
752
753declare i1 @llvm.vector.reduce.add.v64i1(<64 x i1>)
754
755define zeroext i1 @vreduce_add_v64i1(<64 x i1> %v) {
756; CHECK-LABEL: vreduce_add_v64i1:
757; CHECK:       # %bb.0:
758; CHECK-NEXT:    li a0, 64
759; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
760; CHECK-NEXT:    vcpop.m a0, v0
761; CHECK-NEXT:    andi a0, a0, 1
762; CHECK-NEXT:    ret
763  %red = call i1 @llvm.vector.reduce.add.v64i1(<64 x i1> %v)
764  ret i1 %red
765}
766
767declare i1 @llvm.vector.reduce.or.v128i1(<128 x i1>)
768
769define zeroext i1 @vreduce_or_v128i1(<128 x i1> %v) {
770; CHECK-LABEL: vreduce_or_v128i1:
771; CHECK:       # %bb.0:
772; CHECK-NEXT:    li a0, 128
773; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
774; CHECK-NEXT:    vcpop.m a0, v0
775; CHECK-NEXT:    snez a0, a0
776; CHECK-NEXT:    ret
777  %red = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> %v)
778  ret i1 %red
779}
780
781declare i1 @llvm.vector.reduce.xor.v128i1(<128 x i1>)
782
783define zeroext i1 @vreduce_xor_v128i1(<128 x i1> %v) {
784; CHECK-LABEL: vreduce_xor_v128i1:
785; CHECK:       # %bb.0:
786; CHECK-NEXT:    li a0, 128
787; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
788; CHECK-NEXT:    vcpop.m a0, v0
789; CHECK-NEXT:    andi a0, a0, 1
790; CHECK-NEXT:    ret
791  %red = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> %v)
792  ret i1 %red
793}
794
795declare i1 @llvm.vector.reduce.and.v128i1(<128 x i1>)
796
797define zeroext i1 @vreduce_and_v128i1(<128 x i1> %v) {
798; CHECK-LABEL: vreduce_and_v128i1:
799; CHECK:       # %bb.0:
800; CHECK-NEXT:    li a0, 128
801; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
802; CHECK-NEXT:    vmnot.m v8, v0
803; CHECK-NEXT:    vcpop.m a0, v8
804; CHECK-NEXT:    seqz a0, a0
805; CHECK-NEXT:    ret
806  %red = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> %v)
807  ret i1 %red
808}
809
810declare i1 @llvm.vector.reduce.umax.v128i1(<128 x i1>)
811
812define zeroext i1 @vreduce_umax_v128i1(<128 x i1> %v) {
813; CHECK-LABEL: vreduce_umax_v128i1:
814; CHECK:       # %bb.0:
815; CHECK-NEXT:    li a0, 128
816; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
817; CHECK-NEXT:    vcpop.m a0, v0
818; CHECK-NEXT:    snez a0, a0
819; CHECK-NEXT:    ret
820  %red = call i1 @llvm.vector.reduce.umax.v128i1(<128 x i1> %v)
821  ret i1 %red
822}
823
824declare i1 @llvm.vector.reduce.smax.v128i1(<128 x i1>)
825
826define zeroext i1 @vreduce_smax_v128i1(<128 x i1> %v) {
827; CHECK-LABEL: vreduce_smax_v128i1:
828; CHECK:       # %bb.0:
829; CHECK-NEXT:    li a0, 128
830; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
831; CHECK-NEXT:    vmnot.m v8, v0
832; CHECK-NEXT:    vcpop.m a0, v8
833; CHECK-NEXT:    seqz a0, a0
834; CHECK-NEXT:    ret
835  %red = call i1 @llvm.vector.reduce.smax.v128i1(<128 x i1> %v)
836  ret i1 %red
837}
838
839declare i1 @llvm.vector.reduce.umin.v128i1(<128 x i1>)
840
841define zeroext i1 @vreduce_umin_v128i1(<128 x i1> %v) {
842; CHECK-LABEL: vreduce_umin_v128i1:
843; CHECK:       # %bb.0:
844; CHECK-NEXT:    li a0, 128
845; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
846; CHECK-NEXT:    vmnot.m v8, v0
847; CHECK-NEXT:    vcpop.m a0, v8
848; CHECK-NEXT:    seqz a0, a0
849; CHECK-NEXT:    ret
850  %red = call i1 @llvm.vector.reduce.umin.v128i1(<128 x i1> %v)
851  ret i1 %red
852}
853
854declare i1 @llvm.vector.reduce.smin.v128i1(<128 x i1>)
855
856define zeroext i1 @vreduce_smin_v128i1(<128 x i1> %v) {
857; CHECK-LABEL: vreduce_smin_v128i1:
858; CHECK:       # %bb.0:
859; CHECK-NEXT:    li a0, 128
860; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
861; CHECK-NEXT:    vcpop.m a0, v0
862; CHECK-NEXT:    snez a0, a0
863; CHECK-NEXT:    ret
864  %red = call i1 @llvm.vector.reduce.smin.v128i1(<128 x i1> %v)
865  ret i1 %red
866}
867
868declare i1 @llvm.vector.reduce.or.v256i1(<256 x i1>)
869
870define zeroext i1 @vreduce_or_v256i1(<256 x i1> %v) {
871; CHECK-LABEL: vreduce_or_v256i1:
872; CHECK:       # %bb.0:
873; CHECK-NEXT:    li a0, 128
874; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
875; CHECK-NEXT:    vmor.mm v8, v0, v8
876; CHECK-NEXT:    vcpop.m a0, v8
877; CHECK-NEXT:    snez a0, a0
878; CHECK-NEXT:    ret
879  %red = call i1 @llvm.vector.reduce.or.v256i1(<256 x i1> %v)
880  ret i1 %red
881}
882
883declare i1 @llvm.vector.reduce.xor.v256i1(<256 x i1>)
884
885define zeroext i1 @vreduce_xor_v256i1(<256 x i1> %v) {
886; CHECK-LABEL: vreduce_xor_v256i1:
887; CHECK:       # %bb.0:
888; CHECK-NEXT:    li a0, 128
889; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
890; CHECK-NEXT:    vmxor.mm v8, v0, v8
891; CHECK-NEXT:    vcpop.m a0, v8
892; CHECK-NEXT:    andi a0, a0, 1
893; CHECK-NEXT:    ret
894  %red = call i1 @llvm.vector.reduce.xor.v256i1(<256 x i1> %v)
895  ret i1 %red
896}
897
898declare i1 @llvm.vector.reduce.and.v256i1(<256 x i1>)
899
900define zeroext i1 @vreduce_and_v256i1(<256 x i1> %v) {
901; CHECK-LABEL: vreduce_and_v256i1:
902; CHECK:       # %bb.0:
903; CHECK-NEXT:    li a0, 128
904; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
905; CHECK-NEXT:    vmnand.mm v8, v0, v8
906; CHECK-NEXT:    vcpop.m a0, v8
907; CHECK-NEXT:    seqz a0, a0
908; CHECK-NEXT:    ret
909  %red = call i1 @llvm.vector.reduce.and.v256i1(<256 x i1> %v)
910  ret i1 %red
911}
912
913declare i1 @llvm.vector.reduce.umax.v256i1(<256 x i1>)
914
915define zeroext i1 @vreduce_umax_v256i1(<256 x i1> %v) {
916; CHECK-LABEL: vreduce_umax_v256i1:
917; CHECK:       # %bb.0:
918; CHECK-NEXT:    li a0, 128
919; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
920; CHECK-NEXT:    vmor.mm v8, v0, v8
921; CHECK-NEXT:    vcpop.m a0, v8
922; CHECK-NEXT:    snez a0, a0
923; CHECK-NEXT:    ret
924  %red = call i1 @llvm.vector.reduce.umax.v256i1(<256 x i1> %v)
925  ret i1 %red
926}
927
928declare i1 @llvm.vector.reduce.smax.v256i1(<256 x i1>)
929
930define zeroext i1 @vreduce_smax_v256i1(<256 x i1> %v) {
931; CHECK-LABEL: vreduce_smax_v256i1:
932; CHECK:       # %bb.0:
933; CHECK-NEXT:    li a0, 128
934; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
935; CHECK-NEXT:    vmnand.mm v8, v0, v8
936; CHECK-NEXT:    vcpop.m a0, v8
937; CHECK-NEXT:    seqz a0, a0
938; CHECK-NEXT:    ret
939  %red = call i1 @llvm.vector.reduce.smax.v256i1(<256 x i1> %v)
940  ret i1 %red
941}
942
943declare i1 @llvm.vector.reduce.umin.v256i1(<256 x i1>)
944
945define zeroext i1 @vreduce_umin_v256i1(<256 x i1> %v) {
946; CHECK-LABEL: vreduce_umin_v256i1:
947; CHECK:       # %bb.0:
948; CHECK-NEXT:    li a0, 128
949; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
950; CHECK-NEXT:    vmnand.mm v8, v0, v8
951; CHECK-NEXT:    vcpop.m a0, v8
952; CHECK-NEXT:    seqz a0, a0
953; CHECK-NEXT:    ret
954  %red = call i1 @llvm.vector.reduce.umin.v256i1(<256 x i1> %v)
955  ret i1 %red
956}
957
958declare i1 @llvm.vector.reduce.smin.v256i1(<256 x i1>)
959
960define zeroext i1 @vreduce_smin_v256i1(<256 x i1> %v) {
961; CHECK-LABEL: vreduce_smin_v256i1:
962; CHECK:       # %bb.0:
963; CHECK-NEXT:    li a0, 128
964; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
965; CHECK-NEXT:    vmor.mm v8, v0, v8
966; CHECK-NEXT:    vcpop.m a0, v8
967; CHECK-NEXT:    snez a0, a0
968; CHECK-NEXT:    ret
969  %red = call i1 @llvm.vector.reduce.smin.v256i1(<256 x i1> %v)
970  ret i1 %red
971}
972
973declare i1 @llvm.vector.reduce.or.v512i1(<512 x i1>)
974
975define zeroext i1 @vreduce_or_v512i1(<512 x i1> %v) {
976; CHECK-LABEL: vreduce_or_v512i1:
977; CHECK:       # %bb.0:
978; CHECK-NEXT:    li a0, 128
979; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
980; CHECK-NEXT:    vmor.mm v8, v8, v10
981; CHECK-NEXT:    vmor.mm v9, v0, v9
982; CHECK-NEXT:    vmor.mm v8, v9, v8
983; CHECK-NEXT:    vcpop.m a0, v8
984; CHECK-NEXT:    snez a0, a0
985; CHECK-NEXT:    ret
986  %red = call i1 @llvm.vector.reduce.or.v512i1(<512 x i1> %v)
987  ret i1 %red
988}
989
990declare i1 @llvm.vector.reduce.xor.v512i1(<512 x i1>)
991
992define zeroext i1 @vreduce_xor_v512i1(<512 x i1> %v) {
993; CHECK-LABEL: vreduce_xor_v512i1:
994; CHECK:       # %bb.0:
995; CHECK-NEXT:    li a0, 128
996; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
997; CHECK-NEXT:    vmxor.mm v8, v8, v10
998; CHECK-NEXT:    vmxor.mm v9, v0, v9
999; CHECK-NEXT:    vmxor.mm v8, v9, v8
1000; CHECK-NEXT:    vcpop.m a0, v8
1001; CHECK-NEXT:    andi a0, a0, 1
1002; CHECK-NEXT:    ret
1003  %red = call i1 @llvm.vector.reduce.xor.v512i1(<512 x i1> %v)
1004  ret i1 %red
1005}
1006
1007declare i1 @llvm.vector.reduce.and.v512i1(<512 x i1>)
1008
1009define zeroext i1 @vreduce_and_v512i1(<512 x i1> %v) {
1010; CHECK-LABEL: vreduce_and_v512i1:
1011; CHECK:       # %bb.0:
1012; CHECK-NEXT:    li a0, 128
1013; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
1014; CHECK-NEXT:    vmand.mm v8, v8, v10
1015; CHECK-NEXT:    vmand.mm v9, v0, v9
1016; CHECK-NEXT:    vmnand.mm v8, v9, v8
1017; CHECK-NEXT:    vcpop.m a0, v8
1018; CHECK-NEXT:    seqz a0, a0
1019; CHECK-NEXT:    ret
1020  %red = call i1 @llvm.vector.reduce.and.v512i1(<512 x i1> %v)
1021  ret i1 %red
1022}
1023
1024declare i1 @llvm.vector.reduce.umax.v512i1(<512 x i1>)
1025
1026define zeroext i1 @vreduce_umax_v512i1(<512 x i1> %v) {
1027; CHECK-LABEL: vreduce_umax_v512i1:
1028; CHECK:       # %bb.0:
1029; CHECK-NEXT:    li a0, 128
1030; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
1031; CHECK-NEXT:    vmor.mm v8, v8, v10
1032; CHECK-NEXT:    vmor.mm v9, v0, v9
1033; CHECK-NEXT:    vmor.mm v8, v9, v8
1034; CHECK-NEXT:    vcpop.m a0, v8
1035; CHECK-NEXT:    snez a0, a0
1036; CHECK-NEXT:    ret
1037  %red = call i1 @llvm.vector.reduce.umax.v512i1(<512 x i1> %v)
1038  ret i1 %red
1039}
1040
1041declare i1 @llvm.vector.reduce.smax.v512i1(<512 x i1>)
1042
1043define zeroext i1 @vreduce_smax_v512i1(<512 x i1> %v) {
1044; CHECK-LABEL: vreduce_smax_v512i1:
1045; CHECK:       # %bb.0:
1046; CHECK-NEXT:    li a0, 128
1047; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
1048; CHECK-NEXT:    vmand.mm v8, v8, v10
1049; CHECK-NEXT:    vmand.mm v9, v0, v9
1050; CHECK-NEXT:    vmnand.mm v8, v9, v8
1051; CHECK-NEXT:    vcpop.m a0, v8
1052; CHECK-NEXT:    seqz a0, a0
1053; CHECK-NEXT:    ret
1054  %red = call i1 @llvm.vector.reduce.smax.v512i1(<512 x i1> %v)
1055  ret i1 %red
1056}
1057
1058declare i1 @llvm.vector.reduce.umin.v512i1(<512 x i1>)
1059
1060define zeroext i1 @vreduce_umin_v512i1(<512 x i1> %v) {
1061; CHECK-LABEL: vreduce_umin_v512i1:
1062; CHECK:       # %bb.0:
1063; CHECK-NEXT:    li a0, 128
1064; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
1065; CHECK-NEXT:    vmand.mm v8, v8, v10
1066; CHECK-NEXT:    vmand.mm v9, v0, v9
1067; CHECK-NEXT:    vmnand.mm v8, v9, v8
1068; CHECK-NEXT:    vcpop.m a0, v8
1069; CHECK-NEXT:    seqz a0, a0
1070; CHECK-NEXT:    ret
1071  %red = call i1 @llvm.vector.reduce.umin.v512i1(<512 x i1> %v)
1072  ret i1 %red
1073}
1074
1075declare i1 @llvm.vector.reduce.smin.v512i1(<512 x i1>)
1076
1077define zeroext i1 @vreduce_smin_v512i1(<512 x i1> %v) {
1078; CHECK-LABEL: vreduce_smin_v512i1:
1079; CHECK:       # %bb.0:
1080; CHECK-NEXT:    li a0, 128
1081; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
1082; CHECK-NEXT:    vmor.mm v8, v8, v10
1083; CHECK-NEXT:    vmor.mm v9, v0, v9
1084; CHECK-NEXT:    vmor.mm v8, v9, v8
1085; CHECK-NEXT:    vcpop.m a0, v8
1086; CHECK-NEXT:    snez a0, a0
1087; CHECK-NEXT:    ret
1088  %red = call i1 @llvm.vector.reduce.smin.v512i1(<512 x i1> %v)
1089  ret i1 %red
1090}
1091
1092declare i1 @llvm.vector.reduce.or.v1024i1(<1024 x i1>)
1093
1094define zeroext i1 @vreduce_or_v1024i1(<1024 x i1> %v) {
1095; CHECK-LABEL: vreduce_or_v1024i1:
1096; CHECK:       # %bb.0:
1097; CHECK-NEXT:    li a0, 128
1098; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
1099; CHECK-NEXT:    vmor.mm v10, v10, v14
1100; CHECK-NEXT:    vmor.mm v8, v8, v12
1101; CHECK-NEXT:    vmor.mm v9, v9, v13
1102; CHECK-NEXT:    vmor.mm v11, v0, v11
1103; CHECK-NEXT:    vmor.mm v8, v8, v10
1104; CHECK-NEXT:    vmor.mm v9, v11, v9
1105; CHECK-NEXT:    vmor.mm v8, v9, v8
1106; CHECK-NEXT:    vcpop.m a0, v8
1107; CHECK-NEXT:    snez a0, a0
1108; CHECK-NEXT:    ret
1109  %red = call i1 @llvm.vector.reduce.or.v1024i1(<1024 x i1> %v)
1110  ret i1 %red
1111}
1112
1113declare i1 @llvm.vector.reduce.xor.v1024i1(<1024 x i1>)
1114
1115define zeroext i1 @vreduce_xor_v1024i1(<1024 x i1> %v) {
1116; CHECK-LABEL: vreduce_xor_v1024i1:
1117; CHECK:       # %bb.0:
1118; CHECK-NEXT:    li a0, 128
1119; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
1120; CHECK-NEXT:    vmxor.mm v10, v10, v14
1121; CHECK-NEXT:    vmxor.mm v8, v8, v12
1122; CHECK-NEXT:    vmxor.mm v9, v9, v13
1123; CHECK-NEXT:    vmxor.mm v11, v0, v11
1124; CHECK-NEXT:    vmxor.mm v8, v8, v10
1125; CHECK-NEXT:    vmxor.mm v9, v11, v9
1126; CHECK-NEXT:    vmxor.mm v8, v9, v8
1127; CHECK-NEXT:    vcpop.m a0, v8
1128; CHECK-NEXT:    andi a0, a0, 1
1129; CHECK-NEXT:    ret
1130  %red = call i1 @llvm.vector.reduce.xor.v1024i1(<1024 x i1> %v)
1131  ret i1 %red
1132}
1133
1134declare i1 @llvm.vector.reduce.and.v1024i1(<1024 x i1>)
1135
1136define zeroext i1 @vreduce_and_v1024i1(<1024 x i1> %v) {
1137; CHECK-LABEL: vreduce_and_v1024i1:
1138; CHECK:       # %bb.0:
1139; CHECK-NEXT:    li a0, 128
1140; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
1141; CHECK-NEXT:    vmand.mm v10, v10, v14
1142; CHECK-NEXT:    vmand.mm v8, v8, v12
1143; CHECK-NEXT:    vmand.mm v9, v9, v13
1144; CHECK-NEXT:    vmand.mm v11, v0, v11
1145; CHECK-NEXT:    vmand.mm v8, v8, v10
1146; CHECK-NEXT:    vmand.mm v9, v11, v9
1147; CHECK-NEXT:    vmnand.mm v8, v9, v8
1148; CHECK-NEXT:    vcpop.m a0, v8
1149; CHECK-NEXT:    seqz a0, a0
1150; CHECK-NEXT:    ret
1151  %red = call i1 @llvm.vector.reduce.and.v1024i1(<1024 x i1> %v)
1152  ret i1 %red
1153}
1154
1155declare i1 @llvm.vector.reduce.umax.v1024i1(<1024 x i1>)
1156
1157define zeroext i1 @vreduce_umax_v1024i1(<1024 x i1> %v) {
1158; CHECK-LABEL: vreduce_umax_v1024i1:
1159; CHECK:       # %bb.0:
1160; CHECK-NEXT:    li a0, 128
1161; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
1162; CHECK-NEXT:    vmor.mm v10, v10, v14
1163; CHECK-NEXT:    vmor.mm v8, v8, v12
1164; CHECK-NEXT:    vmor.mm v9, v9, v13
1165; CHECK-NEXT:    vmor.mm v11, v0, v11
1166; CHECK-NEXT:    vmor.mm v8, v8, v10
1167; CHECK-NEXT:    vmor.mm v9, v11, v9
1168; CHECK-NEXT:    vmor.mm v8, v9, v8
1169; CHECK-NEXT:    vcpop.m a0, v8
1170; CHECK-NEXT:    snez a0, a0
1171; CHECK-NEXT:    ret
1172  %red = call i1 @llvm.vector.reduce.umax.v1024i1(<1024 x i1> %v)
1173  ret i1 %red
1174}
1175
1176declare i1 @llvm.vector.reduce.smax.v1024i1(<1024 x i1>)
1177
1178define zeroext i1 @vreduce_smax_v1024i1(<1024 x i1> %v) {
1179; CHECK-LABEL: vreduce_smax_v1024i1:
1180; CHECK:       # %bb.0:
1181; CHECK-NEXT:    li a0, 128
1182; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
1183; CHECK-NEXT:    vmand.mm v10, v10, v14
1184; CHECK-NEXT:    vmand.mm v8, v8, v12
1185; CHECK-NEXT:    vmand.mm v9, v9, v13
1186; CHECK-NEXT:    vmand.mm v11, v0, v11
1187; CHECK-NEXT:    vmand.mm v8, v8, v10
1188; CHECK-NEXT:    vmand.mm v9, v11, v9
1189; CHECK-NEXT:    vmnand.mm v8, v9, v8
1190; CHECK-NEXT:    vcpop.m a0, v8
1191; CHECK-NEXT:    seqz a0, a0
1192; CHECK-NEXT:    ret
1193  %red = call i1 @llvm.vector.reduce.smax.v1024i1(<1024 x i1> %v)
1194  ret i1 %red
1195}
1196
1197declare i1 @llvm.vector.reduce.umin.v1024i1(<1024 x i1>)
1198
1199define zeroext i1 @vreduce_umin_v1024i1(<1024 x i1> %v) {
1200; CHECK-LABEL: vreduce_umin_v1024i1:
1201; CHECK:       # %bb.0:
1202; CHECK-NEXT:    li a0, 128
1203; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
1204; CHECK-NEXT:    vmand.mm v10, v10, v14
1205; CHECK-NEXT:    vmand.mm v8, v8, v12
1206; CHECK-NEXT:    vmand.mm v9, v9, v13
1207; CHECK-NEXT:    vmand.mm v11, v0, v11
1208; CHECK-NEXT:    vmand.mm v8, v8, v10
1209; CHECK-NEXT:    vmand.mm v9, v11, v9
1210; CHECK-NEXT:    vmnand.mm v8, v9, v8
1211; CHECK-NEXT:    vcpop.m a0, v8
1212; CHECK-NEXT:    seqz a0, a0
1213; CHECK-NEXT:    ret
1214  %red = call i1 @llvm.vector.reduce.umin.v1024i1(<1024 x i1> %v)
1215  ret i1 %red
1216}
1217
1218declare i1 @llvm.vector.reduce.smin.v1024i1(<1024 x i1>)
1219
1220define zeroext i1 @vreduce_smin_v1024i1(<1024 x i1> %v) {
1221; CHECK-LABEL: vreduce_smin_v1024i1:
1222; CHECK:       # %bb.0:
1223; CHECK-NEXT:    li a0, 128
1224; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma
1225; CHECK-NEXT:    vmor.mm v10, v10, v14
1226; CHECK-NEXT:    vmor.mm v8, v8, v12
1227; CHECK-NEXT:    vmor.mm v9, v9, v13
1228; CHECK-NEXT:    vmor.mm v11, v0, v11
1229; CHECK-NEXT:    vmor.mm v8, v8, v10
1230; CHECK-NEXT:    vmor.mm v9, v11, v9
1231; CHECK-NEXT:    vmor.mm v8, v9, v8
1232; CHECK-NEXT:    vcpop.m a0, v8
1233; CHECK-NEXT:    snez a0, a0
1234; CHECK-NEXT:    ret
1235  %red = call i1 @llvm.vector.reduce.smin.v1024i1(<1024 x i1> %v)
1236  ret i1 %red
1237}
1238