xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll (revision ed8ebad6eb84af60d1c1a8826f55d4d347d2e7bd) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v \
3; RUN:   -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v \
5; RUN:   -verify-machineinstrs < %s | FileCheck %s
6
7declare void @llvm.vp.store.v2i8.p0(<2 x i8>, ptr, <2 x i1>, i32)
8
9define void @vpstore_v2i8(<2 x i8> %val, ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {
10; CHECK-LABEL: vpstore_v2i8:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
13; CHECK-NEXT:    vse8.v v8, (a0), v0.t
14; CHECK-NEXT:    ret
15  call void @llvm.vp.store.v2i8.p0(<2 x i8> %val, ptr %ptr, <2 x i1> %m, i32 %evl)
16  ret void
17}
18
19declare void @llvm.vp.store.v4i8.p0(<4 x i8>, ptr, <4 x i1>, i32)
20
21define void @vpstore_v4i8(<4 x i8> %val, ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {
22; CHECK-LABEL: vpstore_v4i8:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
25; CHECK-NEXT:    vse8.v v8, (a0), v0.t
26; CHECK-NEXT:    ret
27  call void @llvm.vp.store.v4i8.p0(<4 x i8> %val, ptr %ptr, <4 x i1> %m, i32 %evl)
28  ret void
29}
30
31declare void @llvm.vp.store.v8i7.v8i7.p0(<8 x i7>, ptr, <8 x i1>, i32)
32
33define void @vpstore_v8i7(<8 x i7> %val, ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
34; CHECK-LABEL: vpstore_v8i7:
35; CHECK:       # %bb.0:
36; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
37; CHECK-NEXT:    vse8.v v8, (a0), v0.t
38; CHECK-NEXT:    ret
39  call void @llvm.vp.store.v8i7.v8i7.p0(<8 x i7> %val, ptr %ptr, <8 x i1> %m, i32 %evl)
40  ret void
41}
42
43declare void @llvm.vp.store.v8i8.p0(<8 x i8>, ptr, <8 x i1>, i32)
44
45define void @vpstore_v8i8(<8 x i8> %val, ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
46; CHECK-LABEL: vpstore_v8i8:
47; CHECK:       # %bb.0:
48; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
49; CHECK-NEXT:    vse8.v v8, (a0), v0.t
50; CHECK-NEXT:    ret
51  call void @llvm.vp.store.v8i8.p0(<8 x i8> %val, ptr %ptr, <8 x i1> %m, i32 %evl)
52  ret void
53}
54
55declare void @llvm.vp.store.v2i16.p0(<2 x i16>, ptr, <2 x i1>, i32)
56
57define void @vpstore_v2i16(<2 x i16> %val, ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {
58; CHECK-LABEL: vpstore_v2i16:
59; CHECK:       # %bb.0:
60; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
61; CHECK-NEXT:    vse16.v v8, (a0), v0.t
62; CHECK-NEXT:    ret
63  call void @llvm.vp.store.v2i16.p0(<2 x i16> %val, ptr %ptr, <2 x i1> %m, i32 %evl)
64  ret void
65}
66
67declare void @llvm.vp.store.v4i16.p0(<4 x i16>, ptr, <4 x i1>, i32)
68
69define void @vpstore_v4i16(<4 x i16> %val, ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {
70; CHECK-LABEL: vpstore_v4i16:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
73; CHECK-NEXT:    vse16.v v8, (a0), v0.t
74; CHECK-NEXT:    ret
75  call void @llvm.vp.store.v4i16.p0(<4 x i16> %val, ptr %ptr, <4 x i1> %m, i32 %evl)
76  ret void
77}
78
79declare void @llvm.vp.store.v8i16.p0(<8 x i16>, ptr, <8 x i1>, i32)
80
81define void @vpstore_v8i16(<8 x i16> %val, ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
82; CHECK-LABEL: vpstore_v8i16:
83; CHECK:       # %bb.0:
84; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
85; CHECK-NEXT:    vse16.v v8, (a0), v0.t
86; CHECK-NEXT:    ret
87  call void @llvm.vp.store.v8i16.p0(<8 x i16> %val, ptr %ptr, <8 x i1> %m, i32 %evl)
88  ret void
89}
90
91declare void @llvm.vp.store.v2i32.p0(<2 x i32>, ptr, <2 x i1>, i32)
92
93define void @vpstore_v2i32(<2 x i32> %val, ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {
94; CHECK-LABEL: vpstore_v2i32:
95; CHECK:       # %bb.0:
96; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
97; CHECK-NEXT:    vse32.v v8, (a0), v0.t
98; CHECK-NEXT:    ret
99  call void @llvm.vp.store.v2i32.p0(<2 x i32> %val, ptr %ptr, <2 x i1> %m, i32 %evl)
100  ret void
101}
102
103declare void @llvm.vp.store.v4i32.p0(<4 x i32>, ptr, <4 x i1>, i32)
104
105define void @vpstore_v4i32(<4 x i32> %val, ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {
106; CHECK-LABEL: vpstore_v4i32:
107; CHECK:       # %bb.0:
108; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
109; CHECK-NEXT:    vse32.v v8, (a0), v0.t
110; CHECK-NEXT:    ret
111  call void @llvm.vp.store.v4i32.p0(<4 x i32> %val, ptr %ptr, <4 x i1> %m, i32 %evl)
112  ret void
113}
114
115declare void @llvm.vp.store.v8i32.p0(<8 x i32>, ptr, <8 x i1>, i32)
116
117define void @vpstore_v8i32(<8 x i32> %val, ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
118; CHECK-LABEL: vpstore_v8i32:
119; CHECK:       # %bb.0:
120; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
121; CHECK-NEXT:    vse32.v v8, (a0), v0.t
122; CHECK-NEXT:    ret
123  call void @llvm.vp.store.v8i32.p0(<8 x i32> %val, ptr %ptr, <8 x i1> %m, i32 %evl)
124  ret void
125}
126
127declare void @llvm.vp.store.v2i64.p0(<2 x i64>, ptr, <2 x i1>, i32)
128
129define void @vpstore_v2i64(<2 x i64> %val, ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {
130; CHECK-LABEL: vpstore_v2i64:
131; CHECK:       # %bb.0:
132; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
133; CHECK-NEXT:    vse64.v v8, (a0), v0.t
134; CHECK-NEXT:    ret
135  call void @llvm.vp.store.v2i64.p0(<2 x i64> %val, ptr %ptr, <2 x i1> %m, i32 %evl)
136  ret void
137}
138
139declare void @llvm.vp.store.v4i64.p0(<4 x i64>, ptr, <4 x i1>, i32)
140
141define void @vpstore_v4i64(<4 x i64> %val, ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {
142; CHECK-LABEL: vpstore_v4i64:
143; CHECK:       # %bb.0:
144; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
145; CHECK-NEXT:    vse64.v v8, (a0), v0.t
146; CHECK-NEXT:    ret
147  call void @llvm.vp.store.v4i64.p0(<4 x i64> %val, ptr %ptr, <4 x i1> %m, i32 %evl)
148  ret void
149}
150
151declare void @llvm.vp.store.v8i64.p0(<8 x i64>, ptr, <8 x i1>, i32)
152
153define void @vpstore_v8i64(<8 x i64> %val, ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
154; CHECK-LABEL: vpstore_v8i64:
155; CHECK:       # %bb.0:
156; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
157; CHECK-NEXT:    vse64.v v8, (a0), v0.t
158; CHECK-NEXT:    ret
159  call void @llvm.vp.store.v8i64.p0(<8 x i64> %val, ptr %ptr, <8 x i1> %m, i32 %evl)
160  ret void
161}
162
163declare void @llvm.vp.store.v2f16.p0(<2 x half>, ptr, <2 x i1>, i32)
164
165define void @vpstore_v2f16(<2 x half> %val, ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {
166; CHECK-LABEL: vpstore_v2f16:
167; CHECK:       # %bb.0:
168; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
169; CHECK-NEXT:    vse16.v v8, (a0), v0.t
170; CHECK-NEXT:    ret
171  call void @llvm.vp.store.v2f16.p0(<2 x half> %val, ptr %ptr, <2 x i1> %m, i32 %evl)
172  ret void
173}
174
175declare void @llvm.vp.store.v4f16.p0(<4 x half>, ptr, <4 x i1>, i32)
176
177define void @vpstore_v4f16(<4 x half> %val, ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {
178; CHECK-LABEL: vpstore_v4f16:
179; CHECK:       # %bb.0:
180; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
181; CHECK-NEXT:    vse16.v v8, (a0), v0.t
182; CHECK-NEXT:    ret
183  call void @llvm.vp.store.v4f16.p0(<4 x half> %val, ptr %ptr, <4 x i1> %m, i32 %evl)
184  ret void
185}
186
187declare void @llvm.vp.store.v8f16.p0(<8 x half>, ptr, <8 x i1>, i32)
188
189define void @vpstore_v8f16(<8 x half> %val, ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
190; CHECK-LABEL: vpstore_v8f16:
191; CHECK:       # %bb.0:
192; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
193; CHECK-NEXT:    vse16.v v8, (a0), v0.t
194; CHECK-NEXT:    ret
195  call void @llvm.vp.store.v8f16.p0(<8 x half> %val, ptr %ptr, <8 x i1> %m, i32 %evl)
196  ret void
197}
198
199declare void @llvm.vp.store.v2f32.p0(<2 x float>, ptr, <2 x i1>, i32)
200
201define void @vpstore_v2f32(<2 x float> %val, ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {
202; CHECK-LABEL: vpstore_v2f32:
203; CHECK:       # %bb.0:
204; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
205; CHECK-NEXT:    vse32.v v8, (a0), v0.t
206; CHECK-NEXT:    ret
207  call void @llvm.vp.store.v2f32.p0(<2 x float> %val, ptr %ptr, <2 x i1> %m, i32 %evl)
208  ret void
209}
210
211declare void @llvm.vp.store.v4f32.p0(<4 x float>, ptr, <4 x i1>, i32)
212
213define void @vpstore_v4f32(<4 x float> %val, ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {
214; CHECK-LABEL: vpstore_v4f32:
215; CHECK:       # %bb.0:
216; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
217; CHECK-NEXT:    vse32.v v8, (a0), v0.t
218; CHECK-NEXT:    ret
219  call void @llvm.vp.store.v4f32.p0(<4 x float> %val, ptr %ptr, <4 x i1> %m, i32 %evl)
220  ret void
221}
222
223declare void @llvm.vp.store.v6f32.p0(<6 x float>, ptr, <6 x i1>, i32)
224
225define void @vpstore_v6f32(<6 x float> %val, ptr %ptr, <6 x i1> %m, i32 zeroext %evl) {
226; CHECK-LABEL: vpstore_v6f32:
227; CHECK:       # %bb.0:
228; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
229; CHECK-NEXT:    vse32.v v8, (a0), v0.t
230; CHECK-NEXT:    ret
231  call void @llvm.vp.store.v6f32.p0(<6 x float> %val, ptr %ptr, <6 x i1> %m, i32 %evl)
232  ret void
233}
234
235declare void @llvm.vp.store.v8f32.p0(<8 x float>, ptr, <8 x i1>, i32)
236
237define void @vpstore_v8f32(<8 x float> %val, ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
238; CHECK-LABEL: vpstore_v8f32:
239; CHECK:       # %bb.0:
240; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
241; CHECK-NEXT:    vse32.v v8, (a0), v0.t
242; CHECK-NEXT:    ret
243  call void @llvm.vp.store.v8f32.p0(<8 x float> %val, ptr %ptr, <8 x i1> %m, i32 %evl)
244  ret void
245}
246
247declare void @llvm.vp.store.v2f64.p0(<2 x double>, ptr, <2 x i1>, i32)
248
249define void @vpstore_v2f64(<2 x double> %val, ptr %ptr, <2 x i1> %m, i32 zeroext %evl) {
250; CHECK-LABEL: vpstore_v2f64:
251; CHECK:       # %bb.0:
252; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
253; CHECK-NEXT:    vse64.v v8, (a0), v0.t
254; CHECK-NEXT:    ret
255  call void @llvm.vp.store.v2f64.p0(<2 x double> %val, ptr %ptr, <2 x i1> %m, i32 %evl)
256  ret void
257}
258
259declare void @llvm.vp.store.v4f64.p0(<4 x double>, ptr, <4 x i1>, i32)
260
261define void @vpstore_v4f64(<4 x double> %val, ptr %ptr, <4 x i1> %m, i32 zeroext %evl) {
262; CHECK-LABEL: vpstore_v4f64:
263; CHECK:       # %bb.0:
264; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
265; CHECK-NEXT:    vse64.v v8, (a0), v0.t
266; CHECK-NEXT:    ret
267  call void @llvm.vp.store.v4f64.p0(<4 x double> %val, ptr %ptr, <4 x i1> %m, i32 %evl)
268  ret void
269}
270
271declare void @llvm.vp.store.v8f64.p0(<8 x double>, ptr, <8 x i1>, i32)
272
273define void @vpstore_v8f64(<8 x double> %val, ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
274; CHECK-LABEL: vpstore_v8f64:
275; CHECK:       # %bb.0:
276; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
277; CHECK-NEXT:    vse64.v v8, (a0), v0.t
278; CHECK-NEXT:    ret
279  call void @llvm.vp.store.v8f64.p0(<8 x double> %val, ptr %ptr, <8 x i1> %m, i32 %evl)
280  ret void
281}
282
283define void @vpstore_v2i8_allones_mask(<2 x i8> %val, ptr %ptr, i32 zeroext %evl) {
284; CHECK-LABEL: vpstore_v2i8_allones_mask:
285; CHECK:       # %bb.0:
286; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
287; CHECK-NEXT:    vse8.v v8, (a0)
288; CHECK-NEXT:    ret
289  call void @llvm.vp.store.v2i8.p0(<2 x i8> %val, ptr %ptr, <2 x i1> splat (i1 true), i32 %evl)
290  ret void
291}
292
293declare void @llvm.vp.store.v32f64.p0(<32 x double>, ptr, <32 x i1>, i32)
294
295define void @vpstore_v32f64(<32 x double> %val, ptr %ptr, <32 x i1> %m, i32 zeroext %evl) {
296; CHECK-LABEL: vpstore_v32f64:
297; CHECK:       # %bb.0:
298; CHECK-NEXT:    li a3, 16
299; CHECK-NEXT:    mv a2, a1
300; CHECK-NEXT:    bltu a1, a3, .LBB24_2
301; CHECK-NEXT:  # %bb.1:
302; CHECK-NEXT:    li a2, 16
303; CHECK-NEXT:  .LBB24_2:
304; CHECK-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
305; CHECK-NEXT:    vse64.v v8, (a0), v0.t
306; CHECK-NEXT:    addi a2, a1, -16
307; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
308; CHECK-NEXT:    vslidedown.vi v0, v0, 2
309; CHECK-NEXT:    sltu a1, a1, a2
310; CHECK-NEXT:    addi a1, a1, -1
311; CHECK-NEXT:    and a1, a1, a2
312; CHECK-NEXT:    addi a0, a0, 128
313; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
314; CHECK-NEXT:    vse64.v v16, (a0), v0.t
315; CHECK-NEXT:    ret
316  call void @llvm.vp.store.v32f64.p0(<32 x double> %val, ptr %ptr, <32 x i1> %m, i32 %evl)
317  ret void
318}
319