xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll (revision 97982a8c605fac7c86d02e641a6cd7898b3ca343) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64
6
7declare <8 x i7> @llvm.vp.or.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32)
8
9define <8 x i7> @vor_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
10; CHECK-LABEL: vor_vv_v8i7:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
13; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
14; CHECK-NEXT:    ret
15  %v = call <8 x i7> @llvm.vp.or.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
16  ret <8 x i7> %v
17}
18
19declare <2 x i8> @llvm.vp.or.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32)
20
21define <2 x i8> @vor_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {
22; CHECK-LABEL: vor_vv_v2i8:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
25; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
26; CHECK-NEXT:    ret
27  %v = call <2 x i8> @llvm.vp.or.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)
28  ret <2 x i8> %v
29}
30
31define <2 x i8> @vor_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {
32; CHECK-LABEL: vor_vv_v2i8_unmasked:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
35; CHECK-NEXT:    vor.vv v8, v8, v9
36; CHECK-NEXT:    ret
37  %v = call <2 x i8> @llvm.vp.or.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)
38  ret <2 x i8> %v
39}
40
41define <2 x i8> @vor_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
42; CHECK-LABEL: vor_vx_v2i8:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
45; CHECK-NEXT:    vor.vx v8, v8, a0, v0.t
46; CHECK-NEXT:    ret
47  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
48  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
49  %v = call <2 x i8> @llvm.vp.or.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)
50  ret <2 x i8> %v
51}
52
53define <2 x i8> @vor_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
54; CHECK-LABEL: vor_vx_v2i8_unmasked:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
57; CHECK-NEXT:    vor.vx v8, v8, a0
58; CHECK-NEXT:    ret
59  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
60  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
61  %v = call <2 x i8> @llvm.vp.or.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl)
62  ret <2 x i8> %v
63}
64
65define <2 x i8> @vor_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
66; CHECK-LABEL: vor_vi_v2i8:
67; CHECK:       # %bb.0:
68; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
69; CHECK-NEXT:    vor.vi v8, v8, 5, v0.t
70; CHECK-NEXT:    ret
71  %v = call <2 x i8> @llvm.vp.or.v2i8(<2 x i8> %va, <2 x i8> splat (i8 5), <2 x i1> %m, i32 %evl)
72  ret <2 x i8> %v
73}
74
75define <2 x i8> @vor_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) {
76; CHECK-LABEL: vor_vi_v2i8_unmasked:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
79; CHECK-NEXT:    vor.vi v8, v8, 5
80; CHECK-NEXT:    ret
81  %v = call <2 x i8> @llvm.vp.or.v2i8(<2 x i8> %va, <2 x i8> splat (i8 5), <2 x i1> splat (i1 true), i32 %evl)
82  ret <2 x i8> %v
83}
84
85declare <4 x i8> @llvm.vp.or.v4i8(<4 x i8>, <4 x i8>, <4 x i1>, i32)
86
87define <4 x i8> @vor_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {
88; CHECK-LABEL: vor_vv_v4i8:
89; CHECK:       # %bb.0:
90; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
91; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
92; CHECK-NEXT:    ret
93  %v = call <4 x i8> @llvm.vp.or.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)
94  ret <4 x i8> %v
95}
96
97define <4 x i8> @vor_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {
98; CHECK-LABEL: vor_vv_v4i8_unmasked:
99; CHECK:       # %bb.0:
100; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
101; CHECK-NEXT:    vor.vv v8, v8, v9
102; CHECK-NEXT:    ret
103  %v = call <4 x i8> @llvm.vp.or.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)
104  ret <4 x i8> %v
105}
106
107define <4 x i8> @vor_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
108; CHECK-LABEL: vor_vx_v4i8:
109; CHECK:       # %bb.0:
110; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
111; CHECK-NEXT:    vor.vx v8, v8, a0, v0.t
112; CHECK-NEXT:    ret
113  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
114  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
115  %v = call <4 x i8> @llvm.vp.or.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)
116  ret <4 x i8> %v
117}
118
119define <4 x i8> @vor_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
120; CHECK-LABEL: vor_vx_v4i8_commute:
121; CHECK:       # %bb.0:
122; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
123; CHECK-NEXT:    vor.vx v8, v8, a0, v0.t
124; CHECK-NEXT:    ret
125  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
126  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
127  %v = call <4 x i8> @llvm.vp.or.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl)
128  ret <4 x i8> %v
129}
130
131define <4 x i8> @vor_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
132; CHECK-LABEL: vor_vx_v4i8_unmasked:
133; CHECK:       # %bb.0:
134; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
135; CHECK-NEXT:    vor.vx v8, v8, a0
136; CHECK-NEXT:    ret
137  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
138  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
139  %v = call <4 x i8> @llvm.vp.or.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl)
140  ret <4 x i8> %v
141}
142
143define <4 x i8> @vor_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
144; CHECK-LABEL: vor_vi_v4i8:
145; CHECK:       # %bb.0:
146; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
147; CHECK-NEXT:    vor.vi v8, v8, 5, v0.t
148; CHECK-NEXT:    ret
149  %v = call <4 x i8> @llvm.vp.or.v4i8(<4 x i8> %va, <4 x i8> splat (i8 5), <4 x i1> %m, i32 %evl)
150  ret <4 x i8> %v
151}
152
153define <4 x i8> @vor_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) {
154; CHECK-LABEL: vor_vi_v4i8_unmasked:
155; CHECK:       # %bb.0:
156; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
157; CHECK-NEXT:    vor.vi v8, v8, 5
158; CHECK-NEXT:    ret
159  %v = call <4 x i8> @llvm.vp.or.v4i8(<4 x i8> %va, <4 x i8> splat (i8 5), <4 x i1> splat (i1 true), i32 %evl)
160  ret <4 x i8> %v
161}
162
163declare <7 x i8> @llvm.vp.or.v5i8(<7 x i8>, <7 x i8>, <7 x i1>, i32)
164
165define <7 x i8> @vor_vv_v5i8(<7 x i8> %va, <7 x i8> %b, <7 x i1> %m, i32 zeroext %evl) {
166; CHECK-LABEL: vor_vv_v5i8:
167; CHECK:       # %bb.0:
168; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
169; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
170; CHECK-NEXT:    ret
171  %v = call <7 x i8> @llvm.vp.or.v5i8(<7 x i8> %va, <7 x i8> %b, <7 x i1> %m, i32 %evl)
172  ret <7 x i8> %v
173}
174
175define <7 x i8> @vor_vv_v5i8_unmasked(<7 x i8> %va, <7 x i8> %b, i32 zeroext %evl) {
176; CHECK-LABEL: vor_vv_v5i8_unmasked:
177; CHECK:       # %bb.0:
178; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
179; CHECK-NEXT:    vor.vv v8, v8, v9
180; CHECK-NEXT:    ret
181  %v = call <7 x i8> @llvm.vp.or.v5i8(<7 x i8> %va, <7 x i8> %b, <7 x i1> splat (i1 true), i32 %evl)
182  ret <7 x i8> %v
183}
184
185define <7 x i8> @vor_vx_v5i8(<7 x i8> %va, i8 %b, <7 x i1> %m, i32 zeroext %evl) {
186; CHECK-LABEL: vor_vx_v5i8:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
189; CHECK-NEXT:    vor.vx v8, v8, a0, v0.t
190; CHECK-NEXT:    ret
191  %elt.head = insertelement <7 x i8> poison, i8 %b, i32 0
192  %vb = shufflevector <7 x i8> %elt.head, <7 x i8> poison, <7 x i32> zeroinitializer
193  %v = call <7 x i8> @llvm.vp.or.v5i8(<7 x i8> %va, <7 x i8> %vb, <7 x i1> %m, i32 %evl)
194  ret <7 x i8> %v
195}
196
197define <7 x i8> @vor_vx_v5i8_unmasked(<7 x i8> %va, i8 %b, i32 zeroext %evl) {
198; CHECK-LABEL: vor_vx_v5i8_unmasked:
199; CHECK:       # %bb.0:
200; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
201; CHECK-NEXT:    vor.vx v8, v8, a0
202; CHECK-NEXT:    ret
203  %elt.head = insertelement <7 x i8> poison, i8 %b, i32 0
204  %vb = shufflevector <7 x i8> %elt.head, <7 x i8> poison, <7 x i32> zeroinitializer
205  %v = call <7 x i8> @llvm.vp.or.v5i8(<7 x i8> %va, <7 x i8> %vb, <7 x i1> splat (i1 true), i32 %evl)
206  ret <7 x i8> %v
207}
208
209define <7 x i8> @vor_vi_v5i8(<7 x i8> %va, <7 x i1> %m, i32 zeroext %evl) {
210; CHECK-LABEL: vor_vi_v5i8:
211; CHECK:       # %bb.0:
212; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
213; CHECK-NEXT:    vor.vi v8, v8, 5, v0.t
214; CHECK-NEXT:    ret
215  %v = call <7 x i8> @llvm.vp.or.v5i8(<7 x i8> %va, <7 x i8> splat (i8 5), <7 x i1> %m, i32 %evl)
216  ret <7 x i8> %v
217}
218
219define <7 x i8> @vor_vi_v5i8_unmasked(<7 x i8> %va, i32 zeroext %evl) {
220; CHECK-LABEL: vor_vi_v5i8_unmasked:
221; CHECK:       # %bb.0:
222; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
223; CHECK-NEXT:    vor.vi v8, v8, 5
224; CHECK-NEXT:    ret
225  %v = call <7 x i8> @llvm.vp.or.v5i8(<7 x i8> %va, <7 x i8> splat (i8 5), <7 x i1> splat (i1 true), i32 %evl)
226  ret <7 x i8> %v
227}
228
229declare <8 x i8> @llvm.vp.or.v8i8(<8 x i8>, <8 x i8>, <8 x i1>, i32)
230
231define <8 x i8> @vor_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {
232; CHECK-LABEL: vor_vv_v8i8:
233; CHECK:       # %bb.0:
234; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
235; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
236; CHECK-NEXT:    ret
237  %v = call <8 x i8> @llvm.vp.or.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)
238  ret <8 x i8> %v
239}
240
241define <8 x i8> @vor_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {
242; CHECK-LABEL: vor_vv_v8i8_unmasked:
243; CHECK:       # %bb.0:
244; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
245; CHECK-NEXT:    vor.vv v8, v8, v9
246; CHECK-NEXT:    ret
247  %v = call <8 x i8> @llvm.vp.or.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)
248  ret <8 x i8> %v
249}
250
251define <8 x i8> @vor_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {
252; CHECK-LABEL: vor_vx_v8i8:
253; CHECK:       # %bb.0:
254; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
255; CHECK-NEXT:    vor.vx v8, v8, a0, v0.t
256; CHECK-NEXT:    ret
257  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
258  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
259  %v = call <8 x i8> @llvm.vp.or.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)
260  ret <8 x i8> %v
261}
262
263define <8 x i8> @vor_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
264; CHECK-LABEL: vor_vx_v8i8_unmasked:
265; CHECK:       # %bb.0:
266; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
267; CHECK-NEXT:    vor.vx v8, v8, a0
268; CHECK-NEXT:    ret
269  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
270  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
271  %v = call <8 x i8> @llvm.vp.or.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl)
272  ret <8 x i8> %v
273}
274
275define <8 x i8> @vor_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
276; CHECK-LABEL: vor_vi_v8i8:
277; CHECK:       # %bb.0:
278; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
279; CHECK-NEXT:    vor.vi v8, v8, 5, v0.t
280; CHECK-NEXT:    ret
281  %v = call <8 x i8> @llvm.vp.or.v8i8(<8 x i8> %va, <8 x i8> splat (i8 5), <8 x i1> %m, i32 %evl)
282  ret <8 x i8> %v
283}
284
285define <8 x i8> @vor_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) {
286; CHECK-LABEL: vor_vi_v8i8_unmasked:
287; CHECK:       # %bb.0:
288; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
289; CHECK-NEXT:    vor.vi v8, v8, 5
290; CHECK-NEXT:    ret
291  %v = call <8 x i8> @llvm.vp.or.v8i8(<8 x i8> %va, <8 x i8> splat (i8 5), <8 x i1> splat (i1 true), i32 %evl)
292  ret <8 x i8> %v
293}
294
295declare <16 x i8> @llvm.vp.or.v16i8(<16 x i8>, <16 x i8>, <16 x i1>, i32)
296
297define <16 x i8> @vor_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {
298; CHECK-LABEL: vor_vv_v16i8:
299; CHECK:       # %bb.0:
300; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
301; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
302; CHECK-NEXT:    ret
303  %v = call <16 x i8> @llvm.vp.or.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)
304  ret <16 x i8> %v
305}
306
307define <16 x i8> @vor_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {
308; CHECK-LABEL: vor_vv_v16i8_unmasked:
309; CHECK:       # %bb.0:
310; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
311; CHECK-NEXT:    vor.vv v8, v8, v9
312; CHECK-NEXT:    ret
313  %v = call <16 x i8> @llvm.vp.or.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)
314  ret <16 x i8> %v
315}
316
317define <16 x i8> @vor_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {
318; CHECK-LABEL: vor_vx_v16i8:
319; CHECK:       # %bb.0:
320; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
321; CHECK-NEXT:    vor.vx v8, v8, a0, v0.t
322; CHECK-NEXT:    ret
323  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
324  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
325  %v = call <16 x i8> @llvm.vp.or.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)
326  ret <16 x i8> %v
327}
328
329define <16 x i8> @vor_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {
330; CHECK-LABEL: vor_vx_v16i8_unmasked:
331; CHECK:       # %bb.0:
332; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
333; CHECK-NEXT:    vor.vx v8, v8, a0
334; CHECK-NEXT:    ret
335  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
336  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
337  %v = call <16 x i8> @llvm.vp.or.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl)
338  ret <16 x i8> %v
339}
340
341define <16 x i8> @vor_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
342; CHECK-LABEL: vor_vi_v16i8:
343; CHECK:       # %bb.0:
344; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
345; CHECK-NEXT:    vor.vi v8, v8, 5, v0.t
346; CHECK-NEXT:    ret
347  %v = call <16 x i8> @llvm.vp.or.v16i8(<16 x i8> %va, <16 x i8> splat (i8 5), <16 x i1> %m, i32 %evl)
348  ret <16 x i8> %v
349}
350
351define <16 x i8> @vor_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) {
352; CHECK-LABEL: vor_vi_v16i8_unmasked:
353; CHECK:       # %bb.0:
354; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
355; CHECK-NEXT:    vor.vi v8, v8, 5
356; CHECK-NEXT:    ret
357  %v = call <16 x i8> @llvm.vp.or.v16i8(<16 x i8> %va, <16 x i8> splat (i8 5), <16 x i1> splat (i1 true), i32 %evl)
358  ret <16 x i8> %v
359}
360
361declare <2 x i16> @llvm.vp.or.v2i16(<2 x i16>, <2 x i16>, <2 x i1>, i32)
362
363define <2 x i16> @vor_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {
364; CHECK-LABEL: vor_vv_v2i16:
365; CHECK:       # %bb.0:
366; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
367; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
368; CHECK-NEXT:    ret
369  %v = call <2 x i16> @llvm.vp.or.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)
370  ret <2 x i16> %v
371}
372
373define <2 x i16> @vor_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {
374; CHECK-LABEL: vor_vv_v2i16_unmasked:
375; CHECK:       # %bb.0:
376; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
377; CHECK-NEXT:    vor.vv v8, v8, v9
378; CHECK-NEXT:    ret
379  %v = call <2 x i16> @llvm.vp.or.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)
380  ret <2 x i16> %v
381}
382
383define <2 x i16> @vor_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {
384; CHECK-LABEL: vor_vx_v2i16:
385; CHECK:       # %bb.0:
386; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
387; CHECK-NEXT:    vor.vx v8, v8, a0, v0.t
388; CHECK-NEXT:    ret
389  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
390  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
391  %v = call <2 x i16> @llvm.vp.or.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)
392  ret <2 x i16> %v
393}
394
395define <2 x i16> @vor_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {
396; CHECK-LABEL: vor_vx_v2i16_unmasked:
397; CHECK:       # %bb.0:
398; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
399; CHECK-NEXT:    vor.vx v8, v8, a0
400; CHECK-NEXT:    ret
401  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
402  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
403  %v = call <2 x i16> @llvm.vp.or.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl)
404  ret <2 x i16> %v
405}
406
407define <2 x i16> @vor_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
408; CHECK-LABEL: vor_vi_v2i16:
409; CHECK:       # %bb.0:
410; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
411; CHECK-NEXT:    vor.vi v8, v8, 5, v0.t
412; CHECK-NEXT:    ret
413  %v = call <2 x i16> @llvm.vp.or.v2i16(<2 x i16> %va, <2 x i16> splat (i16 5), <2 x i1> %m, i32 %evl)
414  ret <2 x i16> %v
415}
416
417define <2 x i16> @vor_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) {
418; CHECK-LABEL: vor_vi_v2i16_unmasked:
419; CHECK:       # %bb.0:
420; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
421; CHECK-NEXT:    vor.vi v8, v8, 5
422; CHECK-NEXT:    ret
423  %v = call <2 x i16> @llvm.vp.or.v2i16(<2 x i16> %va, <2 x i16> splat (i16 5), <2 x i1> splat (i1 true), i32 %evl)
424  ret <2 x i16> %v
425}
426
427declare <4 x i16> @llvm.vp.or.v4i16(<4 x i16>, <4 x i16>, <4 x i1>, i32)
428
429define <4 x i16> @vor_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {
430; CHECK-LABEL: vor_vv_v4i16:
431; CHECK:       # %bb.0:
432; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
433; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
434; CHECK-NEXT:    ret
435  %v = call <4 x i16> @llvm.vp.or.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)
436  ret <4 x i16> %v
437}
438
439define <4 x i16> @vor_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {
440; CHECK-LABEL: vor_vv_v4i16_unmasked:
441; CHECK:       # %bb.0:
442; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
443; CHECK-NEXT:    vor.vv v8, v8, v9
444; CHECK-NEXT:    ret
445  %v = call <4 x i16> @llvm.vp.or.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)
446  ret <4 x i16> %v
447}
448
449define <4 x i16> @vor_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {
450; CHECK-LABEL: vor_vx_v4i16:
451; CHECK:       # %bb.0:
452; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
453; CHECK-NEXT:    vor.vx v8, v8, a0, v0.t
454; CHECK-NEXT:    ret
455  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
456  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
457  %v = call <4 x i16> @llvm.vp.or.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)
458  ret <4 x i16> %v
459}
460
461define <4 x i16> @vor_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {
462; CHECK-LABEL: vor_vx_v4i16_unmasked:
463; CHECK:       # %bb.0:
464; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
465; CHECK-NEXT:    vor.vx v8, v8, a0
466; CHECK-NEXT:    ret
467  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
468  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
469  %v = call <4 x i16> @llvm.vp.or.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl)
470  ret <4 x i16> %v
471}
472
473define <4 x i16> @vor_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
474; CHECK-LABEL: vor_vi_v4i16:
475; CHECK:       # %bb.0:
476; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
477; CHECK-NEXT:    vor.vi v8, v8, 5, v0.t
478; CHECK-NEXT:    ret
479  %v = call <4 x i16> @llvm.vp.or.v4i16(<4 x i16> %va, <4 x i16> splat (i16 5), <4 x i1> %m, i32 %evl)
480  ret <4 x i16> %v
481}
482
483define <4 x i16> @vor_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) {
484; CHECK-LABEL: vor_vi_v4i16_unmasked:
485; CHECK:       # %bb.0:
486; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
487; CHECK-NEXT:    vor.vi v8, v8, 5
488; CHECK-NEXT:    ret
489  %v = call <4 x i16> @llvm.vp.or.v4i16(<4 x i16> %va, <4 x i16> splat (i16 5), <4 x i1> splat (i1 true), i32 %evl)
490  ret <4 x i16> %v
491}
492
493declare <8 x i16> @llvm.vp.or.v8i16(<8 x i16>, <8 x i16>, <8 x i1>, i32)
494
495define <8 x i16> @vor_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {
496; CHECK-LABEL: vor_vv_v8i16:
497; CHECK:       # %bb.0:
498; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
499; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
500; CHECK-NEXT:    ret
501  %v = call <8 x i16> @llvm.vp.or.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)
502  ret <8 x i16> %v
503}
504
505define <8 x i16> @vor_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {
506; CHECK-LABEL: vor_vv_v8i16_unmasked:
507; CHECK:       # %bb.0:
508; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
509; CHECK-NEXT:    vor.vv v8, v8, v9
510; CHECK-NEXT:    ret
511  %v = call <8 x i16> @llvm.vp.or.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)
512  ret <8 x i16> %v
513}
514
515define <8 x i16> @vor_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {
516; CHECK-LABEL: vor_vx_v8i16:
517; CHECK:       # %bb.0:
518; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
519; CHECK-NEXT:    vor.vx v8, v8, a0, v0.t
520; CHECK-NEXT:    ret
521  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
522  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
523  %v = call <8 x i16> @llvm.vp.or.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)
524  ret <8 x i16> %v
525}
526
527define <8 x i16> @vor_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {
528; CHECK-LABEL: vor_vx_v8i16_unmasked:
529; CHECK:       # %bb.0:
530; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
531; CHECK-NEXT:    vor.vx v8, v8, a0
532; CHECK-NEXT:    ret
533  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
534  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
535  %v = call <8 x i16> @llvm.vp.or.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl)
536  ret <8 x i16> %v
537}
538
539define <8 x i16> @vor_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
540; CHECK-LABEL: vor_vi_v8i16:
541; CHECK:       # %bb.0:
542; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
543; CHECK-NEXT:    vor.vi v8, v8, 5, v0.t
544; CHECK-NEXT:    ret
545  %v = call <8 x i16> @llvm.vp.or.v8i16(<8 x i16> %va, <8 x i16> splat (i16 5), <8 x i1> %m, i32 %evl)
546  ret <8 x i16> %v
547}
548
549define <8 x i16> @vor_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) {
550; CHECK-LABEL: vor_vi_v8i16_unmasked:
551; CHECK:       # %bb.0:
552; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
553; CHECK-NEXT:    vor.vi v8, v8, 5
554; CHECK-NEXT:    ret
555  %v = call <8 x i16> @llvm.vp.or.v8i16(<8 x i16> %va, <8 x i16> splat (i16 5), <8 x i1> splat (i1 true), i32 %evl)
556  ret <8 x i16> %v
557}
558
559declare <16 x i16> @llvm.vp.or.v16i16(<16 x i16>, <16 x i16>, <16 x i1>, i32)
560
561define <16 x i16> @vor_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {
562; CHECK-LABEL: vor_vv_v16i16:
563; CHECK:       # %bb.0:
564; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
565; CHECK-NEXT:    vor.vv v8, v8, v10, v0.t
566; CHECK-NEXT:    ret
567  %v = call <16 x i16> @llvm.vp.or.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)
568  ret <16 x i16> %v
569}
570
571define <16 x i16> @vor_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {
572; CHECK-LABEL: vor_vv_v16i16_unmasked:
573; CHECK:       # %bb.0:
574; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
575; CHECK-NEXT:    vor.vv v8, v8, v10
576; CHECK-NEXT:    ret
577  %v = call <16 x i16> @llvm.vp.or.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)
578  ret <16 x i16> %v
579}
580
581define <16 x i16> @vor_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {
582; CHECK-LABEL: vor_vx_v16i16:
583; CHECK:       # %bb.0:
584; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
585; CHECK-NEXT:    vor.vx v8, v8, a0, v0.t
586; CHECK-NEXT:    ret
587  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
588  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
589  %v = call <16 x i16> @llvm.vp.or.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)
590  ret <16 x i16> %v
591}
592
593define <16 x i16> @vor_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {
594; CHECK-LABEL: vor_vx_v16i16_unmasked:
595; CHECK:       # %bb.0:
596; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
597; CHECK-NEXT:    vor.vx v8, v8, a0
598; CHECK-NEXT:    ret
599  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
600  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
601  %v = call <16 x i16> @llvm.vp.or.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl)
602  ret <16 x i16> %v
603}
604
605define <16 x i16> @vor_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) {
606; CHECK-LABEL: vor_vi_v16i16:
607; CHECK:       # %bb.0:
608; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
609; CHECK-NEXT:    vor.vi v8, v8, 5, v0.t
610; CHECK-NEXT:    ret
611  %v = call <16 x i16> @llvm.vp.or.v16i16(<16 x i16> %va, <16 x i16> splat (i16 5), <16 x i1> %m, i32 %evl)
612  ret <16 x i16> %v
613}
614
615define <16 x i16> @vor_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) {
616; CHECK-LABEL: vor_vi_v16i16_unmasked:
617; CHECK:       # %bb.0:
618; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
619; CHECK-NEXT:    vor.vi v8, v8, 5
620; CHECK-NEXT:    ret
621  %v = call <16 x i16> @llvm.vp.or.v16i16(<16 x i16> %va, <16 x i16> splat (i16 5), <16 x i1> splat (i1 true), i32 %evl)
622  ret <16 x i16> %v
623}
624
625declare <2 x i32> @llvm.vp.or.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32)
626
627define <2 x i32> @vor_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {
628; CHECK-LABEL: vor_vv_v2i32:
629; CHECK:       # %bb.0:
630; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
631; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
632; CHECK-NEXT:    ret
633  %v = call <2 x i32> @llvm.vp.or.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)
634  ret <2 x i32> %v
635}
636
637define <2 x i32> @vor_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {
638; CHECK-LABEL: vor_vv_v2i32_unmasked:
639; CHECK:       # %bb.0:
640; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
641; CHECK-NEXT:    vor.vv v8, v8, v9
642; CHECK-NEXT:    ret
643  %v = call <2 x i32> @llvm.vp.or.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)
644  ret <2 x i32> %v
645}
646
647define <2 x i32> @vor_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {
648; CHECK-LABEL: vor_vx_v2i32:
649; CHECK:       # %bb.0:
650; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
651; CHECK-NEXT:    vor.vx v8, v8, a0, v0.t
652; CHECK-NEXT:    ret
653  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
654  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
655  %v = call <2 x i32> @llvm.vp.or.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)
656  ret <2 x i32> %v
657}
658
659define <2 x i32> @vor_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {
660; CHECK-LABEL: vor_vx_v2i32_unmasked:
661; CHECK:       # %bb.0:
662; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
663; CHECK-NEXT:    vor.vx v8, v8, a0
664; CHECK-NEXT:    ret
665  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
666  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
667  %v = call <2 x i32> @llvm.vp.or.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl)
668  ret <2 x i32> %v
669}
670
671define <2 x i32> @vor_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
672; CHECK-LABEL: vor_vi_v2i32:
673; CHECK:       # %bb.0:
674; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
675; CHECK-NEXT:    vor.vi v8, v8, 5, v0.t
676; CHECK-NEXT:    ret
677  %v = call <2 x i32> @llvm.vp.or.v2i32(<2 x i32> %va, <2 x i32> splat (i32 5), <2 x i1> %m, i32 %evl)
678  ret <2 x i32> %v
679}
680
681define <2 x i32> @vor_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) {
682; CHECK-LABEL: vor_vi_v2i32_unmasked:
683; CHECK:       # %bb.0:
684; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
685; CHECK-NEXT:    vor.vi v8, v8, 5
686; CHECK-NEXT:    ret
687  %v = call <2 x i32> @llvm.vp.or.v2i32(<2 x i32> %va, <2 x i32> splat (i32 5), <2 x i1> splat (i1 true), i32 %evl)
688  ret <2 x i32> %v
689}
690
691declare <4 x i32> @llvm.vp.or.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
692
693define <4 x i32> @vor_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {
694; CHECK-LABEL: vor_vv_v4i32:
695; CHECK:       # %bb.0:
696; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
697; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
698; CHECK-NEXT:    ret
699  %v = call <4 x i32> @llvm.vp.or.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)
700  ret <4 x i32> %v
701}
702
703define <4 x i32> @vor_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {
704; CHECK-LABEL: vor_vv_v4i32_unmasked:
705; CHECK:       # %bb.0:
706; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
707; CHECK-NEXT:    vor.vv v8, v8, v9
708; CHECK-NEXT:    ret
709  %v = call <4 x i32> @llvm.vp.or.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)
710  ret <4 x i32> %v
711}
712
713define <4 x i32> @vor_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {
714; CHECK-LABEL: vor_vx_v4i32:
715; CHECK:       # %bb.0:
716; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
717; CHECK-NEXT:    vor.vx v8, v8, a0, v0.t
718; CHECK-NEXT:    ret
719  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
720  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
721  %v = call <4 x i32> @llvm.vp.or.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)
722  ret <4 x i32> %v
723}
724
725define <4 x i32> @vor_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {
726; CHECK-LABEL: vor_vx_v4i32_unmasked:
727; CHECK:       # %bb.0:
728; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
729; CHECK-NEXT:    vor.vx v8, v8, a0
730; CHECK-NEXT:    ret
731  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
732  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
733  %v = call <4 x i32> @llvm.vp.or.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl)
734  ret <4 x i32> %v
735}
736
737define <4 x i32> @vor_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
738; CHECK-LABEL: vor_vi_v4i32:
739; CHECK:       # %bb.0:
740; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
741; CHECK-NEXT:    vor.vi v8, v8, 5, v0.t
742; CHECK-NEXT:    ret
743  %v = call <4 x i32> @llvm.vp.or.v4i32(<4 x i32> %va, <4 x i32> splat (i32 5), <4 x i1> %m, i32 %evl)
744  ret <4 x i32> %v
745}
746
747define <4 x i32> @vor_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) {
748; CHECK-LABEL: vor_vi_v4i32_unmasked:
749; CHECK:       # %bb.0:
750; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
751; CHECK-NEXT:    vor.vi v8, v8, 5
752; CHECK-NEXT:    ret
753  %v = call <4 x i32> @llvm.vp.or.v4i32(<4 x i32> %va, <4 x i32> splat (i32 5), <4 x i1> splat (i1 true), i32 %evl)
754  ret <4 x i32> %v
755}
756
757declare <8 x i32> @llvm.vp.or.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
758
759define <8 x i32> @vor_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {
760; CHECK-LABEL: vor_vv_v8i32:
761; CHECK:       # %bb.0:
762; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
763; CHECK-NEXT:    vor.vv v8, v8, v10, v0.t
764; CHECK-NEXT:    ret
765  %v = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)
766  ret <8 x i32> %v
767}
768
769define <8 x i32> @vor_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {
770; CHECK-LABEL: vor_vv_v8i32_unmasked:
771; CHECK:       # %bb.0:
772; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
773; CHECK-NEXT:    vor.vv v8, v8, v10
774; CHECK-NEXT:    ret
775  %v = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)
776  ret <8 x i32> %v
777}
778
779define <8 x i32> @vor_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {
780; CHECK-LABEL: vor_vx_v8i32:
781; CHECK:       # %bb.0:
782; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
783; CHECK-NEXT:    vor.vx v8, v8, a0, v0.t
784; CHECK-NEXT:    ret
785  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
786  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
787  %v = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)
788  ret <8 x i32> %v
789}
790
791define <8 x i32> @vor_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {
792; CHECK-LABEL: vor_vx_v8i32_unmasked:
793; CHECK:       # %bb.0:
794; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
795; CHECK-NEXT:    vor.vx v8, v8, a0
796; CHECK-NEXT:    ret
797  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
798  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
799  %v = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl)
800  ret <8 x i32> %v
801}
802
803define <8 x i32> @vor_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
804; CHECK-LABEL: vor_vi_v8i32:
805; CHECK:       # %bb.0:
806; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
807; CHECK-NEXT:    vor.vi v8, v8, 5, v0.t
808; CHECK-NEXT:    ret
809  %v = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %va, <8 x i32> splat (i32 5), <8 x i1> %m, i32 %evl)
810  ret <8 x i32> %v
811}
812
813define <8 x i32> @vor_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) {
814; CHECK-LABEL: vor_vi_v8i32_unmasked:
815; CHECK:       # %bb.0:
816; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
817; CHECK-NEXT:    vor.vi v8, v8, 5
818; CHECK-NEXT:    ret
819  %v = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %va, <8 x i32> splat (i32 5), <8 x i1> splat (i1 true), i32 %evl)
820  ret <8 x i32> %v
821}
822
823declare <16 x i32> @llvm.vp.or.v16i32(<16 x i32>, <16 x i32>, <16 x i1>, i32)
824
825define <16 x i32> @vor_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {
826; CHECK-LABEL: vor_vv_v16i32:
827; CHECK:       # %bb.0:
828; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
829; CHECK-NEXT:    vor.vv v8, v8, v12, v0.t
830; CHECK-NEXT:    ret
831  %v = call <16 x i32> @llvm.vp.or.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)
832  ret <16 x i32> %v
833}
834
835define <16 x i32> @vor_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {
836; CHECK-LABEL: vor_vv_v16i32_unmasked:
837; CHECK:       # %bb.0:
838; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
839; CHECK-NEXT:    vor.vv v8, v8, v12
840; CHECK-NEXT:    ret
841  %v = call <16 x i32> @llvm.vp.or.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)
842  ret <16 x i32> %v
843}
844
845define <16 x i32> @vor_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {
846; CHECK-LABEL: vor_vx_v16i32:
847; CHECK:       # %bb.0:
848; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
849; CHECK-NEXT:    vor.vx v8, v8, a0, v0.t
850; CHECK-NEXT:    ret
851  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
852  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
853  %v = call <16 x i32> @llvm.vp.or.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)
854  ret <16 x i32> %v
855}
856
857define <16 x i32> @vor_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {
858; CHECK-LABEL: vor_vx_v16i32_unmasked:
859; CHECK:       # %bb.0:
860; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
861; CHECK-NEXT:    vor.vx v8, v8, a0
862; CHECK-NEXT:    ret
863  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
864  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
865  %v = call <16 x i32> @llvm.vp.or.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl)
866  ret <16 x i32> %v
867}
868
869define <16 x i32> @vor_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) {
870; CHECK-LABEL: vor_vi_v16i32:
871; CHECK:       # %bb.0:
872; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
873; CHECK-NEXT:    vor.vi v8, v8, 5, v0.t
874; CHECK-NEXT:    ret
875  %v = call <16 x i32> @llvm.vp.or.v16i32(<16 x i32> %va, <16 x i32> splat (i32 5), <16 x i1> %m, i32 %evl)
876  ret <16 x i32> %v
877}
878
879define <16 x i32> @vor_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) {
880; CHECK-LABEL: vor_vi_v16i32_unmasked:
881; CHECK:       # %bb.0:
882; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
883; CHECK-NEXT:    vor.vi v8, v8, 5
884; CHECK-NEXT:    ret
885  %v = call <16 x i32> @llvm.vp.or.v16i32(<16 x i32> %va, <16 x i32> splat (i32 5), <16 x i1> splat (i1 true), i32 %evl)
886  ret <16 x i32> %v
887}
888
889declare <2 x i64> @llvm.vp.or.v2i64(<2 x i64>, <2 x i64>, <2 x i1>, i32)
890
891define <2 x i64> @vor_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {
892; CHECK-LABEL: vor_vv_v2i64:
893; CHECK:       # %bb.0:
894; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
895; CHECK-NEXT:    vor.vv v8, v8, v9, v0.t
896; CHECK-NEXT:    ret
897  %v = call <2 x i64> @llvm.vp.or.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)
898  ret <2 x i64> %v
899}
900
901define <2 x i64> @vor_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {
902; CHECK-LABEL: vor_vv_v2i64_unmasked:
903; CHECK:       # %bb.0:
904; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
905; CHECK-NEXT:    vor.vv v8, v8, v9
906; CHECK-NEXT:    ret
907  %v = call <2 x i64> @llvm.vp.or.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)
908  ret <2 x i64> %v
909}
910
911define <2 x i64> @vor_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
912; RV32-LABEL: vor_vx_v2i64:
913; RV32:       # %bb.0:
914; RV32-NEXT:    addi sp, sp, -16
915; RV32-NEXT:    .cfi_def_cfa_offset 16
916; RV32-NEXT:    sw a0, 8(sp)
917; RV32-NEXT:    sw a1, 12(sp)
918; RV32-NEXT:    addi a0, sp, 8
919; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
920; RV32-NEXT:    vlse64.v v9, (a0), zero
921; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
922; RV32-NEXT:    vor.vv v8, v8, v9, v0.t
923; RV32-NEXT:    addi sp, sp, 16
924; RV32-NEXT:    .cfi_def_cfa_offset 0
925; RV32-NEXT:    ret
926;
927; RV64-LABEL: vor_vx_v2i64:
928; RV64:       # %bb.0:
929; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
930; RV64-NEXT:    vor.vx v8, v8, a0, v0.t
931; RV64-NEXT:    ret
932  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
933  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
934  %v = call <2 x i64> @llvm.vp.or.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
935  ret <2 x i64> %v
936}
937
938define <2 x i64> @vor_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
939; RV32-LABEL: vor_vx_v2i64_unmasked:
940; RV32:       # %bb.0:
941; RV32-NEXT:    addi sp, sp, -16
942; RV32-NEXT:    .cfi_def_cfa_offset 16
943; RV32-NEXT:    sw a0, 8(sp)
944; RV32-NEXT:    sw a1, 12(sp)
945; RV32-NEXT:    addi a0, sp, 8
946; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
947; RV32-NEXT:    vlse64.v v9, (a0), zero
948; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
949; RV32-NEXT:    vor.vv v8, v8, v9
950; RV32-NEXT:    addi sp, sp, 16
951; RV32-NEXT:    .cfi_def_cfa_offset 0
952; RV32-NEXT:    ret
953;
954; RV64-LABEL: vor_vx_v2i64_unmasked:
955; RV64:       # %bb.0:
956; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
957; RV64-NEXT:    vor.vx v8, v8, a0
958; RV64-NEXT:    ret
959  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
960  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
961  %v = call <2 x i64> @llvm.vp.or.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl)
962  ret <2 x i64> %v
963}
964
965define <2 x i64> @vor_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
966; CHECK-LABEL: vor_vi_v2i64:
967; CHECK:       # %bb.0:
968; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
969; CHECK-NEXT:    vor.vi v8, v8, 5, v0.t
970; CHECK-NEXT:    ret
971  %v = call <2 x i64> @llvm.vp.or.v2i64(<2 x i64> %va, <2 x i64> splat (i64 5), <2 x i1> %m, i32 %evl)
972  ret <2 x i64> %v
973}
974
975define <2 x i64> @vor_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
976; CHECK-LABEL: vor_vi_v2i64_unmasked:
977; CHECK:       # %bb.0:
978; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
979; CHECK-NEXT:    vor.vi v8, v8, 5
980; CHECK-NEXT:    ret
981  %v = call <2 x i64> @llvm.vp.or.v2i64(<2 x i64> %va, <2 x i64> splat (i64 5), <2 x i1> splat (i1 true), i32 %evl)
982  ret <2 x i64> %v
983}
984
985declare <4 x i64> @llvm.vp.or.v4i64(<4 x i64>, <4 x i64>, <4 x i1>, i32)
986
987define <4 x i64> @vor_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {
988; CHECK-LABEL: vor_vv_v4i64:
989; CHECK:       # %bb.0:
990; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
991; CHECK-NEXT:    vor.vv v8, v8, v10, v0.t
992; CHECK-NEXT:    ret
993  %v = call <4 x i64> @llvm.vp.or.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)
994  ret <4 x i64> %v
995}
996
997define <4 x i64> @vor_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {
998; CHECK-LABEL: vor_vv_v4i64_unmasked:
999; CHECK:       # %bb.0:
1000; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1001; CHECK-NEXT:    vor.vv v8, v8, v10
1002; CHECK-NEXT:    ret
1003  %v = call <4 x i64> @llvm.vp.or.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)
1004  ret <4 x i64> %v
1005}
1006
1007define <4 x i64> @vor_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
1008; RV32-LABEL: vor_vx_v4i64:
1009; RV32:       # %bb.0:
1010; RV32-NEXT:    addi sp, sp, -16
1011; RV32-NEXT:    .cfi_def_cfa_offset 16
1012; RV32-NEXT:    sw a0, 8(sp)
1013; RV32-NEXT:    sw a1, 12(sp)
1014; RV32-NEXT:    addi a0, sp, 8
1015; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1016; RV32-NEXT:    vlse64.v v10, (a0), zero
1017; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
1018; RV32-NEXT:    vor.vv v8, v8, v10, v0.t
1019; RV32-NEXT:    addi sp, sp, 16
1020; RV32-NEXT:    .cfi_def_cfa_offset 0
1021; RV32-NEXT:    ret
1022;
1023; RV64-LABEL: vor_vx_v4i64:
1024; RV64:       # %bb.0:
1025; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
1026; RV64-NEXT:    vor.vx v8, v8, a0, v0.t
1027; RV64-NEXT:    ret
1028  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
1029  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
1030  %v = call <4 x i64> @llvm.vp.or.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
1031  ret <4 x i64> %v
1032}
1033
1034define <4 x i64> @vor_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
1035; RV32-LABEL: vor_vx_v4i64_unmasked:
1036; RV32:       # %bb.0:
1037; RV32-NEXT:    addi sp, sp, -16
1038; RV32-NEXT:    .cfi_def_cfa_offset 16
1039; RV32-NEXT:    sw a0, 8(sp)
1040; RV32-NEXT:    sw a1, 12(sp)
1041; RV32-NEXT:    addi a0, sp, 8
1042; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
1043; RV32-NEXT:    vlse64.v v10, (a0), zero
1044; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
1045; RV32-NEXT:    vor.vv v8, v8, v10
1046; RV32-NEXT:    addi sp, sp, 16
1047; RV32-NEXT:    .cfi_def_cfa_offset 0
1048; RV32-NEXT:    ret
1049;
1050; RV64-LABEL: vor_vx_v4i64_unmasked:
1051; RV64:       # %bb.0:
1052; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
1053; RV64-NEXT:    vor.vx v8, v8, a0
1054; RV64-NEXT:    ret
1055  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
1056  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
1057  %v = call <4 x i64> @llvm.vp.or.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl)
1058  ret <4 x i64> %v
1059}
1060
1061define <4 x i64> @vor_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
1062; CHECK-LABEL: vor_vi_v4i64:
1063; CHECK:       # %bb.0:
1064; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1065; CHECK-NEXT:    vor.vi v8, v8, 5, v0.t
1066; CHECK-NEXT:    ret
1067  %v = call <4 x i64> @llvm.vp.or.v4i64(<4 x i64> %va, <4 x i64> splat (i64 5), <4 x i1> %m, i32 %evl)
1068  ret <4 x i64> %v
1069}
1070
1071define <4 x i64> @vor_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
1072; CHECK-LABEL: vor_vi_v4i64_unmasked:
1073; CHECK:       # %bb.0:
1074; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
1075; CHECK-NEXT:    vor.vi v8, v8, 5
1076; CHECK-NEXT:    ret
1077  %v = call <4 x i64> @llvm.vp.or.v4i64(<4 x i64> %va, <4 x i64> splat (i64 5), <4 x i1> splat (i1 true), i32 %evl)
1078  ret <4 x i64> %v
1079}
1080
1081declare <8 x i64> @llvm.vp.or.v8i64(<8 x i64>, <8 x i64>, <8 x i1>, i32)
1082
1083define <8 x i64> @vor_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {
1084; CHECK-LABEL: vor_vv_v8i64:
1085; CHECK:       # %bb.0:
1086; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1087; CHECK-NEXT:    vor.vv v8, v8, v12, v0.t
1088; CHECK-NEXT:    ret
1089  %v = call <8 x i64> @llvm.vp.or.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)
1090  ret <8 x i64> %v
1091}
1092
1093define <8 x i64> @vor_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {
1094; CHECK-LABEL: vor_vv_v8i64_unmasked:
1095; CHECK:       # %bb.0:
1096; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1097; CHECK-NEXT:    vor.vv v8, v8, v12
1098; CHECK-NEXT:    ret
1099  %v = call <8 x i64> @llvm.vp.or.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)
1100  ret <8 x i64> %v
1101}
1102
1103define <8 x i64> @vor_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
1104; RV32-LABEL: vor_vx_v8i64:
1105; RV32:       # %bb.0:
1106; RV32-NEXT:    addi sp, sp, -16
1107; RV32-NEXT:    .cfi_def_cfa_offset 16
1108; RV32-NEXT:    sw a0, 8(sp)
1109; RV32-NEXT:    sw a1, 12(sp)
1110; RV32-NEXT:    addi a0, sp, 8
1111; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1112; RV32-NEXT:    vlse64.v v12, (a0), zero
1113; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
1114; RV32-NEXT:    vor.vv v8, v8, v12, v0.t
1115; RV32-NEXT:    addi sp, sp, 16
1116; RV32-NEXT:    .cfi_def_cfa_offset 0
1117; RV32-NEXT:    ret
1118;
1119; RV64-LABEL: vor_vx_v8i64:
1120; RV64:       # %bb.0:
1121; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
1122; RV64-NEXT:    vor.vx v8, v8, a0, v0.t
1123; RV64-NEXT:    ret
1124  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
1125  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
1126  %v = call <8 x i64> @llvm.vp.or.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
1127  ret <8 x i64> %v
1128}
1129
1130define <8 x i64> @vor_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
1131; RV32-LABEL: vor_vx_v8i64_unmasked:
1132; RV32:       # %bb.0:
1133; RV32-NEXT:    addi sp, sp, -16
1134; RV32-NEXT:    .cfi_def_cfa_offset 16
1135; RV32-NEXT:    sw a0, 8(sp)
1136; RV32-NEXT:    sw a1, 12(sp)
1137; RV32-NEXT:    addi a0, sp, 8
1138; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
1139; RV32-NEXT:    vlse64.v v12, (a0), zero
1140; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
1141; RV32-NEXT:    vor.vv v8, v8, v12
1142; RV32-NEXT:    addi sp, sp, 16
1143; RV32-NEXT:    .cfi_def_cfa_offset 0
1144; RV32-NEXT:    ret
1145;
1146; RV64-LABEL: vor_vx_v8i64_unmasked:
1147; RV64:       # %bb.0:
1148; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
1149; RV64-NEXT:    vor.vx v8, v8, a0
1150; RV64-NEXT:    ret
1151  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
1152  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
1153  %v = call <8 x i64> @llvm.vp.or.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl)
1154  ret <8 x i64> %v
1155}
1156
1157define <8 x i64> @vor_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
1158; CHECK-LABEL: vor_vi_v8i64:
1159; CHECK:       # %bb.0:
1160; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1161; CHECK-NEXT:    vor.vi v8, v8, 5, v0.t
1162; CHECK-NEXT:    ret
1163  %v = call <8 x i64> @llvm.vp.or.v8i64(<8 x i64> %va, <8 x i64> splat (i64 5), <8 x i1> %m, i32 %evl)
1164  ret <8 x i64> %v
1165}
1166
1167define <8 x i64> @vor_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
1168; CHECK-LABEL: vor_vi_v8i64_unmasked:
1169; CHECK:       # %bb.0:
1170; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
1171; CHECK-NEXT:    vor.vi v8, v8, 5
1172; CHECK-NEXT:    ret
1173  %v = call <8 x i64> @llvm.vp.or.v8i64(<8 x i64> %va, <8 x i64> splat (i64 5), <8 x i1> splat (i1 true), i32 %evl)
1174  ret <8 x i64> %v
1175}
1176
1177declare <16 x i64> @llvm.vp.or.v16i64(<16 x i64>, <16 x i64>, <16 x i1>, i32)
1178
1179define <16 x i64> @vor_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {
1180; CHECK-LABEL: vor_vv_v16i64:
1181; CHECK:       # %bb.0:
1182; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1183; CHECK-NEXT:    vor.vv v8, v8, v16, v0.t
1184; CHECK-NEXT:    ret
1185  %v = call <16 x i64> @llvm.vp.or.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)
1186  ret <16 x i64> %v
1187}
1188
1189define <16 x i64> @vor_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {
1190; CHECK-LABEL: vor_vv_v16i64_unmasked:
1191; CHECK:       # %bb.0:
1192; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1193; CHECK-NEXT:    vor.vv v8, v8, v16
1194; CHECK-NEXT:    ret
1195  %v = call <16 x i64> @llvm.vp.or.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)
1196  ret <16 x i64> %v
1197}
1198
1199define <16 x i64> @vor_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
1200; RV32-LABEL: vor_vx_v16i64:
1201; RV32:       # %bb.0:
1202; RV32-NEXT:    addi sp, sp, -16
1203; RV32-NEXT:    .cfi_def_cfa_offset 16
1204; RV32-NEXT:    sw a0, 8(sp)
1205; RV32-NEXT:    sw a1, 12(sp)
1206; RV32-NEXT:    addi a0, sp, 8
1207; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
1208; RV32-NEXT:    vlse64.v v16, (a0), zero
1209; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
1210; RV32-NEXT:    vor.vv v8, v8, v16, v0.t
1211; RV32-NEXT:    addi sp, sp, 16
1212; RV32-NEXT:    .cfi_def_cfa_offset 0
1213; RV32-NEXT:    ret
1214;
1215; RV64-LABEL: vor_vx_v16i64:
1216; RV64:       # %bb.0:
1217; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1218; RV64-NEXT:    vor.vx v8, v8, a0, v0.t
1219; RV64-NEXT:    ret
1220  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
1221  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
1222  %v = call <16 x i64> @llvm.vp.or.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
1223  ret <16 x i64> %v
1224}
1225
1226define <16 x i64> @vor_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
1227; RV32-LABEL: vor_vx_v16i64_unmasked:
1228; RV32:       # %bb.0:
1229; RV32-NEXT:    addi sp, sp, -16
1230; RV32-NEXT:    .cfi_def_cfa_offset 16
1231; RV32-NEXT:    sw a0, 8(sp)
1232; RV32-NEXT:    sw a1, 12(sp)
1233; RV32-NEXT:    addi a0, sp, 8
1234; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
1235; RV32-NEXT:    vlse64.v v16, (a0), zero
1236; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
1237; RV32-NEXT:    vor.vv v8, v8, v16
1238; RV32-NEXT:    addi sp, sp, 16
1239; RV32-NEXT:    .cfi_def_cfa_offset 0
1240; RV32-NEXT:    ret
1241;
1242; RV64-LABEL: vor_vx_v16i64_unmasked:
1243; RV64:       # %bb.0:
1244; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1245; RV64-NEXT:    vor.vx v8, v8, a0
1246; RV64-NEXT:    ret
1247  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
1248  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
1249  %v = call <16 x i64> @llvm.vp.or.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl)
1250  ret <16 x i64> %v
1251}
1252
1253define <16 x i64> @vor_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
1254; CHECK-LABEL: vor_vi_v16i64:
1255; CHECK:       # %bb.0:
1256; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1257; CHECK-NEXT:    vor.vi v8, v8, 5, v0.t
1258; CHECK-NEXT:    ret
1259  %v = call <16 x i64> @llvm.vp.or.v16i64(<16 x i64> %va, <16 x i64> splat (i64 5), <16 x i1> %m, i32 %evl)
1260  ret <16 x i64> %v
1261}
1262
1263define <16 x i64> @vor_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
1264; CHECK-LABEL: vor_vi_v16i64_unmasked:
1265; CHECK:       # %bb.0:
1266; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1267; CHECK-NEXT:    vor.vi v8, v8, 5
1268; CHECK-NEXT:    ret
1269  %v = call <16 x i64> @llvm.vp.or.v16i64(<16 x i64> %va, <16 x i64> splat (i64 5), <16 x i1> splat (i1 true), i32 %evl)
1270  ret <16 x i64> %v
1271}
1272