xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll (revision 74f985b793bf4005e49736f8c2cef8b5cbf7c1ab) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
4
5define <8 x i8> @vnsra_v8i16_v8i8_scalar(<8 x i16> %x, i16 %y) {
6; CHECK-LABEL: vnsra_v8i16_v8i8_scalar:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
9; CHECK-NEXT:    vnsra.wx v8, v8, a0
10; CHECK-NEXT:    ret
11  %insert = insertelement <8 x i16> poison, i16 %y, i16 0
12  %splat = shufflevector <8 x i16> %insert, <8 x i16> poison, <8 x i32> zeroinitializer
13  %a = ashr <8 x i16> %x, %splat
14  %b = trunc <8 x i16> %a to <8 x i8>
15  ret <8 x i8> %b
16}
17
18define <8 x i8> @vnsra_v8i16_v8i8_scalar_sext(<8 x i16> %x, i8 %y) {
19; CHECK-LABEL: vnsra_v8i16_v8i8_scalar_sext:
20; CHECK:       # %bb.0:
21; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
22; CHECK-NEXT:    vnsra.wx v8, v8, a0
23; CHECK-NEXT:    ret
24  %insert = insertelement <8 x i8> poison, i8 %y, i8 0
25  %splat = shufflevector <8 x i8> %insert, <8 x i8> poison, <8 x i32> zeroinitializer
26  %sext = sext <8 x i8> %splat to <8 x i16>
27  %a = ashr <8 x i16> %x, %sext
28  %b = trunc <8 x i16> %a to <8 x i8>
29  ret <8 x i8> %b
30}
31
32define <8 x i8> @vnsra_v8i16_v8i8_scalar_zext(<8 x i16> %x, i8 %y) {
33; CHECK-LABEL: vnsra_v8i16_v8i8_scalar_zext:
34; CHECK:       # %bb.0:
35; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
36; CHECK-NEXT:    vnsra.wx v8, v8, a0
37; CHECK-NEXT:    ret
38  %insert = insertelement <8 x i8> poison, i8 %y, i8 0
39  %splat = shufflevector <8 x i8> %insert, <8 x i8> poison, <8 x i32> zeroinitializer
40  %zext = zext <8 x i8> %splat to <8 x i16>
41  %a = ashr <8 x i16> %x, %zext
42  %b = trunc <8 x i16> %a to <8 x i8>
43  ret <8 x i8> %b
44}
45
46define <4 x i16> @vnsra_v4i32_v4i16_scalar(<4 x i32> %x, i32 %y) {
47; CHECK-LABEL: vnsra_v4i32_v4i16_scalar:
48; CHECK:       # %bb.0:
49; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
50; CHECK-NEXT:    vnsra.wx v8, v8, a0
51; CHECK-NEXT:    ret
52  %insert = insertelement <4 x i32> poison, i32 %y, i32 0
53  %splat = shufflevector <4 x i32> %insert, <4 x i32> poison, <4 x i32> zeroinitializer
54  %a = ashr <4 x i32> %x, %splat
55  %b = trunc <4 x i32> %a to <4 x i16>
56  ret <4 x i16> %b
57}
58
59define <4 x i16> @vnsra_v4i32_v4i16_scalar_sext(<4 x i32> %x, i16 %y) {
60; CHECK-LABEL: vnsra_v4i32_v4i16_scalar_sext:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
63; CHECK-NEXT:    vnsra.wx v8, v8, a0
64; CHECK-NEXT:    ret
65  %insert = insertelement <4 x i16> poison, i16 %y, i16 0
66  %splat = shufflevector <4 x i16> %insert, <4 x i16> poison, <4 x i32> zeroinitializer
67  %sext = sext <4 x i16> %splat to <4 x i32>
68  %a = ashr <4 x i32> %x, %sext
69  %b = trunc <4 x i32> %a to <4 x i16>
70  ret <4 x i16> %b
71}
72
73define <4 x i16> @vnsra_v4i32_v4i16_scalar_zext(<4 x i32> %x, i16 %y) {
74; CHECK-LABEL: vnsra_v4i32_v4i16_scalar_zext:
75; CHECK:       # %bb.0:
76; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
77; CHECK-NEXT:    vnsra.wx v8, v8, a0
78; CHECK-NEXT:    ret
79  %insert = insertelement <4 x i16> poison, i16 %y, i16 0
80  %splat = shufflevector <4 x i16> %insert, <4 x i16> poison, <4 x i32> zeroinitializer
81  %zext = zext <4 x i16> %splat to <4 x i32>
82  %a = ashr <4 x i32> %x, %zext
83  %b = trunc <4 x i32> %a to <4 x i16>
84  ret <4 x i16> %b
85}
86
87define <2 x i32> @vnsra_v2i64_v2i32_scalar(<2 x i64> %x, i64 %y) {
88; CHECK-LABEL: vnsra_v2i64_v2i32_scalar:
89; CHECK:       # %bb.0:
90; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
91; CHECK-NEXT:    vnsra.wx v8, v8, a0
92; CHECK-NEXT:    ret
93  %insert = insertelement <2 x i64> poison, i64 %y, i32 0
94  %splat = shufflevector <2 x i64> %insert, <2 x i64> poison, <2 x i32> zeroinitializer
95  %a = ashr <2 x i64> %x, %splat
96  %b = trunc <2 x i64> %a to <2 x i32>
97  ret <2 x i32> %b
98}
99
100define <2 x i32> @vnsra_v2i64_v2i32_scalar_sext(<2 x i64> %x, i32 %y) {
101; CHECK-LABEL: vnsra_v2i64_v2i32_scalar_sext:
102; CHECK:       # %bb.0:
103; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
104; CHECK-NEXT:    vnsra.wx v8, v8, a0
105; CHECK-NEXT:    ret
106  %insert = insertelement <2 x i32> poison, i32 %y, i32 0
107  %splat = shufflevector <2 x i32> %insert, <2 x i32> poison, <2 x i32> zeroinitializer
108  %sext = sext <2 x i32> %splat to <2 x i64>
109  %a = ashr <2 x i64> %x, %sext
110  %b = trunc <2 x i64> %a to <2 x i32>
111  ret <2 x i32> %b
112}
113
114define <2 x i32> @vnsra_v2i64_v2i32_scalar_zext(<2 x i64> %x, i32 %y) {
115; CHECK-LABEL: vnsra_v2i64_v2i32_scalar_zext:
116; CHECK:       # %bb.0:
117; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
118; CHECK-NEXT:    vnsra.wx v8, v8, a0
119; CHECK-NEXT:    ret
120  %insert = insertelement <2 x i32> poison, i32 %y, i32 0
121  %splat = shufflevector <2 x i32> %insert, <2 x i32> poison, <2 x i32> zeroinitializer
122  %zext = zext <2 x i32> %splat to <2 x i64>
123  %a = ashr <2 x i64> %x, %zext
124  %b = trunc <2 x i64> %a to <2 x i32>
125  ret <2 x i32> %b
126}
127
128define <8 x i8> @vnsra_v8i16_v8i8_imm(<8 x i16> %x) {
129; CHECK-LABEL: vnsra_v8i16_v8i8_imm:
130; CHECK:       # %bb.0:
131; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
132; CHECK-NEXT:    vnsrl.wi v8, v8, 8
133; CHECK-NEXT:    ret
134  %a = ashr <8 x i16> %x, <i16 8, i16 8, i16 8, i16 8,i16 8, i16 8, i16 8, i16 8>
135  %b = trunc <8 x i16> %a to <8 x i8>
136  ret <8 x i8> %b
137}
138
139define <4 x i16> @vnsra_v4i32_v4i16_imm(<4 x i32> %x) {
140; CHECK-LABEL: vnsra_v4i32_v4i16_imm:
141; CHECK:       # %bb.0:
142; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
143; CHECK-NEXT:    vnsrl.wi v8, v8, 16
144; CHECK-NEXT:    ret
145  %a = ashr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
146  %b = trunc <4 x i32> %a to <4 x i16>
147  ret <4 x i16> %b
148}
149
150define <2 x i32> @vnsra_v2i64_v2i32_imm(<2 x i64> %x) {
151; CHECK-LABEL: vnsra_v2i64_v2i32_imm:
152; CHECK:       # %bb.0:
153; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
154; CHECK-NEXT:    vnsrl.wi v8, v8, 31
155; CHECK-NEXT:    ret
156  %a = ashr <2 x i64> %x, <i64 31, i64 31>
157  %b = trunc <2 x i64> %a to <2 x i32>
158  ret <2 x i32> %b
159}
160
161define <8 x i8> @vnsra_v8i16_v8i8_sext(<8 x i16> %x, <8 x i8> %y) {
162; CHECK-LABEL: vnsra_v8i16_v8i8_sext:
163; CHECK:       # %bb.0:
164; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
165; CHECK-NEXT:    vnsra.wv v8, v8, v9
166; CHECK-NEXT:    ret
167  %sext = sext <8 x i8> %y to <8 x i16>
168  %a = ashr <8 x i16> %x, %sext
169  %b = trunc <8 x i16> %a to <8 x i8>
170  ret <8 x i8> %b
171}
172
173define <8 x i8> @vnsra_v8i16_v8i8_zext(<8 x i16> %x, <8 x i8> %y) {
174; CHECK-LABEL: vnsra_v8i16_v8i8_zext:
175; CHECK:       # %bb.0:
176; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
177; CHECK-NEXT:    vnsra.wv v8, v8, v9
178; CHECK-NEXT:    ret
179  %sext = zext <8 x i8> %y to <8 x i16>
180  %a = ashr <8 x i16> %x, %sext
181  %b = trunc <8 x i16> %a to <8 x i8>
182  ret <8 x i8> %b
183}
184
185define <8 x i8> @vnsrl_v8i16_v8i8_scalar(<8 x i16> %x, i16 %y) {
186; CHECK-LABEL: vnsrl_v8i16_v8i8_scalar:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
189; CHECK-NEXT:    vnsrl.wx v8, v8, a0
190; CHECK-NEXT:    ret
191  %insert = insertelement <8 x i16> poison, i16 %y, i16 0
192  %splat = shufflevector <8 x i16> %insert, <8 x i16> poison, <8 x i32> zeroinitializer
193  %a = lshr <8 x i16> %x, %splat
194  %b = trunc <8 x i16> %a to <8 x i8>
195  ret <8 x i8> %b
196}
197
198define <8 x i8> @vnsrl_v8i16_v8i8_scalar_sext(<8 x i16> %x, i8 %y) {
199; CHECK-LABEL: vnsrl_v8i16_v8i8_scalar_sext:
200; CHECK:       # %bb.0:
201; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
202; CHECK-NEXT:    vnsrl.wx v8, v8, a0
203; CHECK-NEXT:    ret
204  %insert = insertelement <8 x i8> poison, i8 %y, i16 0
205  %splat = shufflevector <8 x i8> %insert, <8 x i8> poison, <8 x i32> zeroinitializer
206  %sext = sext <8 x i8> %splat to <8 x i16>
207  %a = lshr <8 x i16> %x, %sext
208  %b = trunc <8 x i16> %a to <8 x i8>
209  ret <8 x i8> %b
210}
211
212define <8 x i8> @vnsrl_v8i16_v8i8_scalar_zext(<8 x i16> %x, i8 %y) {
213; CHECK-LABEL: vnsrl_v8i16_v8i8_scalar_zext:
214; CHECK:       # %bb.0:
215; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
216; CHECK-NEXT:    vnsrl.wx v8, v8, a0
217; CHECK-NEXT:    ret
218  %insert = insertelement <8 x i8> poison, i8 %y, i16 0
219  %splat = shufflevector <8 x i8> %insert, <8 x i8> poison, <8 x i32> zeroinitializer
220  %zext = zext <8 x i8> %splat to <8 x i16>
221  %a = lshr <8 x i16> %x, %zext
222  %b = trunc <8 x i16> %a to <8 x i8>
223  ret <8 x i8> %b
224}
225
226define <4 x i16> @vnsrl_v4i32_v4i16_scalar(<4 x i32> %x, i32 %y) {
227; CHECK-LABEL: vnsrl_v4i32_v4i16_scalar:
228; CHECK:       # %bb.0:
229; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
230; CHECK-NEXT:    vnsrl.wx v8, v8, a0
231; CHECK-NEXT:    ret
232  %insert = insertelement <4 x i32> poison, i32 %y, i32 0
233  %splat = shufflevector <4 x i32> %insert, <4 x i32> poison, <4 x i32> zeroinitializer
234  %a = lshr <4 x i32> %x, %splat
235  %b = trunc <4 x i32> %a to <4 x i16>
236  ret <4 x i16> %b
237}
238
239define <4 x i16> @vnsrl_v4i32_v4i16_scalar_sext(<4 x i32> %x, i16 %y) {
240; CHECK-LABEL: vnsrl_v4i32_v4i16_scalar_sext:
241; CHECK:       # %bb.0:
242; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
243; CHECK-NEXT:    vnsrl.wx v8, v8, a0
244; CHECK-NEXT:    ret
245  %insert = insertelement <4 x i16> poison, i16 %y, i16 0
246  %splat = shufflevector <4 x i16> %insert, <4 x i16> poison, <4 x i32> zeroinitializer
247  %sext = sext <4 x i16> %splat to <4 x i32>
248  %a = lshr <4 x i32> %x, %sext
249  %b = trunc <4 x i32> %a to <4 x i16>
250  ret <4 x i16> %b
251}
252
253define <4 x i16> @vnsrl_v4i32_v4i16_scalar_zext(<4 x i32> %x, i16 %y) {
254; CHECK-LABEL: vnsrl_v4i32_v4i16_scalar_zext:
255; CHECK:       # %bb.0:
256; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
257; CHECK-NEXT:    vnsrl.wx v8, v8, a0
258; CHECK-NEXT:    ret
259  %insert = insertelement <4 x i16> poison, i16 %y, i16 0
260  %splat = shufflevector <4 x i16> %insert, <4 x i16> poison, <4 x i32> zeroinitializer
261  %zext = zext <4 x i16> %splat to <4 x i32>
262  %a = lshr <4 x i32> %x, %zext
263  %b = trunc <4 x i32> %a to <4 x i16>
264  ret <4 x i16> %b
265}
266
267define <2 x i32> @vnsrl_v2i64_v2i32_scalar(<2 x i64> %x, i64 %y) {
268; CHECK-LABEL: vnsrl_v2i64_v2i32_scalar:
269; CHECK:       # %bb.0:
270; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
271; CHECK-NEXT:    vnsrl.wx v8, v8, a0
272; CHECK-NEXT:    ret
273  %insert = insertelement <2 x i64> poison, i64 %y, i32 0
274  %splat = shufflevector <2 x i64> %insert, <2 x i64> poison, <2 x i32> zeroinitializer
275  %a = lshr <2 x i64> %x, %splat
276  %b = trunc <2 x i64> %a to <2 x i32>
277  ret <2 x i32> %b
278}
279
280define <2 x i32> @vnsrl_v2i64_v2i32_scalar_sext(<2 x i64> %x, i32 %y) {
281; CHECK-LABEL: vnsrl_v2i64_v2i32_scalar_sext:
282; CHECK:       # %bb.0:
283; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
284; CHECK-NEXT:    vnsrl.wx v8, v8, a0
285; CHECK-NEXT:    ret
286  %insert = insertelement <2 x i32> poison, i32 %y, i32 0
287  %splat = shufflevector <2 x i32> %insert, <2 x i32> poison, <2 x i32> zeroinitializer
288  %sext = sext <2 x i32> %splat to <2 x i64>
289  %a = lshr <2 x i64> %x, %sext
290  %b = trunc <2 x i64> %a to <2 x i32>
291  ret <2 x i32> %b
292}
293
294define <2 x i32> @vnsrl_v2i64_v2i32_scalar_zext(<2 x i64> %x, i32 %y) {
295; CHECK-LABEL: vnsrl_v2i64_v2i32_scalar_zext:
296; CHECK:       # %bb.0:
297; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
298; CHECK-NEXT:    vnsrl.wx v8, v8, a0
299; CHECK-NEXT:    ret
300  %insert = insertelement <2 x i32> poison, i32 %y, i32 0
301  %splat = shufflevector <2 x i32> %insert, <2 x i32> poison, <2 x i32> zeroinitializer
302  %zext = zext <2 x i32> %splat to <2 x i64>
303  %a = lshr <2 x i64> %x, %zext
304  %b = trunc <2 x i64> %a to <2 x i32>
305  ret <2 x i32> %b
306}
307
308define <8 x i8> @vnsrl_v8i16_v8i8_imm(<8 x i16> %x) {
309; CHECK-LABEL: vnsrl_v8i16_v8i8_imm:
310; CHECK:       # %bb.0:
311; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
312; CHECK-NEXT:    vnsrl.wi v8, v8, 8
313; CHECK-NEXT:    ret
314  %a = lshr <8 x i16> %x, <i16 8, i16 8, i16 8, i16 8,i16 8, i16 8, i16 8, i16 8>
315  %b = trunc <8 x i16> %a to <8 x i8>
316  ret <8 x i8> %b
317}
318
319define <4 x i16> @vnsrl_v4i32_v4i16_imm(<4 x i32> %x) {
320; CHECK-LABEL: vnsrl_v4i32_v4i16_imm:
321; CHECK:       # %bb.0:
322; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
323; CHECK-NEXT:    vnsrl.wi v8, v8, 16
324; CHECK-NEXT:    ret
325  %a = lshr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
326  %b = trunc <4 x i32> %a to <4 x i16>
327  ret <4 x i16> %b
328}
329
330define <2 x i32> @vnsrl_v2i64_v2i32_imm(<2 x i64> %x) {
331; CHECK-LABEL: vnsrl_v2i64_v2i32_imm:
332; CHECK:       # %bb.0:
333; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
334; CHECK-NEXT:    vnsrl.wi v8, v8, 31
335; CHECK-NEXT:    ret
336  %a = lshr <2 x i64> %x, <i64 31, i64 31>
337  %b = trunc <2 x i64> %a to <2 x i32>
338  ret <2 x i32> %b
339}
340
341define <4 x i16> @vnsrl_v4i32_v4i16_sext(<4 x i32> %x, <4 x i16> %y) {
342; CHECK-LABEL: vnsrl_v4i32_v4i16_sext:
343; CHECK:       # %bb.0:
344; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
345; CHECK-NEXT:    vnsrl.wv v8, v8, v9
346; CHECK-NEXT:    ret
347  %sext = sext <4 x i16> %y to <4 x i32>
348  %a = lshr <4 x i32> %x, %sext
349  %b = trunc <4 x i32> %a to <4 x i16>
350  ret <4 x i16> %b
351}
352
353define <4 x i16> @vnsrl_v4i32_v4i16_zext(<4 x i32> %x, <4 x i16> %y) {
354; CHECK-LABEL: vnsrl_v4i32_v4i16_zext:
355; CHECK:       # %bb.0:
356; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
357; CHECK-NEXT:    vnsrl.wv v8, v8, v9
358; CHECK-NEXT:    ret
359  %zext = zext <4 x i16> %y to <4 x i32>
360  %a = lshr <4 x i32> %x, %zext
361  %b = trunc <4 x i32> %a to <4 x i16>
362  ret <4 x i16> %b
363}
364
365define <2 x i32> @vnsrl_v2i64_v2i32_sext(<2 x i64> %x, <2 x i32> %y) {
366; CHECK-LABEL: vnsrl_v2i64_v2i32_sext:
367; CHECK:       # %bb.0:
368; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
369; CHECK-NEXT:    vnsrl.wv v8, v8, v9
370; CHECK-NEXT:    ret
371  %sext = sext <2 x i32> %y to <2 x i64>
372  %a = lshr <2 x i64> %x, %sext
373  %b = trunc <2 x i64> %a to <2 x i32>
374  ret <2 x i32> %b
375}
376
377define <2 x i32> @vnsrl_v2i64_v2i32_zext(<2 x i64> %x, <2 x i32> %y) {
378; CHECK-LABEL: vnsrl_v2i64_v2i32_zext:
379; CHECK:       # %bb.0:
380; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
381; CHECK-NEXT:    vnsrl.wv v8, v8, v9
382; CHECK-NEXT:    ret
383  %zext = zext <2 x i32> %y to <2 x i64>
384  %a = lshr <2 x i64> %x, %zext
385  %b = trunc <2 x i64> %a to <2 x i32>
386  ret <2 x i32> %b
387}
388