xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll (revision b6c0f1bfa79a3a32d841ac5ab1f94c3aee3b5d90) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64
6
7declare <8 x i7> @llvm.vp.umax.v8i7(<8 x i7>, <8 x i7>, <8 x i1>, i32)
8
9define <8 x i7> @vmaxu_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroext %evl) {
10; CHECK-LABEL: vmaxu_vv_v8i7:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    li a1, 127
13; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
14; CHECK-NEXT:    vand.vx v9, v9, a1, v0.t
15; CHECK-NEXT:    vand.vx v8, v8, a1, v0.t
16; CHECK-NEXT:    vmaxu.vv v8, v8, v9, v0.t
17; CHECK-NEXT:    ret
18  %v = call <8 x i7> @llvm.vp.umax.v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 %evl)
19  ret <8 x i7> %v
20}
21
22declare <2 x i8> @llvm.vp.umax.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32)
23
24define <2 x i8> @vmaxu_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {
25; CHECK-LABEL: vmaxu_vv_v2i8:
26; CHECK:       # %bb.0:
27; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
28; CHECK-NEXT:    vmaxu.vv v8, v8, v9, v0.t
29; CHECK-NEXT:    ret
30  %v = call <2 x i8> @llvm.vp.umax.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)
31  ret <2 x i8> %v
32}
33
34define <2 x i8> @vmaxu_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {
35; CHECK-LABEL: vmaxu_vv_v2i8_unmasked:
36; CHECK:       # %bb.0:
37; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
38; CHECK-NEXT:    vmaxu.vv v8, v8, v9
39; CHECK-NEXT:    ret
40  %v = call <2 x i8> @llvm.vp.umax.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl)
41  ret <2 x i8> %v
42}
43
44define <2 x i8> @vmaxu_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
45; CHECK-LABEL: vmaxu_vx_v2i8:
46; CHECK:       # %bb.0:
47; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
48; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
49; CHECK-NEXT:    ret
50  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
51  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
52  %v = call <2 x i8> @llvm.vp.umax.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl)
53  ret <2 x i8> %v
54}
55
56define <2 x i8> @vmaxu_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
57; CHECK-LABEL: vmaxu_vx_v2i8_unmasked:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma
60; CHECK-NEXT:    vmaxu.vx v8, v8, a0
61; CHECK-NEXT:    ret
62  %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
63  %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
64  %v = call <2 x i8> @llvm.vp.umax.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl)
65  ret <2 x i8> %v
66}
67
68declare <4 x i8> @llvm.vp.umax.v4i8(<4 x i8>, <4 x i8>, <4 x i1>, i32)
69
70define <4 x i8> @vmaxu_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {
71; CHECK-LABEL: vmaxu_vv_v4i8:
72; CHECK:       # %bb.0:
73; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
74; CHECK-NEXT:    vmaxu.vv v8, v8, v9, v0.t
75; CHECK-NEXT:    ret
76  %v = call <4 x i8> @llvm.vp.umax.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)
77  ret <4 x i8> %v
78}
79
80define <4 x i8> @vmaxu_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {
81; CHECK-LABEL: vmaxu_vv_v4i8_unmasked:
82; CHECK:       # %bb.0:
83; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma
84; CHECK-NEXT:    vmaxu.vv v8, v8, v9
85; CHECK-NEXT:    ret
86  %v = call <4 x i8> @llvm.vp.umax.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl)
87  ret <4 x i8> %v
88}
89
90define <4 x i8> @vmaxu_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
91; CHECK-LABEL: vmaxu_vx_v4i8:
92; CHECK:       # %bb.0:
93; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
94; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
95; CHECK-NEXT:    ret
96  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
97  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
98  %v = call <4 x i8> @llvm.vp.umax.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl)
99  ret <4 x i8> %v
100}
101
102define <4 x i8> @vmaxu_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
103; CHECK-LABEL: vmaxu_vx_v4i8_commute:
104; CHECK:       # %bb.0:
105; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
106; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
107; CHECK-NEXT:    ret
108  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
109  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
110  %v = call <4 x i8> @llvm.vp.umax.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl)
111  ret <4 x i8> %v
112}
113
114define <4 x i8> @vmaxu_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
115; CHECK-LABEL: vmaxu_vx_v4i8_unmasked:
116; CHECK:       # %bb.0:
117; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma
118; CHECK-NEXT:    vmaxu.vx v8, v8, a0
119; CHECK-NEXT:    ret
120  %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
121  %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
122  %v = call <4 x i8> @llvm.vp.umax.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl)
123  ret <4 x i8> %v
124}
125
126declare <5 x i8> @llvm.vp.umax.v5i8(<5 x i8>, <5 x i8>, <5 x i1>, i32)
127
128define <5 x i8> @vmaxu_vv_v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 zeroext %evl) {
129; CHECK-LABEL: vmaxu_vv_v5i8:
130; CHECK:       # %bb.0:
131; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
132; CHECK-NEXT:    vmaxu.vv v8, v8, v9, v0.t
133; CHECK-NEXT:    ret
134  %v = call <5 x i8> @llvm.vp.umax.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl)
135  ret <5 x i8> %v
136}
137
138define <5 x i8> @vmaxu_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %evl) {
139; CHECK-LABEL: vmaxu_vv_v5i8_unmasked:
140; CHECK:       # %bb.0:
141; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
142; CHECK-NEXT:    vmaxu.vv v8, v8, v9
143; CHECK-NEXT:    ret
144  %v = call <5 x i8> @llvm.vp.umax.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl)
145  ret <5 x i8> %v
146}
147
148define <5 x i8> @vmaxu_vx_v5i8(<5 x i8> %va, i8 %b, <5 x i1> %m, i32 zeroext %evl) {
149; CHECK-LABEL: vmaxu_vx_v5i8:
150; CHECK:       # %bb.0:
151; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
152; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
153; CHECK-NEXT:    ret
154  %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
155  %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer
156  %v = call <5 x i8> @llvm.vp.umax.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl)
157  ret <5 x i8> %v
158}
159
160define <5 x i8> @vmaxu_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) {
161; CHECK-LABEL: vmaxu_vx_v5i8_unmasked:
162; CHECK:       # %bb.0:
163; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
164; CHECK-NEXT:    vmaxu.vx v8, v8, a0
165; CHECK-NEXT:    ret
166  %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0
167  %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer
168  %v = call <5 x i8> @llvm.vp.umax.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl)
169  ret <5 x i8> %v
170}
171
172declare <8 x i8> @llvm.vp.umax.v8i8(<8 x i8>, <8 x i8>, <8 x i1>, i32)
173
174define <8 x i8> @vmaxu_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {
175; CHECK-LABEL: vmaxu_vv_v8i8:
176; CHECK:       # %bb.0:
177; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
178; CHECK-NEXT:    vmaxu.vv v8, v8, v9, v0.t
179; CHECK-NEXT:    ret
180  %v = call <8 x i8> @llvm.vp.umax.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)
181  ret <8 x i8> %v
182}
183
184define <8 x i8> @vmaxu_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {
185; CHECK-LABEL: vmaxu_vv_v8i8_unmasked:
186; CHECK:       # %bb.0:
187; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma
188; CHECK-NEXT:    vmaxu.vv v8, v8, v9
189; CHECK-NEXT:    ret
190  %v = call <8 x i8> @llvm.vp.umax.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl)
191  ret <8 x i8> %v
192}
193
194define <8 x i8> @vmaxu_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {
195; CHECK-LABEL: vmaxu_vx_v8i8:
196; CHECK:       # %bb.0:
197; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
198; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
199; CHECK-NEXT:    ret
200  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
201  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
202  %v = call <8 x i8> @llvm.vp.umax.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl)
203  ret <8 x i8> %v
204}
205
206define <8 x i8> @vmaxu_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
207; CHECK-LABEL: vmaxu_vx_v8i8_unmasked:
208; CHECK:       # %bb.0:
209; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma
210; CHECK-NEXT:    vmaxu.vx v8, v8, a0
211; CHECK-NEXT:    ret
212  %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0
213  %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer
214  %v = call <8 x i8> @llvm.vp.umax.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl)
215  ret <8 x i8> %v
216}
217
218declare <16 x i8> @llvm.vp.umax.v16i8(<16 x i8>, <16 x i8>, <16 x i1>, i32)
219
220define <16 x i8> @vmaxu_vv_v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 zeroext %evl) {
221; CHECK-LABEL: vmaxu_vv_v16i8:
222; CHECK:       # %bb.0:
223; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
224; CHECK-NEXT:    vmaxu.vv v8, v8, v9, v0.t
225; CHECK-NEXT:    ret
226  %v = call <16 x i8> @llvm.vp.umax.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl)
227  ret <16 x i8> %v
228}
229
230define <16 x i8> @vmaxu_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext %evl) {
231; CHECK-LABEL: vmaxu_vv_v16i8_unmasked:
232; CHECK:       # %bb.0:
233; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
234; CHECK-NEXT:    vmaxu.vv v8, v8, v9
235; CHECK-NEXT:    ret
236  %v = call <16 x i8> @llvm.vp.umax.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl)
237  ret <16 x i8> %v
238}
239
240define <16 x i8> @vmaxu_vx_v16i8(<16 x i8> %va, i8 %b, <16 x i1> %m, i32 zeroext %evl) {
241; CHECK-LABEL: vmaxu_vx_v16i8:
242; CHECK:       # %bb.0:
243; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
244; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
245; CHECK-NEXT:    ret
246  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
247  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
248  %v = call <16 x i8> @llvm.vp.umax.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl)
249  ret <16 x i8> %v
250}
251
252define <16 x i8> @vmaxu_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) {
253; CHECK-LABEL: vmaxu_vx_v16i8_unmasked:
254; CHECK:       # %bb.0:
255; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
256; CHECK-NEXT:    vmaxu.vx v8, v8, a0
257; CHECK-NEXT:    ret
258  %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0
259  %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer
260  %v = call <16 x i8> @llvm.vp.umax.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl)
261  ret <16 x i8> %v
262}
263
264declare <256 x i8> @llvm.vp.umax.v258i8(<256 x i8>, <256 x i8>, <256 x i1>, i32)
265
266define <256 x i8> @vmaxu_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zeroext %evl) {
267; CHECK-LABEL: vmaxu_vx_v258i8:
268; CHECK:       # %bb.0:
269; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
270; CHECK-NEXT:    vmv1r.v v24, v0
271; CHECK-NEXT:    li a3, 128
272; CHECK-NEXT:    vsetvli zero, a3, e8, m8, ta, ma
273; CHECK-NEXT:    vlm.v v0, (a1)
274; CHECK-NEXT:    addi a1, a2, -128
275; CHECK-NEXT:    sltu a4, a2, a1
276; CHECK-NEXT:    addi a4, a4, -1
277; CHECK-NEXT:    and a1, a4, a1
278; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
279; CHECK-NEXT:    vmaxu.vx v16, v16, a0, v0.t
280; CHECK-NEXT:    bltu a2, a3, .LBB22_2
281; CHECK-NEXT:  # %bb.1:
282; CHECK-NEXT:    li a2, 128
283; CHECK-NEXT:  .LBB22_2:
284; CHECK-NEXT:    vmv1r.v v0, v24
285; CHECK-NEXT:    vsetvli zero, a2, e8, m8, ta, ma
286; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
287; CHECK-NEXT:    ret
288  %elt.head = insertelement <256 x i8> poison, i8 %b, i32 0
289  %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer
290  %v = call <256 x i8> @llvm.vp.umax.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 %evl)
291  ret <256 x i8> %v
292}
293
294define <256 x i8> @vmaxu_vx_v258i8_unmasked(<256 x i8> %va, i8 %b, i32 zeroext %evl) {
295; CHECK-LABEL: vmaxu_vx_v258i8_unmasked:
296; CHECK:       # %bb.0:
297; CHECK-NEXT:    li a3, 128
298; CHECK-NEXT:    mv a2, a1
299; CHECK-NEXT:    bltu a1, a3, .LBB23_2
300; CHECK-NEXT:  # %bb.1:
301; CHECK-NEXT:    li a2, 128
302; CHECK-NEXT:  .LBB23_2:
303; CHECK-NEXT:    vsetvli zero, a2, e8, m8, ta, ma
304; CHECK-NEXT:    vmaxu.vx v8, v8, a0
305; CHECK-NEXT:    addi a2, a1, -128
306; CHECK-NEXT:    sltu a1, a1, a2
307; CHECK-NEXT:    addi a1, a1, -1
308; CHECK-NEXT:    and a1, a1, a2
309; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
310; CHECK-NEXT:    vmaxu.vx v16, v16, a0
311; CHECK-NEXT:    ret
312  %elt.head = insertelement <256 x i8> poison, i8 %b, i32 0
313  %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer
314  %v = call <256 x i8> @llvm.vp.umax.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> splat (i1 true), i32 %evl)
315  ret <256 x i8> %v
316}
317
318; Test splitting when the %evl is a known constant.
319
320define <256 x i8> @vmaxu_vx_v258i8_evl129(<256 x i8> %va, i8 %b, <256 x i1> %m) {
321; CHECK-LABEL: vmaxu_vx_v258i8_evl129:
322; CHECK:       # %bb.0:
323; CHECK-NEXT:    li a2, 128
324; CHECK-NEXT:    vsetvli zero, a2, e8, m8, ta, ma
325; CHECK-NEXT:    vlm.v v24, (a1)
326; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
327; CHECK-NEXT:    vmv1r.v v0, v24
328; CHECK-NEXT:    vsetivli zero, 1, e8, m8, ta, ma
329; CHECK-NEXT:    vmaxu.vx v16, v16, a0, v0.t
330; CHECK-NEXT:    ret
331  %elt.head = insertelement <256 x i8> poison, i8 %b, i32 0
332  %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer
333  %v = call <256 x i8> @llvm.vp.umax.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 129)
334  ret <256 x i8> %v
335}
336
337; The upper half is doing nothing.
338
339define <256 x i8> @vmaxu_vx_v258i8_evl128(<256 x i8> %va, i8 %b, <256 x i1> %m) {
340; CHECK-LABEL: vmaxu_vx_v258i8_evl128:
341; CHECK:       # %bb.0:
342; CHECK-NEXT:    li a1, 128
343; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma
344; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
345; CHECK-NEXT:    ret
346  %elt.head = insertelement <256 x i8> poison, i8 %b, i32 0
347  %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer
348  %v = call <256 x i8> @llvm.vp.umax.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 128)
349  ret <256 x i8> %v
350}
351
352declare <2 x i16> @llvm.vp.umax.v2i16(<2 x i16>, <2 x i16>, <2 x i1>, i32)
353
354define <2 x i16> @vmaxu_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {
355; CHECK-LABEL: vmaxu_vv_v2i16:
356; CHECK:       # %bb.0:
357; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
358; CHECK-NEXT:    vmaxu.vv v8, v8, v9, v0.t
359; CHECK-NEXT:    ret
360  %v = call <2 x i16> @llvm.vp.umax.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)
361  ret <2 x i16> %v
362}
363
364define <2 x i16> @vmaxu_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {
365; CHECK-LABEL: vmaxu_vv_v2i16_unmasked:
366; CHECK:       # %bb.0:
367; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
368; CHECK-NEXT:    vmaxu.vv v8, v8, v9
369; CHECK-NEXT:    ret
370  %v = call <2 x i16> @llvm.vp.umax.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl)
371  ret <2 x i16> %v
372}
373
374define <2 x i16> @vmaxu_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {
375; CHECK-LABEL: vmaxu_vx_v2i16:
376; CHECK:       # %bb.0:
377; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
378; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
379; CHECK-NEXT:    ret
380  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
381  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
382  %v = call <2 x i16> @llvm.vp.umax.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl)
383  ret <2 x i16> %v
384}
385
386define <2 x i16> @vmaxu_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {
387; CHECK-LABEL: vmaxu_vx_v2i16_unmasked:
388; CHECK:       # %bb.0:
389; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma
390; CHECK-NEXT:    vmaxu.vx v8, v8, a0
391; CHECK-NEXT:    ret
392  %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0
393  %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer
394  %v = call <2 x i16> @llvm.vp.umax.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl)
395  ret <2 x i16> %v
396}
397
398declare <4 x i16> @llvm.vp.umax.v4i16(<4 x i16>, <4 x i16>, <4 x i1>, i32)
399
400define <4 x i16> @vmaxu_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {
401; CHECK-LABEL: vmaxu_vv_v4i16:
402; CHECK:       # %bb.0:
403; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
404; CHECK-NEXT:    vmaxu.vv v8, v8, v9, v0.t
405; CHECK-NEXT:    ret
406  %v = call <4 x i16> @llvm.vp.umax.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)
407  ret <4 x i16> %v
408}
409
410define <4 x i16> @vmaxu_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {
411; CHECK-LABEL: vmaxu_vv_v4i16_unmasked:
412; CHECK:       # %bb.0:
413; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
414; CHECK-NEXT:    vmaxu.vv v8, v8, v9
415; CHECK-NEXT:    ret
416  %v = call <4 x i16> @llvm.vp.umax.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl)
417  ret <4 x i16> %v
418}
419
420define <4 x i16> @vmaxu_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {
421; CHECK-LABEL: vmaxu_vx_v4i16:
422; CHECK:       # %bb.0:
423; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
424; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
425; CHECK-NEXT:    ret
426  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
427  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
428  %v = call <4 x i16> @llvm.vp.umax.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl)
429  ret <4 x i16> %v
430}
431
432define <4 x i16> @vmaxu_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {
433; CHECK-LABEL: vmaxu_vx_v4i16_unmasked:
434; CHECK:       # %bb.0:
435; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma
436; CHECK-NEXT:    vmaxu.vx v8, v8, a0
437; CHECK-NEXT:    ret
438  %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0
439  %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer
440  %v = call <4 x i16> @llvm.vp.umax.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl)
441  ret <4 x i16> %v
442}
443
444declare <8 x i16> @llvm.vp.umax.v8i16(<8 x i16>, <8 x i16>, <8 x i1>, i32)
445
446define <8 x i16> @vmaxu_vv_v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 zeroext %evl) {
447; CHECK-LABEL: vmaxu_vv_v8i16:
448; CHECK:       # %bb.0:
449; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
450; CHECK-NEXT:    vmaxu.vv v8, v8, v9, v0.t
451; CHECK-NEXT:    ret
452  %v = call <8 x i16> @llvm.vp.umax.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl)
453  ret <8 x i16> %v
454}
455
456define <8 x i16> @vmaxu_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext %evl) {
457; CHECK-LABEL: vmaxu_vv_v8i16_unmasked:
458; CHECK:       # %bb.0:
459; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
460; CHECK-NEXT:    vmaxu.vv v8, v8, v9
461; CHECK-NEXT:    ret
462  %v = call <8 x i16> @llvm.vp.umax.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl)
463  ret <8 x i16> %v
464}
465
466define <8 x i16> @vmaxu_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {
467; CHECK-LABEL: vmaxu_vx_v8i16:
468; CHECK:       # %bb.0:
469; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
470; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
471; CHECK-NEXT:    ret
472  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
473  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
474  %v = call <8 x i16> @llvm.vp.umax.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl)
475  ret <8 x i16> %v
476}
477
478define <8 x i16> @vmaxu_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) {
479; CHECK-LABEL: vmaxu_vx_v8i16_unmasked:
480; CHECK:       # %bb.0:
481; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
482; CHECK-NEXT:    vmaxu.vx v8, v8, a0
483; CHECK-NEXT:    ret
484  %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
485  %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
486  %v = call <8 x i16> @llvm.vp.umax.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl)
487  ret <8 x i16> %v
488}
489
490declare <16 x i16> @llvm.vp.umax.v16i16(<16 x i16>, <16 x i16>, <16 x i1>, i32)
491
492define <16 x i16> @vmaxu_vv_v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 zeroext %evl) {
493; CHECK-LABEL: vmaxu_vv_v16i16:
494; CHECK:       # %bb.0:
495; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
496; CHECK-NEXT:    vmaxu.vv v8, v8, v10, v0.t
497; CHECK-NEXT:    ret
498  %v = call <16 x i16> @llvm.vp.umax.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl)
499  ret <16 x i16> %v
500}
501
502define <16 x i16> @vmaxu_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zeroext %evl) {
503; CHECK-LABEL: vmaxu_vv_v16i16_unmasked:
504; CHECK:       # %bb.0:
505; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
506; CHECK-NEXT:    vmaxu.vv v8, v8, v10
507; CHECK-NEXT:    ret
508  %v = call <16 x i16> @llvm.vp.umax.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl)
509  ret <16 x i16> %v
510}
511
512define <16 x i16> @vmaxu_vx_v16i16(<16 x i16> %va, i16 %b, <16 x i1> %m, i32 zeroext %evl) {
513; CHECK-LABEL: vmaxu_vx_v16i16:
514; CHECK:       # %bb.0:
515; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
516; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
517; CHECK-NEXT:    ret
518  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
519  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
520  %v = call <16 x i16> @llvm.vp.umax.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl)
521  ret <16 x i16> %v
522}
523
524define <16 x i16> @vmaxu_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %evl) {
525; CHECK-LABEL: vmaxu_vx_v16i16_unmasked:
526; CHECK:       # %bb.0:
527; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma
528; CHECK-NEXT:    vmaxu.vx v8, v8, a0
529; CHECK-NEXT:    ret
530  %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0
531  %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer
532  %v = call <16 x i16> @llvm.vp.umax.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl)
533  ret <16 x i16> %v
534}
535
536declare <2 x i32> @llvm.vp.umax.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32)
537
538define <2 x i32> @vmaxu_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {
539; CHECK-LABEL: vmaxu_vv_v2i32:
540; CHECK:       # %bb.0:
541; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
542; CHECK-NEXT:    vmaxu.vv v8, v8, v9, v0.t
543; CHECK-NEXT:    ret
544  %v = call <2 x i32> @llvm.vp.umax.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)
545  ret <2 x i32> %v
546}
547
548define <2 x i32> @vmaxu_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {
549; CHECK-LABEL: vmaxu_vv_v2i32_unmasked:
550; CHECK:       # %bb.0:
551; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
552; CHECK-NEXT:    vmaxu.vv v8, v8, v9
553; CHECK-NEXT:    ret
554  %v = call <2 x i32> @llvm.vp.umax.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl)
555  ret <2 x i32> %v
556}
557
558define <2 x i32> @vmaxu_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {
559; CHECK-LABEL: vmaxu_vx_v2i32:
560; CHECK:       # %bb.0:
561; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
562; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
563; CHECK-NEXT:    ret
564  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
565  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
566  %v = call <2 x i32> @llvm.vp.umax.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl)
567  ret <2 x i32> %v
568}
569
570define <2 x i32> @vmaxu_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {
571; CHECK-LABEL: vmaxu_vx_v2i32_unmasked:
572; CHECK:       # %bb.0:
573; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma
574; CHECK-NEXT:    vmaxu.vx v8, v8, a0
575; CHECK-NEXT:    ret
576  %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0
577  %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer
578  %v = call <2 x i32> @llvm.vp.umax.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl)
579  ret <2 x i32> %v
580}
581
582declare <4 x i32> @llvm.vp.umax.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
583
584define <4 x i32> @vmaxu_vv_v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 zeroext %evl) {
585; CHECK-LABEL: vmaxu_vv_v4i32:
586; CHECK:       # %bb.0:
587; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
588; CHECK-NEXT:    vmaxu.vv v8, v8, v9, v0.t
589; CHECK-NEXT:    ret
590  %v = call <4 x i32> @llvm.vp.umax.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl)
591  ret <4 x i32> %v
592}
593
594define <4 x i32> @vmaxu_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext %evl) {
595; CHECK-LABEL: vmaxu_vv_v4i32_unmasked:
596; CHECK:       # %bb.0:
597; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
598; CHECK-NEXT:    vmaxu.vv v8, v8, v9
599; CHECK-NEXT:    ret
600  %v = call <4 x i32> @llvm.vp.umax.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl)
601  ret <4 x i32> %v
602}
603
604define <4 x i32> @vmaxu_vx_v4i32(<4 x i32> %va, i32 %b, <4 x i1> %m, i32 zeroext %evl) {
605; CHECK-LABEL: vmaxu_vx_v4i32:
606; CHECK:       # %bb.0:
607; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
608; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
609; CHECK-NEXT:    ret
610  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
611  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
612  %v = call <4 x i32> @llvm.vp.umax.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl)
613  ret <4 x i32> %v
614}
615
616define <4 x i32> @vmaxu_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) {
617; CHECK-LABEL: vmaxu_vx_v4i32_unmasked:
618; CHECK:       # %bb.0:
619; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
620; CHECK-NEXT:    vmaxu.vx v8, v8, a0
621; CHECK-NEXT:    ret
622  %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0
623  %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer
624  %v = call <4 x i32> @llvm.vp.umax.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl)
625  ret <4 x i32> %v
626}
627
628declare <8 x i32> @llvm.vp.umax.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
629
630define <8 x i32> @vmaxu_vv_v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 zeroext %evl) {
631; CHECK-LABEL: vmaxu_vv_v8i32:
632; CHECK:       # %bb.0:
633; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
634; CHECK-NEXT:    vmaxu.vv v8, v8, v10, v0.t
635; CHECK-NEXT:    ret
636  %v = call <8 x i32> @llvm.vp.umax.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl)
637  ret <8 x i32> %v
638}
639
640define <8 x i32> @vmaxu_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext %evl) {
641; CHECK-LABEL: vmaxu_vv_v8i32_unmasked:
642; CHECK:       # %bb.0:
643; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
644; CHECK-NEXT:    vmaxu.vv v8, v8, v10
645; CHECK-NEXT:    ret
646  %v = call <8 x i32> @llvm.vp.umax.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl)
647  ret <8 x i32> %v
648}
649
650define <8 x i32> @vmaxu_vx_v8i32(<8 x i32> %va, i32 %b, <8 x i1> %m, i32 zeroext %evl) {
651; CHECK-LABEL: vmaxu_vx_v8i32:
652; CHECK:       # %bb.0:
653; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
654; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
655; CHECK-NEXT:    ret
656  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
657  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
658  %v = call <8 x i32> @llvm.vp.umax.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl)
659  ret <8 x i32> %v
660}
661
662define <8 x i32> @vmaxu_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) {
663; CHECK-LABEL: vmaxu_vx_v8i32_unmasked:
664; CHECK:       # %bb.0:
665; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma
666; CHECK-NEXT:    vmaxu.vx v8, v8, a0
667; CHECK-NEXT:    ret
668  %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0
669  %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer
670  %v = call <8 x i32> @llvm.vp.umax.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl)
671  ret <8 x i32> %v
672}
673
674declare <16 x i32> @llvm.vp.umax.v16i32(<16 x i32>, <16 x i32>, <16 x i1>, i32)
675
676define <16 x i32> @vmaxu_vv_v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 zeroext %evl) {
677; CHECK-LABEL: vmaxu_vv_v16i32:
678; CHECK:       # %bb.0:
679; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
680; CHECK-NEXT:    vmaxu.vv v8, v8, v12, v0.t
681; CHECK-NEXT:    ret
682  %v = call <16 x i32> @llvm.vp.umax.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl)
683  ret <16 x i32> %v
684}
685
686define <16 x i32> @vmaxu_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zeroext %evl) {
687; CHECK-LABEL: vmaxu_vv_v16i32_unmasked:
688; CHECK:       # %bb.0:
689; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
690; CHECK-NEXT:    vmaxu.vv v8, v8, v12
691; CHECK-NEXT:    ret
692  %v = call <16 x i32> @llvm.vp.umax.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl)
693  ret <16 x i32> %v
694}
695
696define <16 x i32> @vmaxu_vx_v16i32(<16 x i32> %va, i32 %b, <16 x i1> %m, i32 zeroext %evl) {
697; CHECK-LABEL: vmaxu_vx_v16i32:
698; CHECK:       # %bb.0:
699; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
700; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
701; CHECK-NEXT:    ret
702  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
703  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
704  %v = call <16 x i32> @llvm.vp.umax.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl)
705  ret <16 x i32> %v
706}
707
708define <16 x i32> @vmaxu_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %evl) {
709; CHECK-LABEL: vmaxu_vx_v16i32_unmasked:
710; CHECK:       # %bb.0:
711; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma
712; CHECK-NEXT:    vmaxu.vx v8, v8, a0
713; CHECK-NEXT:    ret
714  %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0
715  %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer
716  %v = call <16 x i32> @llvm.vp.umax.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl)
717  ret <16 x i32> %v
718}
719
720declare <2 x i64> @llvm.vp.umax.v2i64(<2 x i64>, <2 x i64>, <2 x i1>, i32)
721
722define <2 x i64> @vmaxu_vv_v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 zeroext %evl) {
723; CHECK-LABEL: vmaxu_vv_v2i64:
724; CHECK:       # %bb.0:
725; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
726; CHECK-NEXT:    vmaxu.vv v8, v8, v9, v0.t
727; CHECK-NEXT:    ret
728  %v = call <2 x i64> @llvm.vp.umax.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl)
729  ret <2 x i64> %v
730}
731
732define <2 x i64> @vmaxu_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext %evl) {
733; CHECK-LABEL: vmaxu_vv_v2i64_unmasked:
734; CHECK:       # %bb.0:
735; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
736; CHECK-NEXT:    vmaxu.vv v8, v8, v9
737; CHECK-NEXT:    ret
738  %v = call <2 x i64> @llvm.vp.umax.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl)
739  ret <2 x i64> %v
740}
741
742define <2 x i64> @vmaxu_vx_v2i64(<2 x i64> %va, i64 %b, <2 x i1> %m, i32 zeroext %evl) {
743; RV32-LABEL: vmaxu_vx_v2i64:
744; RV32:       # %bb.0:
745; RV32-NEXT:    addi sp, sp, -16
746; RV32-NEXT:    .cfi_def_cfa_offset 16
747; RV32-NEXT:    sw a0, 8(sp)
748; RV32-NEXT:    sw a1, 12(sp)
749; RV32-NEXT:    addi a0, sp, 8
750; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
751; RV32-NEXT:    vlse64.v v9, (a0), zero
752; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
753; RV32-NEXT:    vmaxu.vv v8, v8, v9, v0.t
754; RV32-NEXT:    addi sp, sp, 16
755; RV32-NEXT:    .cfi_def_cfa_offset 0
756; RV32-NEXT:    ret
757;
758; RV64-LABEL: vmaxu_vx_v2i64:
759; RV64:       # %bb.0:
760; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
761; RV64-NEXT:    vmaxu.vx v8, v8, a0, v0.t
762; RV64-NEXT:    ret
763  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
764  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
765  %v = call <2 x i64> @llvm.vp.umax.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl)
766  ret <2 x i64> %v
767}
768
769define <2 x i64> @vmaxu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) {
770; RV32-LABEL: vmaxu_vx_v2i64_unmasked:
771; RV32:       # %bb.0:
772; RV32-NEXT:    addi sp, sp, -16
773; RV32-NEXT:    .cfi_def_cfa_offset 16
774; RV32-NEXT:    sw a0, 8(sp)
775; RV32-NEXT:    sw a1, 12(sp)
776; RV32-NEXT:    addi a0, sp, 8
777; RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
778; RV32-NEXT:    vlse64.v v9, (a0), zero
779; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma
780; RV32-NEXT:    vmaxu.vv v8, v8, v9
781; RV32-NEXT:    addi sp, sp, 16
782; RV32-NEXT:    .cfi_def_cfa_offset 0
783; RV32-NEXT:    ret
784;
785; RV64-LABEL: vmaxu_vx_v2i64_unmasked:
786; RV64:       # %bb.0:
787; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
788; RV64-NEXT:    vmaxu.vx v8, v8, a0
789; RV64-NEXT:    ret
790  %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0
791  %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer
792  %v = call <2 x i64> @llvm.vp.umax.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl)
793  ret <2 x i64> %v
794}
795
796declare <4 x i64> @llvm.vp.umax.v4i64(<4 x i64>, <4 x i64>, <4 x i1>, i32)
797
798define <4 x i64> @vmaxu_vv_v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 zeroext %evl) {
799; CHECK-LABEL: vmaxu_vv_v4i64:
800; CHECK:       # %bb.0:
801; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
802; CHECK-NEXT:    vmaxu.vv v8, v8, v10, v0.t
803; CHECK-NEXT:    ret
804  %v = call <4 x i64> @llvm.vp.umax.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl)
805  ret <4 x i64> %v
806}
807
808define <4 x i64> @vmaxu_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext %evl) {
809; CHECK-LABEL: vmaxu_vv_v4i64_unmasked:
810; CHECK:       # %bb.0:
811; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
812; CHECK-NEXT:    vmaxu.vv v8, v8, v10
813; CHECK-NEXT:    ret
814  %v = call <4 x i64> @llvm.vp.umax.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl)
815  ret <4 x i64> %v
816}
817
818define <4 x i64> @vmaxu_vx_v4i64(<4 x i64> %va, i64 %b, <4 x i1> %m, i32 zeroext %evl) {
819; RV32-LABEL: vmaxu_vx_v4i64:
820; RV32:       # %bb.0:
821; RV32-NEXT:    addi sp, sp, -16
822; RV32-NEXT:    .cfi_def_cfa_offset 16
823; RV32-NEXT:    sw a0, 8(sp)
824; RV32-NEXT:    sw a1, 12(sp)
825; RV32-NEXT:    addi a0, sp, 8
826; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
827; RV32-NEXT:    vlse64.v v10, (a0), zero
828; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
829; RV32-NEXT:    vmaxu.vv v8, v8, v10, v0.t
830; RV32-NEXT:    addi sp, sp, 16
831; RV32-NEXT:    .cfi_def_cfa_offset 0
832; RV32-NEXT:    ret
833;
834; RV64-LABEL: vmaxu_vx_v4i64:
835; RV64:       # %bb.0:
836; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
837; RV64-NEXT:    vmaxu.vx v8, v8, a0, v0.t
838; RV64-NEXT:    ret
839  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
840  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
841  %v = call <4 x i64> @llvm.vp.umax.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl)
842  ret <4 x i64> %v
843}
844
845define <4 x i64> @vmaxu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) {
846; RV32-LABEL: vmaxu_vx_v4i64_unmasked:
847; RV32:       # %bb.0:
848; RV32-NEXT:    addi sp, sp, -16
849; RV32-NEXT:    .cfi_def_cfa_offset 16
850; RV32-NEXT:    sw a0, 8(sp)
851; RV32-NEXT:    sw a1, 12(sp)
852; RV32-NEXT:    addi a0, sp, 8
853; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
854; RV32-NEXT:    vlse64.v v10, (a0), zero
855; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma
856; RV32-NEXT:    vmaxu.vv v8, v8, v10
857; RV32-NEXT:    addi sp, sp, 16
858; RV32-NEXT:    .cfi_def_cfa_offset 0
859; RV32-NEXT:    ret
860;
861; RV64-LABEL: vmaxu_vx_v4i64_unmasked:
862; RV64:       # %bb.0:
863; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
864; RV64-NEXT:    vmaxu.vx v8, v8, a0
865; RV64-NEXT:    ret
866  %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0
867  %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer
868  %v = call <4 x i64> @llvm.vp.umax.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl)
869  ret <4 x i64> %v
870}
871
872declare <8 x i64> @llvm.vp.umax.v8i64(<8 x i64>, <8 x i64>, <8 x i1>, i32)
873
874define <8 x i64> @vmaxu_vv_v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 zeroext %evl) {
875; CHECK-LABEL: vmaxu_vv_v8i64:
876; CHECK:       # %bb.0:
877; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
878; CHECK-NEXT:    vmaxu.vv v8, v8, v12, v0.t
879; CHECK-NEXT:    ret
880  %v = call <8 x i64> @llvm.vp.umax.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl)
881  ret <8 x i64> %v
882}
883
884define <8 x i64> @vmaxu_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext %evl) {
885; CHECK-LABEL: vmaxu_vv_v8i64_unmasked:
886; CHECK:       # %bb.0:
887; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
888; CHECK-NEXT:    vmaxu.vv v8, v8, v12
889; CHECK-NEXT:    ret
890  %v = call <8 x i64> @llvm.vp.umax.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl)
891  ret <8 x i64> %v
892}
893
894define <8 x i64> @vmaxu_vx_v8i64(<8 x i64> %va, i64 %b, <8 x i1> %m, i32 zeroext %evl) {
895; RV32-LABEL: vmaxu_vx_v8i64:
896; RV32:       # %bb.0:
897; RV32-NEXT:    addi sp, sp, -16
898; RV32-NEXT:    .cfi_def_cfa_offset 16
899; RV32-NEXT:    sw a0, 8(sp)
900; RV32-NEXT:    sw a1, 12(sp)
901; RV32-NEXT:    addi a0, sp, 8
902; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
903; RV32-NEXT:    vlse64.v v12, (a0), zero
904; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
905; RV32-NEXT:    vmaxu.vv v8, v8, v12, v0.t
906; RV32-NEXT:    addi sp, sp, 16
907; RV32-NEXT:    .cfi_def_cfa_offset 0
908; RV32-NEXT:    ret
909;
910; RV64-LABEL: vmaxu_vx_v8i64:
911; RV64:       # %bb.0:
912; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
913; RV64-NEXT:    vmaxu.vx v8, v8, a0, v0.t
914; RV64-NEXT:    ret
915  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
916  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
917  %v = call <8 x i64> @llvm.vp.umax.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl)
918  ret <8 x i64> %v
919}
920
921define <8 x i64> @vmaxu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) {
922; RV32-LABEL: vmaxu_vx_v8i64_unmasked:
923; RV32:       # %bb.0:
924; RV32-NEXT:    addi sp, sp, -16
925; RV32-NEXT:    .cfi_def_cfa_offset 16
926; RV32-NEXT:    sw a0, 8(sp)
927; RV32-NEXT:    sw a1, 12(sp)
928; RV32-NEXT:    addi a0, sp, 8
929; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
930; RV32-NEXT:    vlse64.v v12, (a0), zero
931; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma
932; RV32-NEXT:    vmaxu.vv v8, v8, v12
933; RV32-NEXT:    addi sp, sp, 16
934; RV32-NEXT:    .cfi_def_cfa_offset 0
935; RV32-NEXT:    ret
936;
937; RV64-LABEL: vmaxu_vx_v8i64_unmasked:
938; RV64:       # %bb.0:
939; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma
940; RV64-NEXT:    vmaxu.vx v8, v8, a0
941; RV64-NEXT:    ret
942  %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0
943  %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer
944  %v = call <8 x i64> @llvm.vp.umax.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl)
945  ret <8 x i64> %v
946}
947
948declare <16 x i64> @llvm.vp.umax.v16i64(<16 x i64>, <16 x i64>, <16 x i1>, i32)
949
950define <16 x i64> @vmaxu_vv_v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 zeroext %evl) {
951; CHECK-LABEL: vmaxu_vv_v16i64:
952; CHECK:       # %bb.0:
953; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
954; CHECK-NEXT:    vmaxu.vv v8, v8, v16, v0.t
955; CHECK-NEXT:    ret
956  %v = call <16 x i64> @llvm.vp.umax.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl)
957  ret <16 x i64> %v
958}
959
960define <16 x i64> @vmaxu_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zeroext %evl) {
961; CHECK-LABEL: vmaxu_vv_v16i64_unmasked:
962; CHECK:       # %bb.0:
963; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
964; CHECK-NEXT:    vmaxu.vv v8, v8, v16
965; CHECK-NEXT:    ret
966  %v = call <16 x i64> @llvm.vp.umax.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl)
967  ret <16 x i64> %v
968}
969
970define <16 x i64> @vmaxu_vx_v16i64(<16 x i64> %va, i64 %b, <16 x i1> %m, i32 zeroext %evl) {
971; RV32-LABEL: vmaxu_vx_v16i64:
972; RV32:       # %bb.0:
973; RV32-NEXT:    addi sp, sp, -16
974; RV32-NEXT:    .cfi_def_cfa_offset 16
975; RV32-NEXT:    sw a0, 8(sp)
976; RV32-NEXT:    sw a1, 12(sp)
977; RV32-NEXT:    addi a0, sp, 8
978; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
979; RV32-NEXT:    vlse64.v v16, (a0), zero
980; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
981; RV32-NEXT:    vmaxu.vv v8, v8, v16, v0.t
982; RV32-NEXT:    addi sp, sp, 16
983; RV32-NEXT:    .cfi_def_cfa_offset 0
984; RV32-NEXT:    ret
985;
986; RV64-LABEL: vmaxu_vx_v16i64:
987; RV64:       # %bb.0:
988; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
989; RV64-NEXT:    vmaxu.vx v8, v8, a0, v0.t
990; RV64-NEXT:    ret
991  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
992  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
993  %v = call <16 x i64> @llvm.vp.umax.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl)
994  ret <16 x i64> %v
995}
996
997define <16 x i64> @vmaxu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %evl) {
998; RV32-LABEL: vmaxu_vx_v16i64_unmasked:
999; RV32:       # %bb.0:
1000; RV32-NEXT:    addi sp, sp, -16
1001; RV32-NEXT:    .cfi_def_cfa_offset 16
1002; RV32-NEXT:    sw a0, 8(sp)
1003; RV32-NEXT:    sw a1, 12(sp)
1004; RV32-NEXT:    addi a0, sp, 8
1005; RV32-NEXT:    vsetivli zero, 16, e64, m8, ta, ma
1006; RV32-NEXT:    vlse64.v v16, (a0), zero
1007; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma
1008; RV32-NEXT:    vmaxu.vv v8, v8, v16
1009; RV32-NEXT:    addi sp, sp, 16
1010; RV32-NEXT:    .cfi_def_cfa_offset 0
1011; RV32-NEXT:    ret
1012;
1013; RV64-LABEL: vmaxu_vx_v16i64_unmasked:
1014; RV64:       # %bb.0:
1015; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1016; RV64-NEXT:    vmaxu.vx v8, v8, a0
1017; RV64-NEXT:    ret
1018  %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0
1019  %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer
1020  %v = call <16 x i64> @llvm.vp.umax.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl)
1021  ret <16 x i64> %v
1022}
1023
1024; Test that split-legalization works as expected.
1025
1026declare <32 x i64> @llvm.vp.umax.v32i64(<32 x i64>, <32 x i64>, <32 x i1>, i32)
1027
1028define <32 x i64> @vmaxu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
1029; CHECK-LABEL: vmaxu_vx_v32i64:
1030; CHECK:       # %bb.0:
1031; CHECK-NEXT:    li a2, 16
1032; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
1033; CHECK-NEXT:    vslidedown.vi v24, v0, 2
1034; CHECK-NEXT:    mv a1, a0
1035; CHECK-NEXT:    bltu a0, a2, .LBB74_2
1036; CHECK-NEXT:  # %bb.1:
1037; CHECK-NEXT:    li a1, 16
1038; CHECK-NEXT:  .LBB74_2:
1039; CHECK-NEXT:    li a2, -1
1040; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma
1041; CHECK-NEXT:    vmaxu.vx v8, v8, a2, v0.t
1042; CHECK-NEXT:    addi a1, a0, -16
1043; CHECK-NEXT:    sltu a0, a0, a1
1044; CHECK-NEXT:    addi a0, a0, -1
1045; CHECK-NEXT:    and a0, a0, a1
1046; CHECK-NEXT:    vmv1r.v v0, v24
1047; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
1048; CHECK-NEXT:    vmaxu.vx v16, v16, a2, v0.t
1049; CHECK-NEXT:    ret
1050  %v = call <32 x i64> @llvm.vp.umax.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl)
1051  ret <32 x i64> %v
1052}
1053