xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll (revision 1cb599835ccf7ee8b2d1d5a7f3107e19a26fc6f5) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s
6
7define <2 x i1> @isnan_v2f16(<2 x half> %x, <2 x i1> %m, i32 zeroext %evl) {
8; CHECK-LABEL: isnan_v2f16:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
11; CHECK-NEXT:    vfclass.v v8, v8, v0.t
12; CHECK-NEXT:    li a0, 768
13; CHECK-NEXT:    vand.vx v8, v8, a0, v0.t
14; CHECK-NEXT:    vmsne.vi v0, v8, 0, v0.t
15; CHECK-NEXT:    ret
16  %1 = call <2 x i1> @llvm.vp.is.fpclass.v2f16(<2 x half> %x, i32 3, <2 x i1> %m, i32 %evl)  ; nan
17  ret <2 x i1> %1
18}
19
20define <2 x i1> @isnan_v2f16_unmasked(<2 x half> %x, i32 zeroext %evl) {
21; CHECK-LABEL: isnan_v2f16_unmasked:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
24; CHECK-NEXT:    vfclass.v v8, v8
25; CHECK-NEXT:    li a0, 768
26; CHECK-NEXT:    vand.vx v8, v8, a0
27; CHECK-NEXT:    vmsne.vi v0, v8, 0
28; CHECK-NEXT:    ret
29  %1 = call <2 x i1> @llvm.vp.is.fpclass.v2f16(<2 x half> %x, i32 3, <2 x i1> splat (i1 true), i32 %evl)  ; nan
30  ret <2 x i1> %1
31}
32
33define <2 x i1> @isnan_v2f32(<2 x float> %x, <2 x i1> %m, i32 zeroext %evl) {
34; CHECK-LABEL: isnan_v2f32:
35; CHECK:       # %bb.0:
36; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
37; CHECK-NEXT:    vfclass.v v8, v8, v0.t
38; CHECK-NEXT:    li a0, 927
39; CHECK-NEXT:    vand.vx v8, v8, a0, v0.t
40; CHECK-NEXT:    vmsne.vi v0, v8, 0, v0.t
41; CHECK-NEXT:    ret
42  %1 = call <2 x i1> @llvm.vp.is.fpclass.v2f32(<2 x float> %x, i32 639, <2 x i1> %m, i32 %evl)
43  ret <2 x i1> %1
44}
45
46define <2 x i1> @isnan_v2f32_unmasked(<2 x float> %x, i32 zeroext %evl) {
47; CHECK-LABEL: isnan_v2f32_unmasked:
48; CHECK:       # %bb.0:
49; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma
50; CHECK-NEXT:    vfclass.v v8, v8
51; CHECK-NEXT:    li a0, 927
52; CHECK-NEXT:    vand.vx v8, v8, a0
53; CHECK-NEXT:    vmsne.vi v0, v8, 0
54; CHECK-NEXT:    ret
55  %1 = call <2 x i1> @llvm.vp.is.fpclass.v2f32(<2 x float> %x, i32 639, <2 x i1> splat (i1 true), i32 %evl)
56  ret <2 x i1> %1
57}
58
59define <4 x i1> @isnan_v4f32(<4 x float> %x, <4 x i1> %m, i32 zeroext %evl) {
60; CHECK-LABEL: isnan_v4f32:
61; CHECK:       # %bb.0:
62; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
63; CHECK-NEXT:    vfclass.v v8, v8, v0.t
64; CHECK-NEXT:    li a0, 768
65; CHECK-NEXT:    vand.vx v8, v8, a0, v0.t
66; CHECK-NEXT:    vmsne.vi v0, v8, 0, v0.t
67; CHECK-NEXT:    ret
68  %1 = call <4 x i1> @llvm.vp.is.fpclass.v4f32(<4 x float> %x, i32 3, <4 x i1> %m, i32 %evl)  ; nan
69  ret <4 x i1> %1
70}
71
72define <4 x i1> @isnan_v4f32_unmasked(<4 x float> %x, i32 zeroext %evl) {
73; CHECK-LABEL: isnan_v4f32_unmasked:
74; CHECK:       # %bb.0:
75; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
76; CHECK-NEXT:    vfclass.v v8, v8
77; CHECK-NEXT:    li a0, 768
78; CHECK-NEXT:    vand.vx v8, v8, a0
79; CHECK-NEXT:    vmsne.vi v0, v8, 0
80; CHECK-NEXT:    ret
81  %1 = call <4 x i1> @llvm.vp.is.fpclass.v4f32(<4 x float> %x, i32 3, <4 x i1> splat (i1 true), i32 %evl)  ; nan
82  ret <4 x i1> %1
83}
84
85define <8 x i1> @isnan_v8f32(<8 x float> %x,  <8 x i1> %m, i32 zeroext %evl) {
86; CHECK-LABEL: isnan_v8f32:
87; CHECK:       # %bb.0:
88; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
89; CHECK-NEXT:    vfclass.v v10, v8, v0.t
90; CHECK-NEXT:    li a0, 512
91; CHECK-NEXT:    vmseq.vx v8, v10, a0, v0.t
92; CHECK-NEXT:    vmv1r.v v0, v8
93; CHECK-NEXT:    ret
94  %1 = call <8 x i1> @llvm.vp.is.fpclass.v8f32(<8 x float> %x, i32 2, <8 x i1> %m, i32 %evl)
95  ret <8 x i1> %1
96}
97
98define <8 x i1> @isnan_v8f32_unmasked(<8 x float> %x, i32 zeroext %evl) {
99; CHECK-LABEL: isnan_v8f32_unmasked:
100; CHECK:       # %bb.0:
101; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma
102; CHECK-NEXT:    vfclass.v v8, v8
103; CHECK-NEXT:    li a0, 512
104; CHECK-NEXT:    vmseq.vx v0, v8, a0
105; CHECK-NEXT:    ret
106  %1 = call <8 x i1> @llvm.vp.is.fpclass.v8f32(<8 x float> %x, i32 2, <8 x i1> splat (i1 true), i32 %evl)
107  ret <8 x i1> %1
108}
109
110define <16 x i1> @isnan_v16f32(<16 x float> %x, <16 x i1> %m, i32 zeroext %evl) {
111; CHECK-LABEL: isnan_v16f32:
112; CHECK:       # %bb.0:
113; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
114; CHECK-NEXT:    vfclass.v v12, v8, v0.t
115; CHECK-NEXT:    li a0, 256
116; CHECK-NEXT:    vmseq.vx v8, v12, a0, v0.t
117; CHECK-NEXT:    vmv1r.v v0, v8
118; CHECK-NEXT:    ret
119  %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f32(<16 x float> %x, i32 1, <16 x i1> %m, i32 %evl)
120  ret <16 x i1> %1
121}
122
123define <16 x i1> @isnan_v16f32_unmasked(<16 x float> %x, i32 zeroext %evl) {
124; CHECK-LABEL: isnan_v16f32_unmasked:
125; CHECK:       # %bb.0:
126; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma
127; CHECK-NEXT:    vfclass.v v8, v8
128; CHECK-NEXT:    li a0, 256
129; CHECK-NEXT:    vmseq.vx v0, v8, a0
130; CHECK-NEXT:    ret
131  %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f32(<16 x float> %x, i32 1, <16 x i1> splat (i1 true), i32 %evl)
132  ret <16 x i1> %1
133}
134
135define <2 x i1> @isnormal_v2f64(<2 x double> %x, <2 x i1> %m, i32 zeroext %evl) {
136; CHECK-LABEL: isnormal_v2f64:
137; CHECK:       # %bb.0:
138; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
139; CHECK-NEXT:    vfclass.v v8, v8, v0.t
140; CHECK-NEXT:    li a0, 129
141; CHECK-NEXT:    vand.vx v8, v8, a0, v0.t
142; CHECK-NEXT:    vmsne.vi v0, v8, 0, v0.t
143; CHECK-NEXT:    ret
144  %1 = call <2 x i1> @llvm.vp.is.fpclass.v2f64(<2 x double> %x, i32 516, <2 x i1> %m, i32 %evl) ; 0x204 = "inf"
145  ret <2 x i1> %1
146}
147
148define <2 x i1> @isnormal_v2f64_unmasked(<2 x double> %x, i32 zeroext %evl) {
149; CHECK-LABEL: isnormal_v2f64_unmasked:
150; CHECK:       # %bb.0:
151; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
152; CHECK-NEXT:    vfclass.v v8, v8
153; CHECK-NEXT:    li a0, 129
154; CHECK-NEXT:    vand.vx v8, v8, a0
155; CHECK-NEXT:    vmsne.vi v0, v8, 0
156; CHECK-NEXT:    ret
157  %1 = call <2 x i1> @llvm.vp.is.fpclass.v2f64(<2 x double> %x, i32 516, <2 x i1> splat (i1 true), i32 %evl) ; 0x204 = "inf"
158  ret <2 x i1> %1
159}
160
161define <4 x i1> @isposinf_v4f64(<4 x double> %x, <4 x i1> %m, i32 zeroext %evl) {
162; CHECK-LABEL: isposinf_v4f64:
163; CHECK:       # %bb.0:
164; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
165; CHECK-NEXT:    vfclass.v v10, v8, v0.t
166; CHECK-NEXT:    li a0, 128
167; CHECK-NEXT:    vmseq.vx v8, v10, a0, v0.t
168; CHECK-NEXT:    vmv1r.v v0, v8
169; CHECK-NEXT:    ret
170  %1 = call <4 x i1> @llvm.vp.is.fpclass.v4f64(<4 x double> %x, i32 512, <4 x i1> %m, i32 %evl) ; 0x200 = "+inf"
171  ret <4 x i1> %1
172}
173
174define <4 x i1> @isposinf_v4f64_unmasked(<4 x double> %x, i32 zeroext %evl) {
175; CHECK-LABEL: isposinf_v4f64_unmasked:
176; CHECK:       # %bb.0:
177; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
178; CHECK-NEXT:    vfclass.v v8, v8
179; CHECK-NEXT:    li a0, 128
180; CHECK-NEXT:    vmseq.vx v0, v8, a0
181; CHECK-NEXT:    ret
182  %1 = call <4 x i1> @llvm.vp.is.fpclass.v4f64(<4 x double> %x, i32 512, <4 x i1> splat (i1 true), i32 %evl) ; 0x200 = "+inf"
183  ret <4 x i1> %1
184}
185
186define <8 x i1> @isneginf_v8f64(<8 x double> %x, <8 x i1> %m, i32 zeroext %evl) {
187; CHECK-LABEL: isneginf_v8f64:
188; CHECK:       # %bb.0:
189; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
190; CHECK-NEXT:    vfclass.v v12, v8, v0.t
191; CHECK-NEXT:    vmseq.vi v8, v12, 1, v0.t
192; CHECK-NEXT:    vmv1r.v v0, v8
193; CHECK-NEXT:    ret
194  %1 = call <8 x i1> @llvm.vp.is.fpclass.v8f64(<8 x double> %x, i32 4, <8 x i1> %m, i32 %evl) ; "-inf"
195  ret <8 x i1> %1
196}
197
198define <8 x i1> @isneginf_v8f64_unmasked(<8 x double> %x, i32 zeroext %evl) {
199; CHECK-LABEL: isneginf_v8f64_unmasked:
200; CHECK:       # %bb.0:
201; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma
202; CHECK-NEXT:    vfclass.v v8, v8
203; CHECK-NEXT:    vmseq.vi v0, v8, 1
204; CHECK-NEXT:    ret
205  %1 = call <8 x i1> @llvm.vp.is.fpclass.v8f64(<8 x double> %x, i32 4, <8 x i1> splat (i1 true), i32 %evl) ; "-inf"
206  ret <8 x i1> %1
207}
208
209define <16 x i1> @isfinite_v16f64(<16 x double> %x, <16 x i1> %m, i32 zeroext %evl) {
210; CHECK-LABEL: isfinite_v16f64:
211; CHECK:       # %bb.0:
212; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
213; CHECK-NEXT:    vfclass.v v8, v8, v0.t
214; CHECK-NEXT:    li a0, 126
215; CHECK-NEXT:    vand.vx v16, v8, a0, v0.t
216; CHECK-NEXT:    vmsne.vi v8, v16, 0, v0.t
217; CHECK-NEXT:    vmv1r.v v0, v8
218; CHECK-NEXT:    ret
219  %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f64(<16 x double> %x, i32 504, <16 x i1> %m, i32 %evl) ; 0x1f8 = "finite"
220  ret <16 x i1> %1
221}
222
223define <16 x i1> @isfinite_v16f64_unmasked(<16 x double> %x, i32 zeroext %evl) {
224; CHECK-LABEL: isfinite_v16f64_unmasked:
225; CHECK:       # %bb.0:
226; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
227; CHECK-NEXT:    vfclass.v v8, v8
228; CHECK-NEXT:    li a0, 126
229; CHECK-NEXT:    vand.vx v8, v8, a0
230; CHECK-NEXT:    vmsne.vi v0, v8, 0
231; CHECK-NEXT:    ret
232  %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f64(<16 x double> %x, i32 504, <16 x i1> splat (i1 true), i32 %evl) ; 0x1f8 = "finite"
233  ret <16 x i1> %1
234}
235
236define <16 x i1> @isposfinite_v16f64(<16 x double> %x, <16 x i1> %m, i32 zeroext %evl) {
237; CHECK-LABEL: isposfinite_v16f64:
238; CHECK:       # %bb.0:
239; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
240; CHECK-NEXT:    vfclass.v v8, v8, v0.t
241; CHECK-NEXT:    li a0, 112
242; CHECK-NEXT:    vand.vx v16, v8, a0, v0.t
243; CHECK-NEXT:    vmsne.vi v8, v16, 0, v0.t
244; CHECK-NEXT:    vmv1r.v v0, v8
245; CHECK-NEXT:    ret
246  %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f64(<16 x double> %x, i32 448, <16 x i1> %m, i32 %evl) ; 0x1c0 = "+finite"
247  ret <16 x i1> %1
248}
249
250define <16 x i1> @isnegfinite_v16f64_unmasked(<16 x double> %x, i32 zeroext %evl) {
251; CHECK-LABEL: isnegfinite_v16f64_unmasked:
252; CHECK:       # %bb.0:
253; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
254; CHECK-NEXT:    vfclass.v v8, v8
255; CHECK-NEXT:    vand.vi v8, v8, 14
256; CHECK-NEXT:    vmsne.vi v0, v8, 0
257; CHECK-NEXT:    ret
258  %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f64(<16 x double> %x, i32 56, <16 x i1> splat (i1 true), i32 %evl) ; 0x38 = "-finite"
259  ret <16 x i1> %1
260}
261
262define <16 x i1> @isnotfinite_v16f64(<16 x double> %x, <16 x i1> %m, i32 zeroext %evl) {
263; CHECK-LABEL: isnotfinite_v16f64:
264; CHECK:       # %bb.0:
265; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
266; CHECK-NEXT:    vfclass.v v8, v8, v0.t
267; CHECK-NEXT:    li a0, 897
268; CHECK-NEXT:    vand.vx v16, v8, a0, v0.t
269; CHECK-NEXT:    vmsne.vi v8, v16, 0, v0.t
270; CHECK-NEXT:    vmv1r.v v0, v8
271; CHECK-NEXT:    ret
272  %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f64(<16 x double> %x, i32 519, <16 x i1> %m, i32 %evl) ; 0x207 = "inf|nan"
273  ret <16 x i1> %1
274}
275
276define <16 x i1> @isnotfinite_v16f64_unmasked(<16 x double> %x, i32 zeroext %evl) {
277; CHECK-LABEL: isnotfinite_v16f64_unmasked:
278; CHECK:       # %bb.0:
279; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma
280; CHECK-NEXT:    vfclass.v v8, v8
281; CHECK-NEXT:    li a0, 897
282; CHECK-NEXT:    vand.vx v8, v8, a0
283; CHECK-NEXT:    vmsne.vi v0, v8, 0
284; CHECK-NEXT:    ret
285  %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f64(<16 x double> %x, i32 519, <16 x i1> splat (i1 true), i32 %evl) ; 0x207 = "inf|nan"
286  ret <16 x i1> %1
287}
288
289declare <2 x i1> @llvm.vp.is.fpclass.v2f16(<2 x half>, i32, <2 x i1>, i32)
290declare <2 x i1> @llvm.vp.is.fpclass.v2f32(<2 x float>, i32, <2 x i1>, i32)
291declare <4 x i1> @llvm.vp.is.fpclass.v4f32(<4 x float>, i32, <4 x i1>, i32)
292declare <8 x i1> @llvm.vp.is.fpclass.v8f32(<8 x float>, i32, <8 x i1>, i32)
293declare <16 x i1> @llvm.vp.is.fpclass.v16f32(<16 x float>, i32, <16 x i1>, i32)
294declare <2 x i1> @llvm.vp.is.fpclass.v2f64(<2 x double>, i32, <2 x i1>, i32)
295declare <4 x i1> @llvm.vp.is.fpclass.v4f64(<4 x double>, i32, <4 x i1>, i32)
296declare <8 x i1> @llvm.vp.is.fpclass.v8f64(<8 x double>, i32, <8 x i1>, i32)
297declare <16 x i1> @llvm.vp.is.fpclass.v16f64(<16 x double>, i32, <16 x i1>, i32)
298