1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh < %s \ 3; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFH 4; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh < %s \ 5; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFH 6; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin < %s \ 7; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFHMIN 8; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin < %s \ 9; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFHMIN 10 11declare <4 x half> @llvm.vp.uitofp.v4f16.v4i7(<4 x i7>, <4 x i1>, i32) 12 13define <4 x half> @vuitofp_v4f16_v4i7(<4 x i7> %va, <4 x i1> %m, i32 zeroext %evl) { 14; ZVFH-LABEL: vuitofp_v4f16_v4i7: 15; ZVFH: # %bb.0: 16; ZVFH-NEXT: li a1, 127 17; ZVFH-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 18; ZVFH-NEXT: vand.vx v9, v8, a1 19; ZVFH-NEXT: vsetvli zero, a0, e8, mf4, ta, ma 20; ZVFH-NEXT: vfwcvt.f.xu.v v8, v9, v0.t 21; ZVFH-NEXT: ret 22; 23; ZVFHMIN-LABEL: vuitofp_v4f16_v4i7: 24; ZVFHMIN: # %bb.0: 25; ZVFHMIN-NEXT: li a1, 127 26; ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf4, ta, ma 27; ZVFHMIN-NEXT: vand.vx v8, v8, a1 28; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 29; ZVFHMIN-NEXT: vzext.vf2 v9, v8, v0.t 30; ZVFHMIN-NEXT: vfwcvt.f.xu.v v10, v9, v0.t 31; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 32; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 33; ZVFHMIN-NEXT: ret 34 %v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i7(<4 x i7> %va, <4 x i1> %m, i32 %evl) 35 ret <4 x half> %v 36} 37 38declare <4 x half> @llvm.vp.uitofp.v4f16.v4i8(<4 x i8>, <4 x i1>, i32) 39 40define <4 x half> @vuitofp_v4f16_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { 41; ZVFH-LABEL: vuitofp_v4f16_v4i8: 42; ZVFH: # %bb.0: 43; ZVFH-NEXT: vsetvli zero, a0, e8, mf4, ta, ma 44; ZVFH-NEXT: vfwcvt.f.xu.v v9, v8, v0.t 45; ZVFH-NEXT: vmv1r.v v8, v9 46; ZVFH-NEXT: ret 47; 48; ZVFHMIN-LABEL: vuitofp_v4f16_v4i8: 49; ZVFHMIN: # %bb.0: 50; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 51; ZVFHMIN-NEXT: vzext.vf2 v9, v8, v0.t 52; ZVFHMIN-NEXT: vfwcvt.f.xu.v v10, v9, v0.t 53; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 54; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 55; ZVFHMIN-NEXT: ret 56 %v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl) 57 ret <4 x half> %v 58} 59 60define <4 x half> @vuitofp_v4f16_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { 61; ZVFH-LABEL: vuitofp_v4f16_v4i8_unmasked: 62; ZVFH: # %bb.0: 63; ZVFH-NEXT: vsetvli zero, a0, e8, mf4, ta, ma 64; ZVFH-NEXT: vfwcvt.f.xu.v v9, v8 65; ZVFH-NEXT: vmv1r.v v8, v9 66; ZVFH-NEXT: ret 67; 68; ZVFHMIN-LABEL: vuitofp_v4f16_v4i8_unmasked: 69; ZVFHMIN: # %bb.0: 70; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 71; ZVFHMIN-NEXT: vzext.vf2 v9, v8 72; ZVFHMIN-NEXT: vfwcvt.f.xu.v v10, v9 73; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 74; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 75; ZVFHMIN-NEXT: ret 76 %v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl) 77 ret <4 x half> %v 78} 79 80declare <4 x half> @llvm.vp.uitofp.v4f16.v4i16(<4 x i16>, <4 x i1>, i32) 81 82define <4 x half> @vuitofp_v4f16_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { 83; ZVFH-LABEL: vuitofp_v4f16_v4i16: 84; ZVFH: # %bb.0: 85; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 86; ZVFH-NEXT: vfcvt.f.xu.v v8, v8, v0.t 87; ZVFH-NEXT: ret 88; 89; ZVFHMIN-LABEL: vuitofp_v4f16_v4i16: 90; ZVFHMIN: # %bb.0: 91; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 92; ZVFHMIN-NEXT: vfwcvt.f.xu.v v9, v8, v0.t 93; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 94; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 95; ZVFHMIN-NEXT: ret 96 %v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl) 97 ret <4 x half> %v 98} 99 100define <4 x half> @vuitofp_v4f16_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { 101; ZVFH-LABEL: vuitofp_v4f16_v4i16_unmasked: 102; ZVFH: # %bb.0: 103; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 104; ZVFH-NEXT: vfcvt.f.xu.v v8, v8 105; ZVFH-NEXT: ret 106; 107; ZVFHMIN-LABEL: vuitofp_v4f16_v4i16_unmasked: 108; ZVFHMIN: # %bb.0: 109; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 110; ZVFHMIN-NEXT: vfwcvt.f.xu.v v9, v8 111; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 112; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 113; ZVFHMIN-NEXT: ret 114 %v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl) 115 ret <4 x half> %v 116} 117 118declare <4 x half> @llvm.vp.uitofp.v4f16.v4i32(<4 x i32>, <4 x i1>, i32) 119 120define <4 x half> @vuitofp_v4f16_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { 121; ZVFH-LABEL: vuitofp_v4f16_v4i32: 122; ZVFH: # %bb.0: 123; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 124; ZVFH-NEXT: vfncvt.f.xu.w v9, v8, v0.t 125; ZVFH-NEXT: vmv1r.v v8, v9 126; ZVFH-NEXT: ret 127; 128; ZVFHMIN-LABEL: vuitofp_v4f16_v4i32: 129; ZVFHMIN: # %bb.0: 130; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma 131; ZVFHMIN-NEXT: vfcvt.f.xu.v v9, v8, v0.t 132; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 133; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 134; ZVFHMIN-NEXT: ret 135 %v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl) 136 ret <4 x half> %v 137} 138 139define <4 x half> @vuitofp_v4f16_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { 140; ZVFH-LABEL: vuitofp_v4f16_v4i32_unmasked: 141; ZVFH: # %bb.0: 142; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 143; ZVFH-NEXT: vfncvt.f.xu.w v9, v8 144; ZVFH-NEXT: vmv1r.v v8, v9 145; ZVFH-NEXT: ret 146; 147; ZVFHMIN-LABEL: vuitofp_v4f16_v4i32_unmasked: 148; ZVFHMIN: # %bb.0: 149; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma 150; ZVFHMIN-NEXT: vfcvt.f.xu.v v9, v8 151; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 152; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 153; ZVFHMIN-NEXT: ret 154 %v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl) 155 ret <4 x half> %v 156} 157 158declare <4 x half> @llvm.vp.uitofp.v4f16.v4i64(<4 x i64>, <4 x i1>, i32) 159 160define <4 x half> @vuitofp_v4f16_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { 161; ZVFH-LABEL: vuitofp_v4f16_v4i64: 162; ZVFH: # %bb.0: 163; ZVFH-NEXT: vsetvli zero, a0, e32, m1, ta, ma 164; ZVFH-NEXT: vfncvt.f.xu.w v10, v8, v0.t 165; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma 166; ZVFH-NEXT: vfncvt.f.f.w v8, v10, v0.t 167; ZVFH-NEXT: ret 168; 169; ZVFHMIN-LABEL: vuitofp_v4f16_v4i64: 170; ZVFHMIN: # %bb.0: 171; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma 172; ZVFHMIN-NEXT: vfncvt.f.xu.w v10, v8, v0.t 173; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 174; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 175; ZVFHMIN-NEXT: ret 176 %v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl) 177 ret <4 x half> %v 178} 179 180define <4 x half> @vuitofp_v4f16_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { 181; ZVFH-LABEL: vuitofp_v4f16_v4i64_unmasked: 182; ZVFH: # %bb.0: 183; ZVFH-NEXT: vsetvli zero, a0, e32, m1, ta, ma 184; ZVFH-NEXT: vfncvt.f.xu.w v10, v8 185; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma 186; ZVFH-NEXT: vfncvt.f.f.w v8, v10 187; ZVFH-NEXT: ret 188; 189; ZVFHMIN-LABEL: vuitofp_v4f16_v4i64_unmasked: 190; ZVFHMIN: # %bb.0: 191; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma 192; ZVFHMIN-NEXT: vfncvt.f.xu.w v10, v8 193; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma 194; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 195; ZVFHMIN-NEXT: ret 196 %v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl) 197 ret <4 x half> %v 198} 199 200declare <4 x float> @llvm.vp.uitofp.v4f32.v4i8(<4 x i8>, <4 x i1>, i32) 201 202define <4 x float> @vuitofp_v4f32_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { 203; CHECK-LABEL: vuitofp_v4f32_v4i8: 204; CHECK: # %bb.0: 205; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 206; CHECK-NEXT: vzext.vf2 v9, v8, v0.t 207; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t 208; CHECK-NEXT: ret 209 %v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl) 210 ret <4 x float> %v 211} 212 213define <4 x float> @vuitofp_v4f32_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { 214; CHECK-LABEL: vuitofp_v4f32_v4i8_unmasked: 215; CHECK: # %bb.0: 216; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 217; CHECK-NEXT: vzext.vf2 v9, v8 218; CHECK-NEXT: vfwcvt.f.xu.v v8, v9 219; CHECK-NEXT: ret 220 %v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl) 221 ret <4 x float> %v 222} 223 224declare <4 x float> @llvm.vp.uitofp.v4f32.v4i16(<4 x i16>, <4 x i1>, i32) 225 226define <4 x float> @vuitofp_v4f32_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { 227; CHECK-LABEL: vuitofp_v4f32_v4i16: 228; CHECK: # %bb.0: 229; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 230; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t 231; CHECK-NEXT: vmv1r.v v8, v9 232; CHECK-NEXT: ret 233 %v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl) 234 ret <4 x float> %v 235} 236 237define <4 x float> @vuitofp_v4f32_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { 238; CHECK-LABEL: vuitofp_v4f32_v4i16_unmasked: 239; CHECK: # %bb.0: 240; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma 241; CHECK-NEXT: vfwcvt.f.xu.v v9, v8 242; CHECK-NEXT: vmv1r.v v8, v9 243; CHECK-NEXT: ret 244 %v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl) 245 ret <4 x float> %v 246} 247 248declare <4 x float> @llvm.vp.uitofp.v4f32.v4i32(<4 x i32>, <4 x i1>, i32) 249 250define <4 x float> @vuitofp_v4f32_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { 251; CHECK-LABEL: vuitofp_v4f32_v4i32: 252; CHECK: # %bb.0: 253; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 254; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t 255; CHECK-NEXT: ret 256 %v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl) 257 ret <4 x float> %v 258} 259 260define <4 x float> @vuitofp_v4f32_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { 261; CHECK-LABEL: vuitofp_v4f32_v4i32_unmasked: 262; CHECK: # %bb.0: 263; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 264; CHECK-NEXT: vfcvt.f.xu.v v8, v8 265; CHECK-NEXT: ret 266 %v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl) 267 ret <4 x float> %v 268} 269 270declare <4 x float> @llvm.vp.uitofp.v4f32.v4i64(<4 x i64>, <4 x i1>, i32) 271 272define <4 x float> @vuitofp_v4f32_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { 273; CHECK-LABEL: vuitofp_v4f32_v4i64: 274; CHECK: # %bb.0: 275; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 276; CHECK-NEXT: vfncvt.f.xu.w v10, v8, v0.t 277; CHECK-NEXT: vmv.v.v v8, v10 278; CHECK-NEXT: ret 279 %v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl) 280 ret <4 x float> %v 281} 282 283define <4 x float> @vuitofp_v4f32_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { 284; CHECK-LABEL: vuitofp_v4f32_v4i64_unmasked: 285; CHECK: # %bb.0: 286; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 287; CHECK-NEXT: vfncvt.f.xu.w v10, v8 288; CHECK-NEXT: vmv.v.v v8, v10 289; CHECK-NEXT: ret 290 %v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl) 291 ret <4 x float> %v 292} 293 294declare <4 x double> @llvm.vp.uitofp.v4f64.v4i8(<4 x i8>, <4 x i1>, i32) 295 296define <4 x double> @vuitofp_v4f64_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { 297; CHECK-LABEL: vuitofp_v4f64_v4i8: 298; CHECK: # %bb.0: 299; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 300; CHECK-NEXT: vzext.vf4 v10, v8, v0.t 301; CHECK-NEXT: vfwcvt.f.xu.v v8, v10, v0.t 302; CHECK-NEXT: ret 303 %v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl) 304 ret <4 x double> %v 305} 306 307define <4 x double> @vuitofp_v4f64_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { 308; CHECK-LABEL: vuitofp_v4f64_v4i8_unmasked: 309; CHECK: # %bb.0: 310; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 311; CHECK-NEXT: vzext.vf4 v10, v8 312; CHECK-NEXT: vfwcvt.f.xu.v v8, v10 313; CHECK-NEXT: ret 314 %v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl) 315 ret <4 x double> %v 316} 317 318declare <4 x double> @llvm.vp.uitofp.v4f64.v4i16(<4 x i16>, <4 x i1>, i32) 319 320define <4 x double> @vuitofp_v4f64_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { 321; CHECK-LABEL: vuitofp_v4f64_v4i16: 322; CHECK: # %bb.0: 323; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 324; CHECK-NEXT: vzext.vf2 v10, v8, v0.t 325; CHECK-NEXT: vfwcvt.f.xu.v v8, v10, v0.t 326; CHECK-NEXT: ret 327 %v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl) 328 ret <4 x double> %v 329} 330 331define <4 x double> @vuitofp_v4f64_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { 332; CHECK-LABEL: vuitofp_v4f64_v4i16_unmasked: 333; CHECK: # %bb.0: 334; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 335; CHECK-NEXT: vzext.vf2 v10, v8 336; CHECK-NEXT: vfwcvt.f.xu.v v8, v10 337; CHECK-NEXT: ret 338 %v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl) 339 ret <4 x double> %v 340} 341 342declare <4 x double> @llvm.vp.uitofp.v4f64.v4i32(<4 x i32>, <4 x i1>, i32) 343 344define <4 x double> @vuitofp_v4f64_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { 345; CHECK-LABEL: vuitofp_v4f64_v4i32: 346; CHECK: # %bb.0: 347; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 348; CHECK-NEXT: vfwcvt.f.xu.v v10, v8, v0.t 349; CHECK-NEXT: vmv2r.v v8, v10 350; CHECK-NEXT: ret 351 %v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl) 352 ret <4 x double> %v 353} 354 355define <4 x double> @vuitofp_v4f64_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { 356; CHECK-LABEL: vuitofp_v4f64_v4i32_unmasked: 357; CHECK: # %bb.0: 358; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma 359; CHECK-NEXT: vfwcvt.f.xu.v v10, v8 360; CHECK-NEXT: vmv2r.v v8, v10 361; CHECK-NEXT: ret 362 %v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl) 363 ret <4 x double> %v 364} 365 366declare <4 x double> @llvm.vp.uitofp.v4f64.v4i64(<4 x i64>, <4 x i1>, i32) 367 368define <4 x double> @vuitofp_v4f64_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { 369; CHECK-LABEL: vuitofp_v4f64_v4i64: 370; CHECK: # %bb.0: 371; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma 372; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t 373; CHECK-NEXT: ret 374 %v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl) 375 ret <4 x double> %v 376} 377 378define <4 x double> @vuitofp_v4f64_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { 379; CHECK-LABEL: vuitofp_v4f64_v4i64_unmasked: 380; CHECK: # %bb.0: 381; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma 382; CHECK-NEXT: vfcvt.f.xu.v v8, v8 383; CHECK-NEXT: ret 384 %v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl) 385 ret <4 x double> %v 386} 387 388declare <32 x double> @llvm.vp.uitofp.v32f64.v32i64(<32 x i64>, <32 x i1>, i32) 389 390define <32 x double> @vuitofp_v32f64_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) { 391; CHECK-LABEL: vuitofp_v32f64_v32i64: 392; CHECK: # %bb.0: 393; CHECK-NEXT: li a2, 16 394; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma 395; CHECK-NEXT: vslidedown.vi v24, v0, 2 396; CHECK-NEXT: mv a1, a0 397; CHECK-NEXT: bltu a0, a2, .LBB25_2 398; CHECK-NEXT: # %bb.1: 399; CHECK-NEXT: li a1, 16 400; CHECK-NEXT: .LBB25_2: 401; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma 402; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t 403; CHECK-NEXT: addi a1, a0, -16 404; CHECK-NEXT: sltu a0, a0, a1 405; CHECK-NEXT: addi a0, a0, -1 406; CHECK-NEXT: and a0, a0, a1 407; CHECK-NEXT: vmv1r.v v0, v24 408; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma 409; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t 410; CHECK-NEXT: ret 411 %v = call <32 x double> @llvm.vp.uitofp.v32f64.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl) 412 ret <32 x double> %v 413} 414 415define <32 x double> @vuitofp_v32f64_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { 416; CHECK-LABEL: vuitofp_v32f64_v32i64_unmasked: 417; CHECK: # %bb.0: 418; CHECK-NEXT: li a2, 16 419; CHECK-NEXT: mv a1, a0 420; CHECK-NEXT: bltu a0, a2, .LBB26_2 421; CHECK-NEXT: # %bb.1: 422; CHECK-NEXT: li a1, 16 423; CHECK-NEXT: .LBB26_2: 424; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma 425; CHECK-NEXT: vfcvt.f.xu.v v8, v8 426; CHECK-NEXT: addi a1, a0, -16 427; CHECK-NEXT: sltu a0, a0, a1 428; CHECK-NEXT: addi a0, a0, -1 429; CHECK-NEXT: and a0, a0, a1 430; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma 431; CHECK-NEXT: vfcvt.f.xu.v v16, v16 432; CHECK-NEXT: ret 433 %v = call <32 x double> @llvm.vp.uitofp.v32f64.v32i64(<32 x i64> %va, <32 x i1> splat (i1 true), i32 %evl) 434 ret <32 x double> %v 435} 436